ICS9222-01 [ICSI]
Dual Memory Clock Generator; 双内存时钟发生器
| 型号： | ICS9222-01 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Dual Memory Clock Generator |
| 文件： | 总6页 (文件大小：94K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated
Circuit
Systems, Inc.
ICS9222-01
Dual Memory Clock Generator
General Description
Features
•
•
Compatible with all Direct Rambus™ based ICs
The ICS9222-01 is a High-speed clock generator providing
two channels up to 450 MHz differential clock source for
direct Rambus_memory system. It includes two independent
DDLL’s (Distributed Delay locked loop) and phase detection
mechanisms to synchronize eachdirect Rambus_ channel
clock to an external system clock. ICS9222-01 provides a
solution for a broad range of Direct Rambus memory
applications. The device works in conjunction with the
ICS964S101, as well as 9250-22 and others (depending on
chipset).
Up to 450 MHz differential clock source for direct
Rambus™ memory system
Cycle to cycle jitter is less than 100 ps
3.3 ± 5% supply
•
•
•
Synchronization flexibility: Supports systems that need
clock domains of Rambus channel to synchronize with
system or processor clock, or systems that do not
require synchronization of the Rambus clock to another
system clock.
The ICS9222-01 power management support system turns
“off” the Rambus channel clock to minimize power
consumption for mobile and other power sensitive
applications. In “clock off” mode the device remains “on”
while the output is disabled, allowing fast transitions between
clock-off and clock–on states. In “power down” mode it
completely powers down for minimum power dissipation.
•
•
Excellent power management support
REFCLK input is from the main clock generator such as
a 9250-22.
Pin Configuration
Block Diagram
CLK_STOP#
PD#
VDDREF
REFCLK
VDDC
SYNCLK0
PCLK0
GND
VDDP
GND
SYNCLK1
PCLK1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
FS0
FS1
FS2
GND
CLKB0
CLK0
VDDCLK
VDDCLK
CLK1
CLKB1
GND
MULT_0
MULT_1
MULT_2
Test MUX
FS (2:0)
Bypass MUX
Bypclk
GND
PLLclk
PCLK1
SYNCLK1
Phase
Detector
CLK1
Phase
Aligner
CLKB1
REFCLK
B
A
GND
PLL
VDDC
CLK0
Phase
Aligner
CLKB0
VDDIPD
CLK_STOP#
PD#
MULT (2:0)
2
Phase
Detector
GND
PAclk
PCLK0
SYNCLK0
28-Pin TSSOP
0274C—11/14/05
ICS9222-01
Pin Descriptions
Pin #
1, 7, 21, 22
2
3, 11
6, 8, 18, 25
Name
VDD
REFCLK
VDDC
GND
Type
PWR
IN
PWR
PWR
Description
3.3 V power supply
Reference clock
Power for phase aligners
Ground
Phase controller input, used to drive a phase aligner
that adjusts the phase of the busclk.
Voltage for phase detector inputs
Active low output enable/disable for CLK/CLKB
3.3V CMOS active low power down, the device is
powered down when the "(PD#) =0"
3.3V CMOS PLL Multiplier select, logic for selecting the
multiply ratio for the PLL from the input REFCLK
Clock output Complement
4, 5, 9, 10
PCLK, SYNCLK
IN
12
13
VDDIPD
CLK_ STOP#
PWR
IN
14
PD#
IN
IN
15, 16, 17
MULT (2:0)
19, 24
20, 23
CLKB (1:0)
CLK (1:0)
OUT
OUT
Clock output
3.3V CMOS Mode control, used in selecting bypass,
test, normal, and output test (OE)
26, 27, 28
FS (2:0)
IN
0274C—11/14/05
2
ICS9222-01
PLL Divider Selection and PLL Values (PLLCLK=REFCLK*A/B)
CLK(1:0)/CL
KB(1:0) w/
REFCLK=
50MHz
CLK(1:0)/CL
KB(1:0) w/
REFCLK=
66MHz
MULT_0 MULT_1 MULT_2
A
B
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
4
9
6
9
8
16
8
10
1
2
1
1
3
3
1
1
Reserved
Reserved
300
267MHz
300
400
Reserved
Reserved
356
Reserved
Reserved
450
Reserved
Reserved
400
Reserved
Bypass and Test Mode Select
FS0
0
FS1
0
FS2
0
MODE
Normal
CLK (1:0)
CLK
CLKB (1:0)
CLKB
0
0
1
Supplier Test
Reserved
Reserved
0
0
1
1
0
1
OE
OE
Tristate
Tristate
Tristate
Tristate
Non-aligned
CLK
Non-aligned
CLKB
1
0
0
Bypass
1
1
1
0
1
1
1
0
1
Supplier Test
Test
Reserved
Reserved
REFCLK
Reserved
Reserved
REFCLKB
Reserved
0274C—11/14/05
3
ICS9222-01
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.0 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
Electrical Characteristics - Input / Supply / Outputs
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-10% (unless otherwise stated)
PARAMETER
SYMBOL
VDD
MIN
MAX
UNIT
V
Supply Voltage
3.135 3.465
REFCLK Input cycle time
tCYCLE,IN
tJ,IN
10
-
40
250
60%
33
ns
Input Cycle-to-Cycle Jitter
ps
Input Duty Cycle over 10K cycles
Input frequency of modulation
Modulation index
DCIN
40%
30
tCYCLE
kHz
%
FM,IN
PM,IN
0.25
30
0.5
Phase detector input cycle time at PCLK (1:0) & SYNCLK (1:0)
Initial phase error at phase detector inputs
tCYCLE,PD
terr,init
100
0.5
ns
-0.5
25%
tCYCLE,PD
Phase detector input duty cycle over 10K cycles
Input rise & fall times (measured at 20%-80% of input voltage)
for PCLK (1:0), SYNCLK (1:0) & REFCLK
DCIN,PD
75% tCYCLE,PD
tIR, tIF
CIN,PD
∆CIN,PD
CIN,CMOS
VIL
-
-
1
7
ns
pF
Input capacitance at PCLK (1:0) & SYNCLK (1:0) & REFCLK
Input capacitance matching at PCLK (1:0) & SYNCLK (1:0)
Input capacitance at CMOS pins
-
0.5
10
0.3
-
pF
-
pF
Input (CMOS) signal low voltage
-
VDD
VDD
VDD,IR
VDD,IR
VDD,IPD
VDD,IPD
V
Input (CMOS) signal high voltage
VIH
0.7
-
REFCLK input low voltage
VIL,R
0.3
-
REFCLK input high voltage
VIH,R
0.7
-
Input signal low voltage for PD inputs and STOP_CLK
Input signal high voltage for PD inputs and STOP_CLK
Input supply reference for REFCLK
VIL,R
0.3
-
VIH,R
0.7
VDD,IR
VDD,IPD
1.235 3.465
1.235 3.465
Input supply reference for PD inputs
V
Phase detector phase error for distributed loop measured at
PCLK (1:0) & SYNCLK (1:0)
tERR,PD
tCYCLE
tJ
-100
2.5
-
100
3.75
60
ps
ns
Clock Cycle time
Cycle-to-cycle jitter at CLK (1:0) & CLKB (1:0)
Total jitter over 2 ,3 or 4 cycles
Phase aligner phase step size CLK (1:0) & CLKB (1:0)
PLL output phase error when tracking SSC
Output crossing-point voltage
ps
tJ
-
100
-
ps
tSTEP
tERR,SSC
VX
1
ps
-100
1.3
1.1
0.4
1
100
1.8
2
ps
V
Output voltage during Clk Stop (CLK_STOP#=0)
Output Voltage swing
VX,STOP
VCOS
VOL
V
1
V
Output low voltage
-
V
Output high voltage
VOH
-
2.35
60%
50
V
Output duty cycle over 10K cycles
DC
40%
-
tCYCLE
ps
Output cycle-to-cycle duty cycle error
tDC,ERR
Output rise & fall times (measured at 20%-80% of input voltage)
for PCLK (1:0), SYNCLK (1:0) & REFCLK
tCR,tCF
tCR,CF
300
-
500
100
250
ps
ps
Difference between rise and fall times on a single device (20%-80%)
Operating Supply Current 400MHz
mA
0274C—11/14/05
4
ICS9222-01
c
N
In Millimeters
In Inches
L
SYMBOL
COMMON DIMENSIONS COMMON DIMENSIONS
MIN
--
0.05
0.80
0.19
0.09
MAX
1.20
0.15
1.05
0.30
0.20
MIN
--
.002
.032
.007
.0035
SEE VARIATIONS
0.252 BASIC
.169
MAX
.047
.006
.041
.012
.008
E1
E
A
A1
A2
b
c
D
E
E1
e
INDEX
AREA
1
2
SEE VARIATIONS
6.40 BASIC
4.30
α
D
4.50
.177
0.65 BASIC
0.0256 BASIC
L
0.45
0.75
.018
.030
N
SEE VARIATIONS
SEE VARIATIONS
α
aaa
0°
--
8°
0.10
0°
--
8°
.004
A
A2
A1
VARIATIONS
- CC --
D mm.
D (inch)
N
e
SEATING
PLANE
MIN
9.60
MAX
9.80
MIN
.378
MAX
.386
b
28
Reference Doc.: JEDEC Publication 95, MO-153
aaa
C
10-0035
4.40 mm. Body, 0.65 mm. pitch TSSOP
(0.0256 Inch)
(173 mil)
Ordering Information
ICS9222yG-01LF-T
Example:
ICS XXXX y G - PPP LF - T
Designation for tape and reel packaging
Lead Free, RoHS Compliant (Optional)
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
G=TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
0274C—11/14/05
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
5
information being relied upon by the customer is current and accurate.
ICS9222-01
Revision History
Rev.
Issue Date Description
Page #
C
11/14/2005 Added LF to Ordering Information
5
0274C—11/14/05
6
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