ICS9248-103 [ICSI]
Frequency Generator & Integrated Buffers for PENTIUM/ProTM; 频率发生器和缓冲器集成奔腾/ ProTM
| 型号： | ICS9248-103 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Frequency Generator & Integrated Buffers for PENTIUM/ProTM |
| 文件： | 总16页 (文件大小：393K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated
Circuit
Systems, Inc.
ICS9248-103
Frequency Generator & Integrated Buffers for PENTIUM/ProTM
General Description
Features
Up to 137MHz frequency support
The ICS9248-103 is the single chip clock solution for
Notebook designs using the 440BX or the VIAApollo Pro 133
style chipset. It provides all necessary clock signals for such a
system.
Spread Spectrum for EMI control
Serial I2C interface for Power Management,
Frequency Select, Spread Spectrum
Provides the following system clocks
- 4-CPUs@2.5/3.3V, upto137MHz
(includingCPUCLK_F)
Spread spectrum may be enabled through I2C programming.
Spread spectrum typically reduces system EMI by 8dB to
10dB. This simplifies EMI qualification without resorting to
board design iterations or costly shielding. The ICS9248-103
employs a proprietary closed loop design, which tightly
controls the percentage of spreading over process and
temperature variations.
- 9-SDRAMs @3.3V, upto137MHz
(including SDRAM_F)
- 8-PCI@3.3V, CPU/2orCPU/3
(including 3 free running PCICLK_Fs)
- 1-24/48MHz@3.3V
-1-48MHz@3.3Vfixed
- 2-REF@3.3V,14.318MHz.
Efficient Power management scheme through PCI
andSTOPCLOCKS
Spread Spectrum ± .25%, & 0 to -0.5% down spread
Block Diagram
Pin Configuration
48-Pin SSOP
* Internal Pull-up Resistor of 120K to VDD
Power Groups
VDDLCPU,GNDLCPU=CPUCLK[2:0],CPUCLK_F
VDDSDR,GNDSDR=SDRAMCLKS[7:0],SDRAM_F
VDDPCI,GNDPCI=PCICLKS[6:0],PCICLK_F
VDD48,GND48=48MHz,24MHz
VDDREF,GNDREF=REF,X1,X2
VDDCOR=PLLCORE
Pentium is a trademark of Intel Corporation
I2C is a trademark of Philips Corporation
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
9248-103RevC 10/14/99
information being relied upon by the customer is current and accurate.
ICS9248-103
Pin Descriptions
PIN NUMBER
PIN NAME
TYPE
DESCRIPTION
1
VDDREF
PWR Ref, XTAL power supply, nominal 3.3V
14.318 Mhz reference clock.This REF output is the STRONGER
buffer for ISA BUS loads
2
REF0
OUT
Halts PCICLK [4:0]clocks at logic 0 level, when input low (In
mobile mode, MODE=0)
20
PCI_STOP#
GND
IN
3, 9, 16,
33, 40, 44
PWR Ground
Crystal input, has internal load cap (36pF) and feedback
resistor from X2
4
X1
IN
5
X2
OUT Crystal output, nominally 14.318MHz.
6,14
VDDPCI
PWR Supply for PCICLK_F and PCICLK [6:0], nominal 3.3V
Indicates whether VDDLCPU is 2.5 or 3.3V. High=2.5V CPU,
LOW=3.3V CPU. Latched Input.
CPU2.5_3.3#1,2
IN
7
8
Free running PCI clock not affected by PCI_STOP# for power
management.
Frequency select pin. Latched Input.
Free running PCI clock not affected by PCI_STOP# for power
management.
Selects either 24 or 48MHz when Low = 48MHz
Free running PCI clock not affected by PCI_STOP# for power
management.
PCI clock output Synchronous to CPU clocks with 1-4ns skew (CPU
early)
PCICLK_F0
FS31,2
OUT
IN
OUT
IN
PCICLK_F1
SEL24_48#MHz1,2
PCICLK_F2
10
11
OUT
PCICLK1
OUT
18, 17, 13,
12
PCI clock outputs. Synchronous to CPU clocks with 1-4ns skew
(CPU early)
Input to Fanout Buffers for SDRAM outputs.
PCICLK [5:2]
OUT
IN
15
19
BUFFER IN
VDDCOR
PWR Power pin for the PLL core. 3.3V
Asynchronous active low input pin used to power down the
device into a low power state. The internal clocks are disabled
21
PD#1
IN
and the VCO and the crystal are stopped. The latency of the
power down will not be greater than 4ms.
22
GND48
PWR Ground pin for 24 & 48MHz output buffers & fixed PLL core.
28, 29, 31, 32,
34, 35, 37, 38
SDRAM clock outputs, Fanout Buffer outputs from BUFFER IN pin
(controlled by chipset).
SDRAM [7:0]
OUT
30, 36
23
VDDSDR
SDATA
SCLK
PWR Supply for SDRAM [7:0] and CPU PLL Core, nominal 3.3V.
IN
IN
Data input for I2C serial input, 5V tolerant input
Clock input of I2C input, 5V tolerant input
24
24_48MHz
FS11, 2
OUT 24MHz or 48MHz output clock selectable by pin 10
IN Frequency select pin. Latched Input.
OUT 48MHz output clock
25
26
48MHz
FS01, 2
IN
Frequency select pin. Latched Input
27
39
VDD48
SDRAM_F
PWR Power for 24 & 48MHz output buffers and fixed PLL core.
OUT Free running SDRAM clock output. Not affected by CPU_STOP#
This asynchronous input halts CPUCLK & SDRAM (0:7) at logic
"0" level when driven low.
41
CLK_STOP#
IN
42, 43, 45
CPUCLK [2:0]
CPUCLK_F
VDDLCPU
REF1
OUT CPU clock outputs, powered by VDDLCPU
OUT Free running CPU clock. Not affected by the CPU_STOP#
PWR Supply for CPU clocks 2.5V
46
47
OUT 14.318 MHz reference clock.
48
FS21, 2
IN
Frequency select pin. Latched Input
Notes:
1: Internal Pull-up Resistor of 120K to 3.3V on indicated inputs
2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor
to program logic Hi to VDD or GND for logic low.
2
ICS9248-103
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
For more information, contact ICS for an I2C programming application note.
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
How to Read:
Controller (host) will send start bit.
Controller (host) sends the read address D3 (H)
ICS clock will acknowledge
Controller (host) sends a dummy command code
ICS clock will acknowledge
ICS clock will send the byte count
Controller (host) acknowledges
Controller (host) sends a dummy byte count
ICS clock will acknowledge
Controller (host) starts sending first byte (Byte 0)
through byte 5
ICS clock sends first byte (Byte 0) through byte 5
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit
ICS clock will acknowledge each byte one at a time.
Controller (host) sends a Stop bit
How to Write:
Controller (Host)
ICS (Slave/Receiver)
How to Read:
Start Bit
Controller (Host)
ICS (Slave/Receiver)
Address
Start Bit
D2(H)
Address
D3(H)
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Dummy Command Code
ACK
Byte Count
Dummy Byte Count
Byte 0
ACK
ACK
ACK
ACK
ACK
ACK
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
ACK
Stop Bit
Stop Bit
Notes:
1.
The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification.
Read-BackwillsupportIntelPIIX4"Block-Read"protocol.
2.
3.
4.
5.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.
6.
At power-on, all registers are set to a default condition, as shown.
3
ICS9248-103
Functionality
VDD =3.3V±5%,VDDL =2.5V±5%or3.3±5%,TA=0to70°C
Crystal (X1, X2) = 14.31818MHz
CPU
(MHz)
124.00
120.00
114.99
109.99
105.00
83.31
137.00
75.00
100.00
95.00
83.31
133.33
90.00
96.22
66.82
PCI
(MHz)
41.33
40.00
38.33
36.66
35.00
41.65
34.25
37.50
33.33
31.67
27.77
33.33
30.00
32.07
33.41
30.5
FS3
FS2
FS1
FS0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
91.5
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default = 0)
Bit
Description
PWD
0 - ±0.25% Spread Spectrum Modulation, Center Spread
1 - 0 to -0.5% Down Spread
Bit 7
1
CPUCLK
(MHz)
PCICLK
(MHz)
Bit [2, 6:4]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
124.00
120.00
114.99
109.99
105.00
83.31
137.00
75.00
100.00
95.00
83.31
133.33
90.00
96.22
66.82
91.5
41.33
40.00
38.33
36.66
35.00
41.65
34.25
37.50
33.33
31.67
27.77
33.33
30.00
32.07
33.41
30.5
Note1
Bit
[2, 6:4]
Note 1, Default at Power-up will be for
latched logic inputs to define
frequency. Bit [2, 6:4] are default
to 0010.
Note 2, PWD = Power-Up Default
Note 3, When disabling spread spectrum
bit7 needs to be set to 0 to maintain
nominal frequency.
0 - Frequency is selected by hardware select, latched inputs
1 - Frequency is selected by Bit [2, 6:4]
0 - Normal
1 - Spread Spectrum Enabled
0 - Running
Bit 3
Bit 1
Bit 0
0
1
0
1- Tristate all outputs
4
ICS9248-103
Byte 1: CPU, Active/Inactive Register (1 = enable, 0 = disable)
Bit
Pin #
-
46
-
PWD
Description
(Reserved)
CPUCLK_F (Act/Inact)
(Reserved)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
1
1
1
1
-
(Reserved)
39
42
43
45
SDRAM_F (Act/Inact)
CPUCLK2 (Act/Inact)
CPUCLK1 (Act/Inact)
CPUCLK0 (Act/Inact)
Byte 2: PCI Active/Inactive Register (1 = enable, 0 = disable)
Bit
Pin #
7
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
1
1
1
1
PCICLK_F0 (Act/Inact)
PCICLK4(Act/Inact)
PCICLK3 (Act/Inact)
PCICLK2 (Act/Inact)
PCICLK1 (Act/Inact)
PCICLK0 (Act/Inact)
PCICLK_F1 (Act/Inact)
PCICLK_F2 (Act/Inact)
18
17
13
12
11
10
8
Byte 3: SDRAM Active/Inactive Register (1 = enable, 0 = disable)
Bit
Pin #
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
1
1
1
1
1
1
1
1
(Reserved)
(Reserved)
(Reserved)
(Reserved)
SDRAM7 (Active/Inactive)
SDRAM6 (Active/Inactive)
SDRAM5 (Active/Inactive)
SDRAM4 (Active/Inactive)
-
28
29
31
32
Notes:
1. Inactive means outputs are held LOW and are disabled from switching.
2. Latched Frequency Selects (FS#) will be inverted logic load of the input frequency select pin conditions.
5
ICS9248-103
Byte 4: Reserved Active/Inactive Register (1 = enable, 0 = disable)
Bit
Pin #
PWD
1
1
1
1
X
1
X
1
Description
(Reserved)
(Reserved)
(SEL24_48)#
(Reserved)
Latched FS1#
(Reserved)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
Latched FS3#
(Reserved)
Byte 5: Peripheral Active/Inactive Register (1 = enable, 0 = disable)
Bit
Pin #
34
35
37
38
26
25
48
2
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
1
1
1
1
SDRAM3 (Act/Inact)
SDRAM2 (Act/Inact)
SDRAM1 (Act/Inact)
SDRAM0 (Act/Inact)
48MHz (Act/Inact)
24MHz (Act/Inact)
REF1 (Act/Inact)
REF0 (Act/Inact)
Notes:
1. Inactive means outputs are held LOW and are disabled from switching.
2. Latched Frequency Selects (FS#) will be inverted logic load of the input frequency select pin conditions.
6
ICS9248-103
CLK_STOP# Timing Diagram
CLK_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation.
CLK_STOP# is synchronized by the ICS9248-103. The minimum that the CPU clock is enabled (CLK_STOP# high pulse) is 100
CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be stopped in
a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPU clock on latency is less than 4
CPU clocks and CPU clock off latency is less than 4 CPU clocks.
INTERNAL
CPUCLK
PCICLK [6:0]
CLK_STOP#
PCI_STOP# (High)
SDRAM [7:0]
CPUCLK [2:0]
CPUCLK _F
SDRAM_F
Notes:
1. All timing is referenced to the internal CPU clock.
2. CLK_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized
to the CPU clocks inside the ICS9248-103.
3. IOAPIC output is Stopped Glitch Free by CPUSTOP# going low.
4. SDRAM-F output is controlled by Buffer in signal, not affected by the ICS9248-103
CLK_STOP# signal. SDRAM [7:0] are controlled as shown.
5. All other clocks continue to run undisturbed.
7
ICS9248-103
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is
an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering down the clock
synthesizer.
Internal clocks are not running after the device is put in power down. When PD# is active low all clocks need to be driven to a
low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than 4 mS. The power down
latency should be as short as possible but conforming to the sequence requirements shown below. PCI_STOP# and CLK_STOP#
are considered to be don't cares during the power down operations. The REF and 48MHz clocks are expected to be stopped in
the LOW state as soon as possible. Due to the state of the internal logic, stopping and holding the REF clock outputs in the
LOW state may require more than one clock cycle to complete.
PD#
CPUCLK
PCICLK
VCO
Crystal
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device).
2. As shown, the outputs Stop Low on the next falling edge after PD# goes low.
3. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part.
4. The shaded sections on the VCO and the Crystal signals indicate an active clock.
5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz.
8
ICS9248-103
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9248-103. It is used to turn off the PCICLK [4:0] clocks for low power
operation. PCI_STOP# is synchronized by the ICS9248-103 internally. The minimum that the PCICLK [4:0] clocks are enabled
(PCI_STOP# high pulse) is at least 10 PCICLK [4:0] clocks. PCICLK [4:0] clocks are stopped in a low state and started with a full
high pulse width guaranteed. PCICLK [4:0] clock on latency cycles are only three rising PCICLK clocks off latency is one
PCICLKclock.
CPUCLK
(Internal)
PCICLK_F
(Internal)
PCICLK_F
(Free-running)
CLK_STOP#
PCI_STOP#
PCICLK [6:0]
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS9248.
3. All other clocks continue to run undisturbed.
4. CLK_STOP# is shown in a high (true) state.
9
ICS9248-103
Shared Pin Operation -
Input/Output Pins
These figures illustrate the optimal PCB physical layout
options. These configuration resistors are of such a large
ohmic value that they do not effect the low impedance clock
signals. The layouts have been optimized to provide as little
impedance transition to the clock signal as possible, as it
passes through the programming resistor pad(s).
The I/O pins designated by (input/output) on the ICS9248-
103 serve as dual signal functions to the device. During
initial power-up, they act as input pins. The logic level
(voltage) that is present on these pins at this time is read and
stored into a 4-bit internal data latch. At the end of Power-On
reset, (see AC characteristics for timing values), the device
changes the mode of operations for these pins to an output
function. In this mode the pins produce the specified buffered
clocks to external loads.
To program (load) the internal configuration register for these
pins, a resistor is connected to either the VDD (logic 1)
power supply or the GND (logic 0) voltage potential. A 10
Kilohm(10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
Figs. 1 and 2 show the recommended means of implementing
this function. In Fig. 1 either one of the resistors is loaded
onto the board (selective stuffing) to configure the devices
internal logic. Figs. 2a and b provide a single resistor loading
option where either solder spot tabs or a physical jumper
header may be used.
Fig. 1
10
ICS9248-103
Fig. 2a
Fig. 2b
11
ICS9248-103
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . 115°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . 65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device.These ratings are stress
specifications only and functional operation of the device at these or any other conditions above those listed in the operational
sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = VDDL = 3.3 V +/-5% (unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
SYMBOL
VIH
CONDITIONS
MIN
2
TYP
MAX UNITS
VDD+0.3
0.8
V
V
VIL
VSS-0.3
CL = 0 pF; Select @ 66MHz
CL = 0 pF; Select @ 100MHz
CL = 0 pF; Select @ 133MHz
90
150
Operating Supply
Current
IDD3.3OP
mA
120
151
170
180
IDDP D
Fi
µA
Powerdown Current
Input Frequency
Input Capacitance1
CL = 0 pF; Input address VDD or GND
VDD = 3.3 V
250
600
16
MHz
12
27
14.318
CIN
Logic Inputs
X1 & X2 pins
5
pF
pF
CINX
36
45
Clk Stabilization1
Skew1
TSTAB
From VDD = 3.3 V to 1% target Freq.
5.5
4
ms
ns
tCP U-P CI1 VT = 1.5 V
1
2.8
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70º C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
8
MAX UNITS
15
CL = 0 pF; Select @ 66.8 MHz
CL = 0 pF; Select @ 100 MHz
CL = 0 pF; Select @ 133 MHz
Operating SupplyCurrent
IDDL2.5
mA
11
18
20
10
17
IDDLP D
Powerdown Current
Skew1
<1
2.4
A
µ
CL = 0 pF; Input address VDD or GND
VT = 1.5 V; VTL = 1.25 V
tCP U-P CI2
1
4
ns
1Guaranteed by design, not 100% tested in production.
12
ICS9248-103
Electrical Characteristics - CPU
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 20 pF
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
Fall Time1
Duty Cycle1
Skew window1
Jitter, Cycle-to-cycle1
SYMBOL
VOH2A
VOL2A
IOH2A
CONDITIONS
MIN
2.4
TYP
2.85
0.31
-45
MAX UNITS
V
IOH = -20 mA
IOL = 12 mA
VOH = 2.0 V
VOL = 0.8 V
0.4
-27
V
mA
mA
IOL2A
22
45
29
tr2A
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.5
1.4
2
ns
ns
%
ps
ps
tf2A
2
dt2A
55
tsk2A
VT = 1.5 V
80
175
250
tjcyc-cyc2A VT = 1.5 V
200
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - CPU
TA = 0 - 70C; VDDL = 2.5 V +/-5%; CL = 20 pF
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
SYMBOL
VOH2B
VOL2B
CONDITIONS
MIN
2
TYP
2.3
MAX UNITS
V
IOH = -12 mA
IOL = 12 mA
VOH = 1.7 V
VOL = 0.7 V
0.31
-39
26
0.4
-21
V
IOH2B
mA
mA
IOL2B
22
tr2B
tf2B
VOL = 0.4 V, VOH = 2.0 V
1.3
1.6
ns
ns
Fall Time1
VOH = 2.0 V, VOL = 0.4 V
VT = 1.25 V, < 133 MHz
VT = 1.25 V, >= 133 MHz
1.4
47.5
47
1.6
55
52
45
42
Duty Cycle1
dt2B
%
Skew window1
Jitter, Cycle-to-cycle1
tsk2B
VT = 1.25 V
70
175
300
ps
ps
tjcyc-cyc2B VT = 1.25 V
200
1Guaranteed by design, not 100% tested in production.
13
ICS9248-103
Electrical Characteristics - PCI
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 30 pF
PARAMETER
SYMBOL
VOH1
CONDITIONS
MIN
2.4
TYP
3
MAX UNITS
V
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
IOH = -18 mA
IOL = 9.4 mA
VOH = 2.0 V
VOL = 0.8 V
VOL1
0.2
-62
43
0.4
-33
V
IOH1
mA
mA
IOL1
38
45
Rise Time1
Fall Time1
Duty Cycle1
tr1
tf1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.5
1.5
50
2
ns
ns
%
ps
ps
ps
2
dt1
55
Skew window1
Jitter, One Sigma1
Jitter, Absolute1
tsk1
tj1s1
tjabs1
VT = 1.5 V
180
15
500
150
250
VT = 1.5 V
VT = 1.5 V
-250
75
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - SDRAM
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 30 pF
PARAMETER
SYMBOL
VOH3
CONDITIONS
MIN
2.4
TYP
3
MAX UNITS
V
IOH = -28 mA
IOL = 19 mA
VOH = 2.0 V
VOL = 0.8 V
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
VOL3
0.3
-69
42
1
0.4
-46
V
mA
mA
ns
IOH3
IOL3
32
45
Rise Time1
Fall Time1
Duty Cycle1
Skew window1
Tr3
Tf3
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.3
2
1.3
50
ns
Dt3
Tsk3
55
250
%
VT = 1.5 V
185
ps
Propagation Time1
(Buffer In to output)
Tsk3
VT = 1.5 V
4
5
ns
1Guaranteed by design, not 100% tested in production.
14
ICS9248-103
Electrical Characteristics - 24,48MHz, REF(0:1)
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
VOH5
CONDITIONS
MIN
2.4
TYP
2.6
MAX UNITS
V
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
IOH = -14 mA
IOL = 6 mA
VOH = 2.0 V
VOL = 0.8 V
VOL5
0.22
-32
22
0.4
-20
V
IOH5
mA
mA
IOL5
16
Rise Time1
Fall Time1
Duty Cycle1
tr5
tf5
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
2
2
4
ns
ns
%
ps
ps
4
dt5
45
1
55
Jitter, One Sigma1
Jitter, Absolute1
tj1s5
tjabs5
VT = 1.5 V
150
250
600
VT = 1.5 V
-600
1Guaranteed by design, not 100% tested in production.
15
ICS9248-103
SYMBOL
COMMON DIMENSIONS
VARIATIONS
D
NOM. MAX.
N
MIN.
.095
.008
.088
.008
.005
NOM.
.101
.012
.090
.010
-
MAX.
.110
.016
.092
.0135
.010
MIN.
.620
A
A1
A2
B
AC
.625
.630
48
C
D
E
See Variations
.296
.292
.299
e
H
h
0.025 BSC
.406
.013
.400
.010
.024
.410
.016
.040
L
.032
SSOP Package
N
See Variations
5°
.093
0°
.085
8°
.100
X
Ordering Information
ICS9248yF-103
Example:
ICS XXXX y F - PPP
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
16
information being relied upon by the customer is current and accurate.
相关型号：
©2020 ICPDF网 联系我们和版权申明