ICS9248-134 [ICSI]
Frequency Timing Generator for PENTIUM II/III Systems; 频率时序发生器奔腾II / III系统
| 型号： | ICS9248-134 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Frequency Timing Generator for PENTIUM II/III Systems |
| 文件： | 总13页 (文件大小：295K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated
Circuit
Systems, Inc.
ICS9248-134
Frequency Timing Generator for PENTIUM II/III Systems
Recommended Application:
For Intel Camino Style Chipsets
Pin Configuration
GND
REF0
*SEL24_48#/REF1
VDDREF
X1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDDL
IOAPIC0
IOAPIC1
GND
IOAPIC2
VDDL
OutputFeatures:
•
•
•
•
•
•
•
3 - CPUs @ 2.5V, up to 180MHz.
1 - CPU/2 @ 2.5V.
X2
GND
CPU/2
GND
*FS0/PCICLK_F
*FS1/PCICLK0
VDDPCI
*FS2/PCICLK1
*FS3/PCICLK2
GND
CPUCLK0
VDDL
CPUCLK1
CPUCLK2
GND
VDD66
3V66_0
3V66_1
3V66_2
GND66
SDATA
3 - IOAPIC @ 2.5V, PCI or PCI/2
3 - 3V66MHz @ 3.3V.
11 - PCIs @ 3.3V
PCICLK3
PCICLK4
VDDPCI
PCICLK5
PCICLK6
GND
PCICLK7
PCICLK8
PCICLK9
VDDPCI
1 - 48MHz, @ 3.3V fixed
1 - 24/48MHz, @ 3.3V
SCLK
Features:
VDD48
48MHz/FS4*
24_48MHz
GND48
•
•
•
Support power management: Power down Mode
from I2C programming.
PD#
Spread spectrum for EMI control
± 0.25% center spread).
48-pin SSOP
*120K ohm pull-up to VDD on indicated inputs.
Uses external 14.318MHz crystal
Key Specifications:
Functionality
FS4 FS3 FS2 FS1 FS0
•
•
•
CPU Output Jitter: <250ps
CPU
103.00 34.33
105.00 35.00
PCI
3V66
68.67
70.00
IOAPIC
17.17
17.50
IOAPIC Output Jitter: <500ps
48MHz, 3V66, PCI Output Jitter: <500ps)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
100.45 33.483 66.967 16.742
100.90 33.63 67.27 16.82
107.10 35.700 71.400 17.850
109.00 36.33
112.00 37.34
114.00 28.50
116.00 29.00
118.00 29.50
133.30 33.33
120.00 30.00
122.00 30.50
125.00 31.25
72.67
74.67
57.00
58.00
59.00
66.65
60.00
61.00
62.50
18.17
18.67
14.25
14.50
14.75
16.66
15.00
15.25
15.63
Block Diagram
PLL2
48MHz
24_48MHz
/ 2
X1
X2
XTAL
OSC
REF (1:0)
128.21 32.05 64.105 16.026
130.00 32.50
132.00 33.00
133.90 33.48
138.00 34.50
142.00 35.50
146.00 36.50
150.00 37.50
153.00 38.25
156.00 39.00
159.00 39.75
162.00 40.50
165.00 41.25
168.00 42.00
171.00 42.75
174.00 43.50
177.00 44.25
180.00 45.00
65.00
66.00
66.95
69.00
71.00
73.00
75.00
76.50
78.00
79.50
81.00
82.50
84.00
85.50
87.00
88.50
90.00
16.25
16.50
16.74
17.25
17.75
18.25
18.75
19.13
19.50
19.88
20.25
20.63
21.00
21.38
21.75
22.13
22.50
PLL1
Spread
Spectrum
CPU
DIVDER
CPUCLK (2:0)
CPU/2
/ 2
SEL24_48#
FREQ_APIC
IOAPIC
DIVDER
IOAPIC (2:0)
Control
Logic
SDATA
SCLK
PCI
DIVDER
PCICLK (9:0)
PCICLK_F
FS (4:0)
PD#
Config.
Reg.
3V66
DIVDER
3V66 (2:0)
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
9248-134Rev A8/22/00
information being relied upon by the customer is current and accurate.
ICS9248-134
General Description
The ICS9248-134 is a main clock synthesizer chip for Pentium II based systems using Rambus Interface DRAMs. This chip
provides all the clocks required for such a system when used with a Direct Rambus Clock Generator(DRCG) chip such as the
ICS9212-01.
Spread Spectrum may be enabled by driving the SPREAD# pin active. Spread spectrum typically reduces system EMI by 8dB
to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248-134
employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature
variations.
The CPU/2 clocks are inputs to the DRCG.
Pin Descriptions
Pin number
1, 7, 13, 19, 25, 31,
36, 41, 45
Pin name
Type
Description
GND
PWR
Ground pins
2
REF0
REF1
OUT
OUT
IN
14.318MHz reference clock outputs at 3.3V
14.318MHz reference clock outputs at 3.3V
Logic input to select 24 or 48MHz for pin 26 output
3
SEL24_48
4, 10, 16, 23,
VDD
PWR
Power pins 3.3V
28, 35
5
6
X1
X2
IN
XTAL_IN 14.318MHz crystal input
OUT
XTAL_OUT Crystal output
Free running PCI clock at 3.3V. Synchronous to CPU clocks. Not
affected by the PCI_STOP# input.
PCICLK_F
OUT
8
FS0
IN
OUT
IN
Logic - input for frequency selection
PCICLK0
FS1
PCI clock output at 3.3V. Synchronous to CPU clocks.
Logic - input for frequency selection
9
PCICLK1
FS2
OUT
IN
PCI clock output at 3.3V. Synchronous to CPU clocks.
Logic - input for frequency selection
11
12
PCICLK2
FS3
OUT
IN
PCI clock output at 3.3V. Synchronous to CPU clocks.
Logic - input for frequency selection
14, 15, 17, 18, 20,
21, 22
PCICLK (9:3)
OUT
PCI clock outputs at 3.3V. Synchronous to CPU clocks.
This asynchronous input powers down the chip when drive
active(Low). The internal PLLs are disabled and all the output clocks
are held at a Low state.
24
PD#
IN
24 or 48MHz output selectable by
SEL24_48# (0=48MHz 1=24MHz)
Fixed 48MHz clock output. 3.3V
26
27
24_48MHz
OUT
48MHz
FS4
OUT
IN
Logic - input for frequency selection
Clock input of I2C input
Data pin for I2C circuitry 5V tolerant
29
30
SCLK
IN
SDATA
I/O
3.3V clock outputs. These outputs are stopped when CPU_STOP#
is driven active..
32, 33, 34
3V66 (2:0)
OUT
37, 38, 40
42
CPUCLK (2:0)
CPU/2
OUT
OUT
PWR
OUT
Host bus clock output at 2.5V.
2.5V clock outputs at 1/2 CPU frequency.
Power pins for the CPU, CPU/2 & IOAPIC clocks. 2.5V
39, 43, 48
44, 46, 47
VDDL
IOAPIC (2:0)
IOAPIC clocks at 2.5V. Synchronous with CPUCLKs.
2
ICS9248-134
Serial Configuration Command Bitmap
Byte 0: Functionality and frequency select register (Default = 0)
Bit
Description
PWD
Bit 2
FS4
Bit 7
FS3
Bit 6
FS2
Bit 5
FS1
Bit 4
CPU
CPU/2
PCI
3V66
IOAPIC
FS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
103.00
105.00
100.45
100.90
107.10
109.00
112.00
114.00
116.00
118.00
133.30
120.00
122.00
125.00
128.21
130.00
132.00
133.90
138.00
142.00
146.00
150.00
153.00
156.00
159.00
162.00
165.00
168.00
171.00
174.00
177.00
51.50
52.50
34.33
35.00
68.67
70.00
17.17
17.50
16.742
16.82
17.850
18.17
18.67
14.25
14.50
14.75
16.66
15.00
15.25
15.63
16.026
16.25
16.50
16.74
17.25
17.75
18.25
18.75
19.13
19.50
19.88
20.25
20.63
21.00
21.38
21.75
22.13
50.225 33.483 66.967
50.45 33.63 67.27
53.550 35.700 71.400
54.50
56.00
57.00
58.00
59.00
66.65
60.00
61.00
62.50
64.105
65.00
66.00
66.95
69.00
71.00
73.00
75.00
76.50
78.00
79.50
81.00
82.50
84.00
85.50
87.00
88.50
36.33
37.34
28.50
29.00
29.50
33.33
30.00
30.50
31.25
72.67
74.67
57.00
58.00
59.00
66.65
60.00
61.00
62.50
32.05 64.105
Bit
2, 7:4
Reserved
Note 1
32.50
33.00
33.48
34.50
35.50
36.50
37.50
38.25
39.00
39.75
40.50
41.25
42.00
42.75
43.50
44.25
65.00
66.00
66.95
69.00
71.00
73.00
75.00
76.50
78.00
79.50
81.00
82.50
84.00
85.50
87.00
88.50
1
1
1
1
1
180.00
90.00
45.00
90.00
22.50
0 - Frequency is selected by hardware select, latched inputs
1 - Frequency is selected by Bit 2, 7:4
Bit 3
Bit 1
Bit 0
0
1
0
0 - Spread Spectrum disabled
1 - Spread spectrum enabled
0 - Running
1 - Tristate all outputs
Note 1:
Default at power-up will be latched logic inputs to define frequency, as displayed by Bit 1.
3
ICS9248-134
Byte 1: CPU,Active/Inactive Register
(1 = enable, 0 = disable)
Byte2:PCIActive/InactiveRegister
(1 = enable, 0 = disable)
Bit
Pin # PWD
Description
PCICLK7
Bit
Pin #
40
38
37
42
47
46
44
-
PWD
1
1
1
1
1
1
1
X
Description
CPUCLK 0
CPUCLK 1
CPUCLK 2
CPU/2
IOAPIC0
IOAPIC1
IOAPIC2
(Reserved)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
18
17
15
14
12
11
9
1
1
1
1
1
1
1
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PCICLK6
PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK_F
8
Notes:
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
1. Inactive means outputs are held LOW and are disabled
from switching.
Byte 3: 3V66 Active/Inactive Register
(1 = enable, 0 = disable)
Byte 4: PCIActive/Inactive Register
(1 = enable, 0 = disable)
Bit
Pin #
PWD
1
1
1
X
1
1
X
X
Description
Bit
Pin #
26
27
-
PWD
1
1
X
1
1
1
1
X
Description
24_48MHz
48MHz
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
34
33
32
-
3
2
3V66_0
3V66_1
3V66_2
FS1#
REF1
REF0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
FS0#
-
(Reserved)
PCICLK10
PCICLK9
PCICLK8
FS4#
22
21
20
-
-
-
FS3#
FS2#
Notes:
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
1. Inactive means outputs are held LOW and are disabled
from switching.
Byte 5: Active/Inactive Register
(1= enable, 0 = disable)
Byte6: Active/Inactive Register
(1= enable, 0 = disable)
Bit
Pin #
PWD
Description
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Bit
Pin # PWD
Description
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
-
-
-
-
-
-
-
-
0
0
0
0
0
1
1
0
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
-
-
-
-
-
-
-
-
1
1
1
1
1
1
1
1
Notes:
Note: Don’t write into this register, writing into this register
1. Inactive means outputs are held LOW and are disabled
from switching.
can cause malfunction
4
ICS9248-134
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . 115°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70º C; VDD = 3.3 V +/-5%; VDDL = 2.5 V +/-5% (unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input Low Current
Operating
SYMBOL
VIH
CONDITIONS
MIN
2
TYP
MAX UNITS
VDD+0.3
V
VIL
VSS-0.3
0.8
5
V
µA
µA
µA
IIH
VIN = VDD
0.1
2.0
IIL1
VIN = 0 V; Inputs with no pull-up resistors
VIN = 0 V; Inputs with pull-up resistors
-5
IIL2
-200
-100
71
IDD3.3OP100 CL = 0 pF; Select @ 100 MHz
IDD3.3OP133 CL = 0 pF; Select @ 133 MHz
160
160
16
5
mA
mA
MHz
pF
Supply Current
76
Input frequency
Input Capacitance1
Fi
CIN
VDD = 3.3 V;
11
27
14.318
Logic Inputs
CINX
Ttrans
Ts
X1 & X2 pins
36
5
45
3
pF
Transition Time1
Settling Time1
To 1st crossing of target Freq.
From 1st crossing to 1% target Freq.
From VDD = 3.3 V to 1% target Freq.
ms
ms
Clk Stabilization1
TSTAB
3
ms
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70º C; VDD = 3.3 V +/-5%; VDDL = 2.5 V +/-5% (unless otherwise stated)
PARAMETER
Operating
SYMBOL
CONDITIONS
MIN
TYP
15
MAX UNITS
IDD2.5OP100 CL = 0 pF; Select @ 100 MHz
IDD2.5OP133 CL = 0 pF; Select @ 133 MHz
75
90
mA
mA
Supply Current
Power Down
Supply Current
18
IDD2.5PD
CL = 0 pF; PWRDWN# = 0
272
400
µA
1Guaranteed by design, not 100% tested in production.
5
ICS9248-134
Group Offset
TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)
GROUP
CPU to 3V66
3V66 to PCI
CPU to IOAPIC
CPU to PCI
OFFSET
MEASUREMENT LOADS
CPU @ 20pF, 3V66 @ 30pF
3V66 @ 30pF, PCI @ 30pF
CPU @ 20pF, IOAPIC @ 20pF
CPU @ 20pF, PCI @ 30pF
MEASURE POINTS
CPU @ 1.25V, 3V66 @ 1.5V
3V66 @ 1.5V, PCI @ 1.5V
CPU @ 1.25V, IOAPIC @ 1.25V
CPU @ 1.25V, PCI @ 1.5V
0.0-1.5 ns; CPU leads.
0.5-4.0 ns; 3V66 leads.
0.5-4.0 ns; CPU leads.
0.5-4.0 ns; CPU leads.
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - CPUCLK
TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
Output Impedance1
SYMBOL
CONDITIONS
MIN
13.5
TYP
30
MAX UNITS
RDSP2B VO = VDD*(0.5)
RDSN2B VO = VDD*(0.5)
45
45
Ω
Output Impedance1
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
13.5
2
32
2.24
0.31
-31
25
Ω
V
VOH2B
VOL2B
IOH2B
IOL2B
tr2B
IOH = -12.0 mA
IOL = 12.0 mA
VOH = 1.7 V
VOL = 0.7 V
0.4
-19
V
mA
mA
ns
19
45
VOL = 0.4 V, VOH = 2.0 V
VOH = 2.0 V, VOL = 0.4 V
VT = 1.25 V; CPU frequencies < 135 MHz
VT = 1.25 V
1.1
1.4
50
1.6
1.8
55
Fall Time1
tf2B
ns
Duty Cycle1
dt2B
%
Skew1
tsk2B
53
175
ps
VT = 1.25 V; CPU frequencies <135 MHz
VT = 1.25 V; CPU frequencies >=135 MHz
179
231
275
350
Jitter, Cycle-to-cycle1
tjcyc-cyc2B
ps
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - CPU/2
TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
Output Impedance1
SYMBOL
RDSP2B
CONDITIONS
MIN
13.5
TYP
30
MAX UNITS
VO = VDD*(0.5)
45
45
Ω
Output Impedance1
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
RDSN2B
VOH2B
VOL2B
IOH2B
IOL2B
tr2B
VO = VDD*(0.5)
IOH = -12.0 mA
IOL = 12.0 mA
VOH = 1.7 V
13.5
2
31
2.2
0.31
-31
26
Ω
V
0.4
-19
V
mA
mA
ns
VOL = 0.7 V
19
45
VOL = 0.4 V, VOH = 2.0 V
VOH = 2.0 V, VOL = 0.4 V
VT = 1.25 V
1.1
1.1
49
1.6
1.6
55
Fall Time1
Duty Cycle1
tf2B
ns
dt2B
%
VT = 1.25 V; CPU frequencies <135 MHz
VT = 1.25 V; CPU frequencies >=135 MHz
227
306
275
350
Jitter, Cycle-to-cycle1
tjcyc-cyc2B
ps
1Guaranteed by design, not 100% tested in production.
6
ICS9248-134
Electrical Characteristics - 3V66
TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 30 pF (unless otherwise stated)
PARAMETER
Output Impedance1
SYMBOL
RDSP1
CONDITIONS
MIN
12
TYP
24
MAX UNITS
VO = VDD*(0.5)
55
55
Ω
Output Impedance1
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
RDSN1
VOH1
VOL1
IOH1
VO = VDD*(0.5)
IOH = -11 mA
IOL = 9.4 mA
VOH = 2.0 V
VOL = 0.8 V
12
23
3.1
0.17
-51
41
Ω
V
2.4
0.4
-22
V
mA
mA
IOL1
16
45
tr1
tf1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.4
1.5
50
2
2
ns
ns
%
Fall Time1
Duty Cycle1
dt1
55
Skew1
tsk1
VT = 1.5 V
VT = 1.5 V
89
250
500
ps
ps
Jitter, Cycle-to-cycle1
Tjcyc-cyc1
173
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - PCICLK
TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 30 pF (unless otherwise stated)
PARAMETER
Output Impedance1
SYMBOL
RDSP1
CONDITIONS
MIN
12
TYP
24
MAX UNITS
VO = VDD*(0.5)
55
55
Ω
Output Impedance1
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
RDSN1
VOH1
VOL1
IOH1
VO = VDD*(0.5)
IOH = -11 mA
IOL = 9.4 mA
VOH = 2.0 V
VOL = 0.8 V
12
23
3.1
0.16
-50
42
Ω
V
2.4
0.4
-22
V
mA
mA
IOL1
16
45
tr1
tf1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
1.8
1.5
2.5
2.5
ns
ns
%
Fall Time1
Duty Cycle1
dt1
VT = 1.5 V
50
55
VT = 1.5 V, PCICLK(F:7)
VT = 1.5 V, PCICLK(8:10)
VT = 1.5 V, PCICLK(F:10)
VT = 1.5 V
260
211
466
280
350
250
600
500
Skew Window1
tsk1
ps
ps
Jitter, Cycle-to-cycle1
Tjcyc-cyc1
1Guaranteed by design, not 100% tested in production.
7
ICS9248-134
Electrical Characteristics - 48 MHz, 24_48 MHz
TA = 0 - 70ºC; VDD = 3.3 V +/-5%; VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
Output Impedance1
SYMBOL
RDSP5
CONDITIONS
MIN
20
TYP
47
MAX UNITS
VO = VDD*(0.5)
60
60
Ω
Output Impedance1
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
RDSN5
VOH5
VOL5
IOH5
VO = VDD*(0.5)
IOH = -16 mA
IOL = 9 mA
20
44
2.62
0.3
-27
22
Ω
V
2.4
0.4
-22
V
VOH = 2.0 V
VOL = 0.8 V
mA
mA
IOL5
16
45
tr5
tf5
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
2.1
2.2
4
4
ns
ns
Fall Time1
Duty Cycle1
dt5
VT = 1.5 V
VT = 1.5 V
51
55
%
ps
Jitter, Cycle-to-cycle1
Tjcyc-cyc5
375
500
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - REF
TA = 0 - 70ºC; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
Output Impedance1
SYMBOL
RDSP5
CONDITIONS
MIN
20
TYP
MAX UNITS
VO = VDD*(0.5)
48
60
60
Ω
Output Impedance1
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
RDSN5
VOH5
VOL5
IOH5
VO = VDD*(0.5)
IOH = -16 mA
IOL = 9 mA
20
44
2.6
0.3
-26
22
Ω
V
2.4
0.4
-22
V
VOH = 2.0 V
VOL = 0.8 V
mA
mA
IOL5
16
45
tr5
tf5
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
2.1
2.2
4
4
ns
ns
Fall Time1
Duty Cycle1
dt5
VT = 1.5 V
VT = 1.5 V
53
55
%
ps
Jitter, Cycle-to-cycle1
Tjcyc-cyc5
839
1000
1Guaranteed by design, not 100% tested in production.
8
ICS9248-134
Electrical Characteristics - IOAPIC
TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
Output Impedance1
SYMBOL
RDSP4B
CONDITIONS
MIN
13.5
TYP
26
MAX UNITS
VO = VDD*(0.5)
45
45
Ω
Output Impedance1
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
RDSN4B
VOH4B
VOL4B
IOH4B
VO = VDD*(0.5)
IOH = -12.0 mA
IOL = 12.0 mA
VOH = 1.7 V
13.5
2
31
2.24
0.31
-31
26
Ω
V
0.4
-19
V
mA
mA
IOL4B
VOL = 0.7 V
19
45
Rise Time1
Fall Time1
Tr4B
Tf4B
Dt4B
tsk4B
VOL = 0.4 V, VOH = 2.0 V
VOH = 2.0 V, VOL = 0.4 V
VT = 1.25 V
1.6
1.6
2
2
ns
ns
Duty Cycle1
49
55
%
ps
ps
Skew 1
VT = 1.25 V
139
245
250
500
Jitter, Cycle-to-cycle1
Tjcyc-cyc4B VT = 1.25 V
1Guaranteed by design, not 100% tested in production.
9
ICS9248-134
Power Management Features:
REF.
48MHz
PD# CPUCLK CPU/2 IOAPIC 3V66
PCI
LOW
ON
PCI_F
LOW
ON
Osc
OFF
ON
VCOs
OFF
ON
0
1
LOW
ON
LOW
ON
LOW
ON
LOW
ON
LOW
ON
Note:
1. LOW means outputs held static LOW as per latency requirement next page.
2. On means active.
3. PD# pulled Low, impacts all outputs including REF and 48 MHz outputs.
Power Management Requirements:
Latency
Signal
Signal State
No. of rising edges of
PCICLK
1 (normal operation)
0 (power down)
3mS
PD#
2max.
Note:
1. Clock on/off latency is defined in the number of rising edges of free running PCICLKs between the clock disable goes low/
high to the first valid clock comes out of the device.
2. Power up latency is when PWR_DWN# goes inactive (high to when the first valid clocks are dirven from the device.
10
ICS9248-134
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
For more information, contact ICS for an I2C programming application note.
How to Write:
Controller (host) sends a start bitꢀ
Controller (host) sends the write address D2(H)
ICS clock will acknowledge
How to Read:
Controller (host) will send start bitꢀ
Controller (host) sends the read address D3 (H)
ICS clock will acknowledge
Controller (host) sends a dummy command code
ICS clock will acknowledge
ICS clock will send the byte count
Controller (host) acknowledges
Controller (host) sends a dummy byte count
ICS clock will acknowledge
Controller (host) starts sending first byte (Byte 0)
through byte 5
ICS clock sends first byte (Byte 0) through byte 5
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit
ICS clock will acknowledge each byte one at a timeꢀ
Controller (host) sends a Stop bit
How to Write:
Controller (Host)
ICS (Slave/Receiver)
How to Read:
Start Bit
Controller (Host)
ICS (Slave/Receiver)
Address
Start Bit
D2(H)
Address
D3(H)
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Dummy Command Code
ACK
Byte Count
Dummy Byte Count
Byte 0
ACK
ACK
ACK
ACK
ACK
ACK
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
ACK
Stop Bit
Stop Bit
Notes:
1.
The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for
verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.
2.
3.
4.
5.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.
6.
At power-on, all registers are set to a default condition, as shown.
11
ICS9248-134
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is
an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering down the
clock synthesizer.
Internal clocks are not running after the device is put in power down. When PD# is active low all clocks need to be driven to
a low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than 3 mS. The power
down latency should be as short as possible but conforming to the sequence requirements shown below. The REF and 48MHz
clocks are expected to be stopped in the LOW state as soon as possible. Due to the state of the internal logic, stopping and
holding the REF clock outputs in the LOW state may require more than one clock cycle to complete.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device).
2. As shown, the outputs Stop Low on the next falling edge after PD# goes low.
3. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part.
4. The shaded sections on the VCO and the Crystal signals indicate an active clock.
5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz.
12
ICS9248-134
SYMBOL
In Millimeters
In Inc hes
COMMON DIMENSIONS COMMON DIMENSIONS
MIN
MAX
2.794
0.406
0.343
0.254
MIN
MAX
.110
.016
.0135
.010
A
A1
b
2.413
0.203
0.203
0.127
.095
.008
.008
.005
c
SEE VARIATIONS
SEE VARIATIONS
D
E
10.033
7.391
10.668
7.595
.395
.291
.420
.299
E1
e
0.635 BASIC
0.025 BASIC
h
0.381
0.508
0.635
1.016
.015
.020
.025
.040
L
SEE VARIATIONS
SEE VARIATIONS
N
0°
8°
0°
8°
α
VARIATIONS
N
D mm.
D (inch)
MIN
MAX
MIN
MAX
9.652
28
34
48
56
64
9.398
11.303
15.748
18.288
20.828
.370
.445
.620
.720
.820
.380
.455
.630
.730
.830
11.557
16.002
18.542
21.082
J E DE C MO- 118
6/ 1/ 00
DOC# 10-0034
REVB
Ordering Information
ICS9248yF-134-T
Example:
ICS XXXX y F - PPP - T
Designation for tape and reel packaging
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
13
information being relied upon by the customer is current and accurate.
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