ICS9248-61 [ICSI]
Frequency Timing Generator for Pentium II Systems; 频率时序发生器奔腾II系统
| 型号： | ICS9248-61 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Frequency Timing Generator for Pentium II Systems |
| 文件： | 总9页 (文件大小：292K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated
Circuit
Systems, Inc.
ICS9248-61
Frequency Timing Generator for Pentium II Systems
General Description
Features
Generates the following system clocks:
The ICS9248-61 is the Main clock solution for Notebook
designs using the Intel 440BX style chipset. Along with an
SDRAM buffer such as the ICS9179-03, it provides all
necessary clock signals for such a system.
-2CPU(2.5V)upto100MHz.
- 7 PCI(3.3V) @ 33.3MHz (Includes one free running).
-2REFclksFixed(3.3V)48MHzat14.318MHz.
Skew characteristics:
Spread spectrum may be enabled by driving pin 26, SPREAD#
active (Low) at power-on. Spread spectrum typically reduces
system EMI by 8dB to 10dB. This simplifies EMI qualification
without resorting to board design iterations or costly shielding.
The ICS9248-61 employs a proprietary closed loop design,
which tightly controls the percentage of spreading over
process and temperature variations.
-CPUCPU<175ps
- PCI PCI < 250ps
- PCI_E (early) PCI = 2.1ns
- CPU(early) PCI = 1.5ns 4ns
Supports Spread Spectrum modulation for CPU and PCI
clocks, 0.5% down spread
Efficient Power management scheme through stop clocks
and power down modes.
Uses external 14.318MHz crystal, no external load cap
required for CL=18pF crystal.
28pin209milSSOP.
Block Diagram
Pin Configuration
28 pin SSOP
Power Groups
GNDR/C=REFCLK,CORE,Crystal
VDDCOR=Core
GNDLCPU,VDDCPU=CPU
GND48,VDD48=48MHz
VDDPCI,GNDPCI-PCICLK,PCICLK_F,PCICLK_E
Pentium is a trademark on Intel Corporation.
9248-61RevB1/8/99
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
ICS9248-61
Pin Descriptions
Pin number
Pin name
Type
Description
2
X1
Input 14.318 MHz crystal input
3
X2
Output 14.318 MHz crystal output
4
7
8
12
13
PCICLK_F
GNDPCI
VDDPCI
PCICLK_E
VDD48
Output 3.3 V free running PCI clock output, will not be stopped by the PCI_STOP#
Power Ground for PCI clock outputs
Power 3.3 V power for the PCI clock outputs
Output Early PCICLK output, offset from other PCICLKs, stopped by PCI-STOP#
Power 3.3 V power for 48 MHz clocks
on power-on control for the frequency of clocks at the CPU & PCICLK output pins. If
SEL 100_66#/
48MHz
logic "0" is used the 66.6 MHz frequency is selected. If Logic "1" is used, the 100
MHz frequency is selected. The PCI clock is multiplexed to run at 33.3 MHz for both
14
Input
selects
15
16
GND48
DIV4#
Power Ground for 48 MHz clocks
Active low input, enables the CPUCLK and the PCICLK to run at 1/4 of the regular
Input
frequecies
Asynchronous active low input pin used to power down the device into a low power
Input state. The internal clocks are disabled and the VCO and the crystal are stopped. The
latency of the power down will not be greater than 3ms.
Asynchronous active low input pin used to stop the CPUCLK in active low state, all
Input other clocks will continue to run. The CPUCLK will have a "Turnon " latency of at
least 3 CPU clocks.
17
18
PD#
CPU_STOP#
19
20
VDDCOR
Input 3.3 V power for the core
Synchronous active low input used to stop the PCICLK in active low state. It will not
PCI-STOP#
Input
effect PCICLK_F or any other outputs.
21
22
25
GNDR/C
GNDLCPU
VDDLCPU
Input Ground for REFCLK, Crystal & Core
Power Ground for the CPU and Host clock outputs
Power 2.5 V power for the CPU and Host clock outputs
power-on spread spectrum enable option. Active low = spread spectrum clocking
enable. Active high = spread spectrum clocking disable.
26
SPREAD#
Output
28
1,27
VDDR
REF(0:1)
Input 3.3 V power for the REFCLK and crystal clock outputs
Output
3.3V, 14.318 MHz reference clock output.
23,24
5,6,9,10, 11
CPUCLK (0:1)
PCICLK (1:4)
0utput 2.5 V CPU and Host clock outputs
Output 3.3 V PCI clock outputs, generating timing requirements
2
ICS9248-61
Frequency Table
SEL
DIV4#
CPU MHz
PCI MHz
100/66#
1
1
0
0
1
0
1
0
100
66.69
25
33
33
8.32
8.32
16.65
Power Management
Clock Enable Configuration
CPU_STOP# PCI_STOP# PWR_DWN#
CPUCLK
PCICLK PCICLK_F
REF
Crystal
Off
VCOs
Off
X
0
0
1
1
X
0
1
0
1
0
1
1
1
1
Low
Low
Low
Low
Low
Stopped
33.3MHz
Running Running Running
Running Running Running
Running Running Running
Running Running Running
Low
33.3 MHz 33.3MHz
Low 33.3MHz
100/66.6MHz
100/66.6MHz 33.3 MHz 33.3MHz
Full clock cycle timing is guaranteed at all times after the system has initially powered up except where noted. During power
up and power down operations using the PD# pin will not cause clocks of a short or longer pulse than that of the running clock.
The first clock pulse coming out of a stopped clock condition may be slightly distorted due to clock network charging circuitry.
Board routing and signal loading may have a large impact on the initial clock distortion also.
ICS9248-61PowerManagementRequirements
Latency
SIGNAL
SIGNAL STATE
No. of rising edges of free running
PCICLK
CPU_ STOP#
0 (Disabled)2
1 (Enabled)1
0 (Disabled)2
1
1
1
PCI_STOP#
PD#
1 (Enabled)1
1 (Normal Operation)3
0 (Power Down)4
1
3ms
2max
Notes.
1. Clock on latency is defined from when the clock enable goes active to when the first valid clock comes out of the device.
2. Clock off latency is defined from when the clock enable goes inactive to when the last clock is driven low out of the device.
3. Power up latency is when PD# goes inactive (high) to when the first valid clocks are output by the device.
4. Power down has controlled clock counts applicable to CPUCLK, PCICLK only.
The REF will be stopped independant of these.
3
ICS9248-61
CPU_STOP# Timing Diagram
CPUSTOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPUCLKs for low power operation.
CPU_STOP# is synchronized by the ICS9248-61. The minimum that the CPUCLK is enabled (CPU_STOP# high pulse) is 100
CPUCLKs.All other clocks will continue to run while the CPUCLKs are disabled.The CPUCLKs will always be stopped in a low
state and start in such a manner that guarantees the high pulse width is a full pulse. CPUCLK on latency is less than 4 CPUCLKs
and CPUCLK off latency is less than 4 CPUCLKs.
Notes:
1. All timing is referenced to the internal CPUCLK.
2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized to the CPUCLKs inside
the ICS9248-61.
3. All other clocks continue to run undisturbed.
4. PD# and PCI_STOP# are shown in a high (true) state.
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9248-61. It is used to turn off the PCICLK (0:4) clocks for low power operation.
PCI_STOP# is synchronized by the ICS9248-61 internally.The minimum that the PCICLK (0:4) clocks are enabled (PCI_STOP#
high pulse) is at least 10 PCICLK (0:4) clocks. PCICLK (0:4) clocks are stopped in a low state and started with a full high pulse
width guaranteed. PCICLK (0:4) clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS9248.
3. All other clocks continue to run undisturbed.
4. PD# and CPU_STOP# are shown in a high (true) state.
4
ICS9248-61
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is
an asynchronous active low input. This signal is synchronized internally by the ICS9248-61 prior to its control action of
powering down the clock synthesizer. Internal clocks will not be running after the device is put in power down state. When PD#
is active (low) all clocks are driven to a low state and held prior to turning off the VCOs and the crystal oscillator. The power on
latency is guaranteed to be less than 3ms. The power down latency is less than three CPUCLK cycles. PCI_STOP# and
CPU_STOP# are dont care signals during the power down operations.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device).
2. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside the ICS9248.
3. The shaded sections on the VCO and the Crystal signals indicate an active clock is being generated.
5
ICS9248-61
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . 65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = VDDL = 3.3 V +/-5% (unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input Low Current
Operating
SYMBOL
VIH
CONDITIONS
MIN
2
TYP
MAX UNITS
VDD+0.3
V
V
VIL
VSS-0.3
0.8
5
A
µ
µ
µ
IIH
VIN = VDD
0.1
2.0
-100
60
A
A
IIL1
VIN = 0 V; Inputs with no pull-up resistors
VIN = 0 V; Inputs with pull-up resistors
-5
IIL2
-200
IDD3.3OP66 CL = 0 pF; Select @ 66MHz
IDD3.3OP100 CL = 0 pF; Select @ 100MHz
180
180
mA
mA
Supply Current
66
CL = 0 pF;
IDD3.3PD
Power Down Supply
Current
Input frequency
With input address to Vdd or GND
70
600
16
5
A
µ
MHz
pF
Fi
VDD = 3.3 V;
11
27
14.318
CIN
Logic Inputs
Input Capacitance1
CINX
Ttrans
TSTAB
X1 & X2 pins
36
45
pF
Transition Time1
Clk Stabilization1
Skew1
To 1st crossing of target Freq.
From VDD = 3.3 V to 1% target Freq.
3
3
4
ms
ms
ns
TCPU-PCI1 VT = 1.5 V;
1.5
2.4
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V+/-5%, VDDL = 2.5 V+/-5% (unless otherwise stated)
PARAMETER
Operating
SYMBOL
IDD2.5OP66
CONDITIONS
MIN
TYP
16
MAX UNITS
CL = 0 pF; Select @ 66.8 MHz
72
mA
mA
Supply Current
Skew1
IDD2.5OP100 CL = 0 pF; Select @ 100 MHz
23
100
tCPU-PCI2 V = 1.5 V; V = 1.25 V
T
TL
1.5
3
4
ns
1Guaranteed by design, not 100% tested in production.
6
ICS9248-61
Electrical Characteristics - CPUCLK
TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
VOH2B
VOL2B
IOH2B
CONDITIONS
MIN
2
TYP
2.3
0.2
-41
37
MAX UNITS
V
IOH = -12.0 mA
IOL = 12 mA
VOH = 1.7 V
VOL = 0.7 V
0.4
-19
V
mA
mA
ns
IOL2B
19
45
1
tr2B
VOL = 0.4 V, VOH = 2.0 V
VOH = 2.0 V, VOL = 0.4 V
VT = 1.25 V
1.25
1
1.6
1.6
1
Fall Time
tf2B
ns
1
Duty Cycle
dt2B
48
55
%
1
Skew
tsk2B
VT = 1.25 V
30
175
250
150
+250
ps
1
Jitter, Cycle-to-cycle tjcyc-cyc2B VT = 1.25 V
150
40
ps
1
Jitter, One Sigma
Jitter, Absolute
tj1s2B
VT = 1.25 V
VT = 1.25 V
ps
1
tjabs2B
-250
140
ps
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - PCICLK
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 30 pF
PARAMETER
SYMBOL
VOH1
CONDITIONS
MIN
2.4
TYP
3.1
0.1
-62
57
MAX UNITS
V
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
IOH = -11 mA
IOL = 9.4 mA
VOH = 2.0 V
VOL = 0.8 V
VOL1
0.4
-22
V
IOH1
mA
mA
IOL1
16
45
Rise Time1
Fall Time1
Duty Cycle1
tr1
tf1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.5
1.1
50
2
2
ns
ns
%
dt1
55
Skew1
tsk1
VT = 1.5 V
140
500
ps
ps
Jitter, Cycle-to-cycle
Jitter, One Sigma1
Jitter, Absolute1
tjcyc-cyc1
VT = 1.25 V
250
500
tj1s1
VT = 1.5 V
VT = 1.5 V
17
70
150
250
ps
ps
tjabs1
-250
1Guaranteed by design, not 100% tested in production.
7
ICS9248-61
Electrical Characteristics - REF/48MHz
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
VOH5
CONDITIONS
MIN
2.6
TYP
3.1
MAX UNITS
V
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
IOH = -12 mA
IOL = 9 mA
VOH = 2.0 V
VOL = 0.8 V
VOL5
0.17
-44
42
0.4
-22
V
IOH5
mA
mA
IOL5
16
45
Rise Time1
Fall Time1
Duty Cycle1
tr5
tf5
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.4
1.1
53
1
4
4
ns
ns
%
%
%
dt5
55
3
Jitter, One Sigma1
Jitter, Absolute1
tj1s5
tjabs5
VT = 1.5 V
VT = 1.5 V
3
5
1Guaranteed by design, not 100% tested in production.
8
ICS9248-61
COMMON
DIMENSIONS
D
VARIATIONS
SYMBOL
MIN.
NOM.
MAX.
N
MIN.
NOM.
MAX.
A
A1
A2
b
0.068
0.002
0.066
0.010
0.004
0.073
0.005
0.078
0.008
0.070
0.015
0.008
14
16
20
24
28
30
0.239
0.239
0.278
0.318
0.397
0.397
0.244
0.244
0.284
0.323
0.402
0.402
0.249
0.249
0.289
0.328
0.407
0.407
0.068
0.012
c
0.006
D
E
See Variations
0.209
0.205
0.212
e
0.0256 BSC
0.307
H
L
0.301
0.025
0.311
0.037
SSOP Package
0.030
N
See Variations
4°
Dimensions in inches
0°
8°
Ordering Information
ICS9248F-61
Example:
ICS XXXX Y F - PPP
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
RevisionDesignator
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
9
information being relied upon by the customer is current and accurate.
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