ICS9248YF-138 [ICSI]
Frequency Generator & Integrated Buffers for Celeron & PII/III⑩; 频率发生器和缓冲器集成的赛扬和PII / III⑩
| 型号： | ICS9248YF-138 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Frequency Generator & Integrated Buffers for Celeron & PII/III⑩ |
| 文件： | 总12页 (文件大小：246K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS9248-138
Integrated
Circuit
Systems, Inc.
Preliminary Product Preview
Frequency Generator & Integrated Buffers for Celeron & PII/III™
Recommended Application:
Pin Configuration
810/810E and Solano type chipsetꢀ
1*SEL24_48#/REF0
VDDREF
X1
1
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDDLAPIC
IOAPIC1
Output Features:
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
VDDLCPU
CPUCLK0
CPUCLK1
GNDLCPU
GNDSDR
SDRAM0
SDRAM1
SDRAM2
VDDSDR
SDRAM3
SDRAM4
SDRAM5
GNDSDR
SDRAM6
SDRAM7
SDRAM_F
VDDSDR
GND48
•
•
•
•
•
•
•
•
2- CPUs @ 2.5V
X2
9 - SDRAM @ 3.3V, including 1 free running
7 - PCICLK @ 3.3V
GNDREF
GND3V66
3V66-0
3V66-1
3V66-2
1 - IOAPIC @ 2.5V,
3 - 3V66MHz @ 3.3V
2 - 48MHz, @ 3.3V fixed.
1 - 24/48MHz, @3.3V selectable by I2C
1 - REF @v3.3V, 14.318MHz.
VDD3V66
VDDPCI
1*FS0/PCICLK0
1**FS1/PCICLK1
GNDPCI
PCICLK2
PCICLK3
PCICLK4
VDDPCI
PCICLK5
PCICLK6
GNDPCI
PD#
Features:
•
•
•
Up to 200MHz frequency support
Support FS0-FS4 strapping status bit for I2C read back.
Support power management: Through Power down
Mode from I2C programming.
24_48MHz/FS2**
48MHz/FS3*
48MHz/FS4*1
VDD48
•
•
Spread spectrum for EMI control ( ± 0.25% center).
Uses external 14.318MHz crystal
SCLK
SDATA
Skew Specifications:
•
•
•
•
•
CPU – CPU: <175ps
48-Pin 300mil SSOP
* These inputs have a 120K pull up to VDDꢀ
** These inputs have a 120K pull down to GNDꢀ
1 These are double strengthꢀ
SDRAM - SDRAM: < 250ps
3V66 – 3V66: <175ps
PCI – PCI: <500ps
For group skew specifications, please refer to group
timing relationship.
Functionality
CPU
(MHz)
66.67
66.87
68.67
SDRAM
(MHz)
100.00
100.30
103.00
107.00
100.00
100.30
103.00
107.00
133.33
133.73
137.33
120.00
100.00
100.30
103.00
90.00
3V66
(MHz)
66.67
66.87
68.67
71.34
66.67
66.87
68.67
71.34
66.67
66.87
68.67
60.00
66.67
66.87
68.67
60.00
PCICLK
(MHz)
33.33
33.43
34.33
35.66
33.33
33.43
34.33
35.66
33.33
33.43
34.33
30.00
33.33
33.43
34.33
30.00
IOAPIC
(MHz)
16.67
16.72
17.16
17.83
16.67
16.72
17.17
17.84
16.67
16.72
17.17
15.00
16.67
16.72
17.17
15.00
FS4 FS3 FS2 FS1 FS0
Block Diagram
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
PLL2
48MHz [1:0]
24_48MHz
2
71.34
/ 2
100.00
100.30
103.00
107.00
133.33
133.73
137.33
120.00
133.33
133.73
137.33
120.00
X1
X2
XTAL
OSC
REF0
PLL1
Spread
Spectrum
CPU
DIVDER
CPUCLK [1:0]
2
8
SDRAM
DIVDER
SDRAM [7:0]
SDRAM_F
IOAPIC
SEL24_48#
IOAPIC
DIVDER
Control
Logic
SDATA
SCLK
PCI
DIVDER
PCICLK [6:0]
3V66 [2:0]
7
FS[4:0]
PD#
1
1
1
1
1
1
1
1
0
1
0
1
1
0
1
1
0
1
1
0
160.00
160.00
166.67
166.67
160.00
120.00
166.67
125.00
80.00
80.00
83.34
83.34
40.00
40.00
41.67
41.67
20.00
20.00
20.84
20.84
Config.
Reg.
3V66
DIVDER
3
Additional frequencies selectable through I2C programmingꢀ
PRODUCT PREVIEW documents contain information on new
products in the sampling or preproduction phase of development.
Characteristic data and other specifications are subject to change
without notice.
9248- 138 Rev A 10/03/00
Third party brands and names are the property of their respective owners.
ICS9248-138
Preliminary Product Preview
General Description
The ICS9248-138 is the single chip clock solution for designs using the 810/810E and Solano style chipsetꢀ It provides all
necessary clock signals for such a systemꢀ
Spread spectrum may be enabled through I2C programmingꢀ Spread spectrum typically reduces system EMI by 8dB to 10dBꢀ
This simplifies EMI qualification without resorting to board design iterations or costly shieldingꢀ The ICS9248-138 employs a
proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variationsꢀ
Serial programming I2C interface allows changing functions, stop clock programming and frequency selectionꢀ
Pin Configuration
PIN NUMBER
PIN NAME
TYPE
DESCRIPTION
Logic inputs frequency select I/O/USB output,
When a "0" is latched, output frequency = 48MHz
When a "1" is latched, output frequency = 24MHz
14.318 MHz reference clock.
SEL24_48MHz#
IN
1
REF0
VDD
OUT
PWR
2, 10, 11, 18, 25,
3.3V Power supply for SDRAM output buffers, PCI output buffers,
reference output buffers and 48MHz output
Crystal input,nominally 14.318MHz.
30, 38
3
X1
X2
IN
4
OUT
Crystal output, nominally 14.318MHz.
5, 6, 14, 21, 29, 34,
GND
PWR
Ground pin for 3V outputs.
42
9, 8, 7
3V66 [2:0]
FS0
OUT
IN
3.3V Clocks
Frequency select pin.
PCI clock output
Frequency select pin.
PCI clock output
PCI clock outputs.
12
PCICLK0
FS1
OUT
IN
13
PCICLK1
PCICLK [6:2]
OUT
OUT
20, 19, 17, 16, 15
Asynchronous active low input pin used to power down the device into a low
power state. The internal clocks are disabled and the VCO and the crystal are
stopped. The latency of the power down will not be greater than 3ms.
22
PD#
IN
23
24
SCLK
SDATA
FS4
IN
IN
Clock input of I2C input, 5V tolerant input
Data input for I2C serial input, 5V tolerant input
Frequency select pin.
IN
26
27
28
31
48MHz
FS3
OUT
IN
48MHz output clocks
Frequency select pin.
48MHz
FS2
24_48MHz
OUT
IN
48MHz output clocks
Frequency select pin.
OUT
24 or 48MHz output
Free running SDRAM - used for feed back to chipset, should remain on
always.
SDRAM_F
OUT
OUT
32, 33, 35, 36, 37,
SDRAM [7:0]
SDRAM clock outputs
39, 40, 41,
43
44, 45
46
GNDLCPU
CPUCLK [1:0]
VDDLCPU
IOAPIC
PWR
OUT
PWR
OUT
Ground pin for the CPU clocks.
CPU clock outputs.
Power pin for the CPUCLKs. 2.5V
2.5V clock output
47
Third party brands and names are the property of their respective owners.
2
ICS9248-138
Preliminary Product Preview
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default = 0)
Bit
Description
CPUCLK SDRAM 3V66
PWD
bit2 bit7 bit6 bit5 bit4
FS4 FS3 FS2 FS1 FS0
PCICLK IOAPIC
Spread Precentage
(MHz)
(MHz)
100.00
100.30
103.00
107.00
100.00
100.30
103.00
107.00
133.33
133.73
137.33
120.00
100.00
100.30
103.00
90.00
(MHz)
66.67
66.87
68.67
71.34
66.67
66.87
68.67
71.34
66.67
66.87
68.67
60.00
66.67
66.87
68.67
60.00
68.00
70.00
71.34
72.67
68.00
70.00
71.34
72.67
73.34
76.67
80.00
83.34
73.34
80.00
83.34
66.67
(MHz)
33.33
33.43
34.33
35.67
33.33
33.43
34.33
35.67
33.33
33.43
34.33
30.00
33.33
33.43
34.33
30.00
34.00
35.00
35.67
36.33
34.00
35.00
35.67
36.33
36.67
38.33
40.00
41.67
36.67
40.00
41.67
33.33
(MH)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
66.67
16.67 0 to -0.5% Down Spread
66.87
16.72
17.16
17.83
± 0.25% Center Spread
± 0.25% Center Spread
± 0.25% Center Spread
68.67
71.34
100.00
100.30
103.00
107.00
133.33
133.73
137.33
120.00
133.33
133.73
137.33
120.00
136.00
140.00
142.67
145.33
136.00
140.00
142.67
145.33
146.67
153.33
160.00
166.67
146.67
160.00
166.67
200.00
16.67 0 to -0.5% Down Spread
16.72
17.17
17.84
± 0.25% Center Spread
± 0.25% Center Spread
± 0.25% Center Spread
16.67 0 to -0.5% Down Spread
16.72
17.17
15.00
± 0.25% Center Spread
± 0.25% Center Spread
± 0.25% Center Spread
16.67 0 to -0.5% Down Spread
16.72
17.17
15.00
17.00
17.50
17.84
18.17
17.00
17.50
17.84
18.17
18.34
19.17
20.00
20.84
18.34
20.00
20.84
16.67
± 0.25% Center Spread
± 0.25% Center Spread
± 0.25% Center Spread
± 0.25% Center Spread
± 0.25% Center Spread
± 0.25% Center Spread
± 0.25% Center Spread
± 0.25% Center Spread
± 0.25% Center Spread
± 0.25% Center Spread
± 0.25% Center Spread
± 0.25% Center Spread
± 0.25% Center Spread
± 0.25% Center Spread
± 0.25% Center Spread
± 0.25% Center Spread
± 0.25% Center Spread
± 0.25% Center Spread
± 0.25% Center Spread
0,0000
Bit
2, 7:4
136.00
140.00
142.67
145.33
102.00
105.00
107.00
109.00
146.67
153.33
160.00
166.67
110.00
120.00
125.00
200.00
0 - Frequency is selected by hardware select, Latched Inputs
1 - Frequency is selected by Bit 2, 6:4
0 - Normal
1 - Spread Spectrum Enabled ± 0.25% Center Spread
0 - Running
Bit 3
Bit 1
Bit 0
0
1
0
1- Tristate all outputs
Note 1: Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3ꢀ
I2C is a trademark of Philips Corporation
Third party brands and names are the property of their respective owners.
3
ICS9248-138
Preliminary Product Preview
Byte 1: SDRAM Control Register
(1= enable, 0 = disable)
Byte 2: PCI, Control Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
BIT PIN# PWD
DESCRIPTION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
1
1
1
1
1
1
1
1
FS0#
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
X
X
1
FS2#
FS1#
20
19
17
16
15
13
12
PCICLK6
PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0
-
31
32
33
35
36
37
SDRAM_F
SDRAM7
SDRAM6
SDRAM5
SDRAM4
SDRAM3
1
1
1
1
1
Byte 3: 3V66, Control Register
(1= enable, 0 = disable)
Byte 4: Control Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
BIT PIN# PWD
DESCRIPTION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
1
1
1
1
1
1
1
1
Reserved
Reserved
Reserved
Reserved
Reserved
48MHz-0
48MHz-1
24_48MHz
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
X
1
FS4#
Reserved
Reserved
FS3#
-
-
1
-
-
X
1
-
-
Reserved
3V66-0
3V66-1
3V66-2
26
27
28
7
8
9
1
1
1
Byte 5: Control Register
(1= enable, 0 = disable)
Byte 6: Control Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
BIT PIN# PWD
DESCRIPTION
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
-
-
-
-
-
-
-
-
0
0
0
0
0
1
1
0
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
-
X
1
1
1
1
1
1
1
SEL24_48#
REF0
1
47
44
45
39
40
41
IOAPIC
CPUCLK1
CPUCLK0
SDRAM2
SDRAM1
SDRAM0
Notes:
Note: Dont write into this register, writing into this
register can cause malfunction
1ꢀ Inactive means outputs are held LOW and are disabled
from switchingꢀ
2ꢀ Latched Frequency Selects (FS#) will be inferted logic
load of the input frequency select pin conditionsꢀ
Third party brands and names are the property of their respective owners.
4
ICS9248-138
Preliminary Product Preview
Absolute Maximum Ratings
Core Supply Voltage ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ 5ꢀ5 V
I/O Supply Voltage ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ 3ꢀ6V
Logic Inputs ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ GND0ꢀ5 V to VDD +0ꢀ5 V
Ambient Operating Temperature ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ 0°C to +70°C
Storage Temperature ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ 65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the deviceꢀ These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not impliedꢀ Exposure to absolute maximum rating conditions for extended periods
may affect product reliabilityꢀ
GroupTimingRelationshipTable
Group
CPU 66MHz
SDRAM 100MHz
CPU 100MHz
SDRAM 100MHz
CPU 133MHz
SDRAM 100MHz
CPU 133MHz
SDRAM 133MHz
Offset
2.5ns
7.5ns
0.0ns
Tolerance
500ps
Offset
5.0ns
5.0ns
0.0ns
Tolerance
500ps
Offset
0.0ns
0.0ns
0.0ns
Tolerance
500ps
Offset
3.75ns
0.0ns
Tolerance
500ps
CPU to SDRAM
CPU to 3V66
500ps
500ps
500ps
500ps
SDRAM to 3V66
500ps
500ps
500ps
3.75ns
500ps
3V66 to PCI
PCI to PCI
1.5-3.5ns
0.0ns
500ps
1.0ns
N/A
1.5-3.5ns
0.0ns
500ps
1.0ns
N/A
1.5-3.5ns
0.0ns
500ps
1.0ns
N/A
1.5 -3.5ns
0.0ns
500ps
1.0ns
N/A
USB & DOT
Asynch
Asynch
Asynch
Asynch
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +5%, VDDL=2.5 V+ 5%(unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input Low Current
Operating
SYMBOL
VIH
CONDITIONS
MIN
2
TYP
MAX UNITS
VDD+0.3
V
V
VIL
VSS-0.3
-5
0.8
5
A
µ
IIH
VIN = VDD
A
µ
IIL1
VIN = 0 V; Inputs with no pull-up resistors
VIN = 0 V; Inputs with pull-up resistors
CL = 0 pF; Select @ 66M
-5
A
µ
IIL2
-200
IDD3.3OP
100
600
mA
Supply Current
Power Down
A
µ
IDD3.3PD CL = 0 pF; With input address to Vdd or GND
Supply Current
Input frequency
Pin Inductance
Input Capacitance1
Fi
VDD = 3.3 V;
14.318
MHz
nH
pF
Lpin
CIN
7
5
Logic Inputs
Cout
CINX
Ttrans
Ts
Out put pin capacitance
X1 & X2 pins
6
pF
27
45
3
pF
Transition Time1
Settling Time1
Clk Stabilization1
Delay
To 1st crossing of target Freq.
From 1st crossing to 1% target Freq.
From VDD = 3.3 V to 1% target Freq.
mS
mS
mS
nS
3
TSTAB
3
t
PZH,tPZH output enable delay (all outputs)
1
1
10
10
tPLZ,tPZH
output disable delay (all outputs)
nS
1Guarenteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
5
ICS9248-138
Preliminary Product Preview
Electrical Characteristics - CPU
TA = 0 - 70C, VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
CONDITIONS
MIN
13.5
13.5
2
TYP MAX UNITS
1
RDSP2B
VO = VDD*(0.5)
VO = VDD*(0.5)
IOH = -1 mA
45
45
Ω
Ω
1
RDSN2B
VOH2B
VOL2B
IOH2B
IOL2B
V
IOL = 1 mA
0.4
-27
30
V
VOH @MIN= 1.0V , VOH@ MAX= 2.375V
VOL @MIN= 1.2V , VOL@ MAX= 0.3V
VOL = 0.4 V, VOH = 2.0 V
VOH = 0.4 V, VOL = 2.0 V
VT = 1.25 V
-27
27
mA
mA
ns
ns
%
1
tr2B
0.4
0.4
45
1.6
1.6
55
1
Fall Time
tf2B
1
Duty Cycle
dt2B
1
Skew
tsk2B
VT = 1.25 V
250
250
ps
ps
1
tjcyc-cyc
VT = 1.25 V
Jitter
1Guarenteed by design, not 100% tested in production.
Electrical Characteristics - 3V66
TA = 0 - 70C; VDD = 3.3 V+/-5%; CL = 10-30 pF (unless otherwise stated)
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
CONDITIONS
MIN
12
TYP MAX UNITS
1
RDSP1
VO = VDD*(0.5)
VO = VDD*(0.5)
IOH = -1 mA
55
55
Ω
Ω
1
RDSN1
12
VOH1
VOL1
IOH1
IOL1
2.4
V
IOL = 1 mA
0.55
-33
38
V
VOH@ MIN = 1.0 V, VOH@ MAX = 3.135 V
VOL@ MIN = 1.95 V, VOL@ MAX= 0.4
VOL = 0.4 V, VOH = 2.4 V
-33
30
mA
mA
ns
ns
%
1
tr1
0.5
0.5
45
2
1
Fall Time
tf1
VOH = 2.4 V, VOL = 0.4 V
2
1
Duty Cycle
dt1
VT = 1.5 V
55
1
Skew
tsk1
VT = 1.5 V
VT = 1.5 V
175
500
ps
ps
tjcyc-cyc
Jitter
1Guarenteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
6
ICS9248-138
Preliminary Product Preview
Electrical Characteristics - IOAPIC
TA = 0 - 70C;VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
1
RDSP4B
VO = VDD*(0.5)
VO = VDD*(0.5)
IOH = -5.5 mA
IOL = 9.0 mA
9
9
2
30
30
Ω
Ω
1
RDSN4B
VOH4\B
VOL4B
IOH4B
IOL4B
V
0.4
-27
30
V
VOH@ min = 1.0 V, VOH@ MAX = 2.375 V
VOL@ MIN = 1.2 V, VOL@ MAX= 0.3 V
VOL = 0.4 V, VOH = 2.0 V
VOH = 2.0 V, VOL = 0.4 V
VT = 1.25 V
-27
27
mA
mA
ns
1
tr4B
0.4
0.4
45
1.6
1.6
55
1
Fall Time
tf4B
ns
1
Duty Cycle
dt4B
%
1
Skew
tsk4
250
500
ps
tjcyc-cyc
VT = 1.25 V
Jitter
ps
1Guarenteed by design, not 100% tested in production.
Electrical Characteristics - SDRAM
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 20 - 30 pF (unless otherwise stated)
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
CONDITIONS
MIN
10
TYP MAX UNITS
1
RDSP3
VO = VDD*(0.5)
VO = VDD*(0.5)
IOH = -1 mA
24
24
Ω
Ω
1
RDSN3
10
VOH3
VOL3
IOH3
IOL3
2.4
V
IOL = 1 mA
0.4
-46
53
V
VOH @MIN= 2.0 V, VOH@ MAX=3.135 V
VOL@ MIN= 1.0 V, VOL@ MAX=0.4 V
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
-54
54
mA
mA
ns
ns
%
1
Tr3
0.4
0.4
45
1.6
1.6
55
1
Fall Time
Tf3
1
Duty Cycle
Dt3
1
Skew
Tsk3
VT = 1.5 V
250
250
ps
ps
tjcyc-cyc VT = 1.5 V
Jitter
1Guarenteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
7
ICS9248-138
Preliminary Product Preview
Electrical Characteristics - PCI
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise stated)
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
CONDITIONS
MIN
12
TYP MAX UNITS
1
RDSP1
VO = VDD*(0.5)
VO = VDD*(0.5)
IOH = -1 mA
55
55
Ω
Ω
1
RDSN1
12
VOH1
VOL1
IOH1
IOL1
2.4
V
IOL = 1 mA
0.55
-33
38
V
VOH@ MIN = 1.0 V, VOH@ MAX = 3.135 V -33
mA
mA
ns
ns
%
VOL@ MIN = 1.95 V, VOL@ MAX= 0.4
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
30
0.5
0.5
45
1
tr1
2
1
Fall Time
tf1
2
1
Duty Cycle
dt1
55
1
Skew
tsk1
VT = 1.5 V
VT = 1.5 V
500
500
ps
ps
tjcyc-cyc
Jitter
1Guarenteed by design, not 100% tested in production.
Electrical Characteristics - REF, 48MHz_0
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 10 -20 pF (unless otherwise stated)
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
CONDITIONS
VO = VDD*(0.5)
MIN
TYP
MAX UNITS
1
Ω
Ω
RDSP5
20
20
60
60
1
RDSN5
VO = VDD*(0.5)
VOH5
VOL5
IOH5
IOL5
IOH = 1 mA
2.4
V
IOL = -1 mA
0.4
-23
27
V
VOH @MIN=1 V, VOH@MAX= 3.135 V
VOL@MIN=1.95 V, VOL@MIN=0.4 V
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
-29
29
mA
mA
ns
ns
%
1
tr5
4
1
Fall Time
tf5
4
1
Duty Cycle
dt5
45
55
Skew
Tsk
VT = 1.5 V
250
500
1000
ps
ps
ps
1
tjcyc-cyc
VT = 1.5 V; Fixed Clocks
VT = 1.5 V; Ref Clocks
Jitter
1
tjcyc-cyc
1Guarenteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
8
ICS9248-138
Preliminary Product Preview
General I2C serial interface information
The information in this section assumes familiarity with I2C programmingꢀ
For more information, contact ICS for an I2C programming application noteꢀ
How to Write:
Controller (host) sends a start bitꢀ
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
How to Read:
Controller (host) will send start bitꢀ
Controller (host) sends the read address D3 (H)
ICS clock will acknowledge
Controller (host) sends a dummy command code
ICS clock will acknowledge
ICS clock will send the byte count
Controller (host) acknowledges
Controller (host) sends a dummy byte count
ICS clock will acknowledge
Controller (host) starts sending first byte (Byte 0)
through byte 5
ICS clock sends first byte (Byte 0) through byte 5
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit
ICS clock will acknowledge each byte one at a timeꢀ
Controller (host) sends a Stop bit
How to Write:
Controller (Host)
ICS (Slave/Receiver)
How to Read:
Start Bit
Controller (Host)
ICS (Slave/Receiver)
Address
Start Bit
D2(H)
Address
D3(H)
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Dummy Command Code
ACK
Byte Count
Dummy Byte Count
Byte 0
ACK
ACK
ACK
ACK
ACK
ACK
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
ACK
Stop Bit
Stop Bit
Notes:
1ꢀ
The ICS clock generator is a slave/receiver, I2C componentꢀ It can read back the data stored in the latches for
verificationꢀ Read-Back will support Intel PIIX4 "Block-Read" protocolꢀ
2ꢀ
3ꢀ
4ꢀ
5ꢀ
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3ꢀ3V logic levelsꢀ
The data byte format is 8 bit bytesꢀ
To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controllerꢀ The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferredꢀ The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytesꢀ The data is loaded until a Stop sequence is issuedꢀ
6ꢀ
At power-on, all registers are set to a default condition, as shownꢀ
Third party brands and names are the property of their respective owners.
9
ICS9248-138
Preliminary Product Preview
Shared Pin Operation -
Input/Output Pins
Figure 1 shows a means of implementing this function when
a switch or 2 pin header is usedꢀ With no jumper is installed
the pin will be pulled highꢀ With the jumper in place the pin
will be pulled lowꢀ If programmability is not necessary, than
only a single resistor is necessaryꢀThe programming resistors
should be located close to the series termination resistor to
minimize the current loop areaꢀ It is more important to locate
the series termination resistor close to the driver than the
programming resistorꢀ
The I/O pins designated by (input/output) on the ICS9248-
138 serve as dual signal functions to the deviceꢀ During initial
power-up, they act as input pinsꢀ The logic level (voltage)
that is present on these pins at this time is read and stored
into a 5-bit internal data latchꢀ At the end of Power-On reset,
(seeAC characteristics for timing values), the device changes
the mode of operations for these pins to an output functionꢀ
In this mode the pins produce the specified buffered clocks
to external loadsꢀ
To program (load) the internal configuration register for these
pins, a resistor is connected to either the VDD (logic 1) power
supply or the GND (logic 0) voltage potentialꢀ A 10 Kilohm
(10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating periodꢀ
Via to
VDD
Programming
Header
2K W
Via to Gnd
Device
Pad
8.2K W
Clock trace to load
Series Term. Res.
Fig. 1
Third party brands and names are the property of their respective owners.
10
ICS9248-138
Preliminary Product Preview
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the partꢀ PD# is
an asynchronous active low inputꢀ This signal needs to be synchronized internal to the device prior to powering down the clock
synthesizerꢀ
Internal clocks are not running after the device is put in power downꢀ When PD# is active low all clocks need to be driven to a
low value and held prior to turning off the VCOs and crystalꢀ The power up latency needs to be less than 3 mSꢀ The power down
latency should be as short as possible but conforming to the sequence requirements shown belowꢀ The REF and 48MHz clocks
are expected to be stopped in the LOW state as soon as possibleꢀ Due to the state of the internal logic, stopping and holding
the REF clock outputs in the LOW state may require more than one clock cycle to completeꢀ
PD#
CPUCLK
3V66
PCICLK
VCO
Crystal
Notes:
1ꢀ All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device)ꢀ
2ꢀ As shown, the outputs Stop Low on the next falling edge after PD# goes lowꢀ
3ꢀ PD# is an asynchronous input and metastable conditions may existꢀ This signal is synchronized inside this partꢀ
4ꢀ The shaded sections on the VCO and the Crystal signals indicate an active clockꢀ
5ꢀ Diagrams shown with respect to 133MHzꢀ Similar operation when CPU is 100MHzꢀ
Third party brands and names are the property of their respective owners.
11
ICS9248-138
Preliminary Product Preview
SYMBOL
In Millimeters
In Inches
COMMON DIMENSIONS
COMMON DIMENSIONS
MIN
MAX
2.794
0.406
0.343
0.254
MIN
.095
.008
.008
.005
MAX
.110
.016
.0135
.010
A
A1
b
2.413
0.203
0.203
0.127
c
SEE VARIATIONS
SEE VARIATIONS
D
E
E1
e
10.033
7.391
10.668
7.595
.395
.291
.420
.299
0.635 BASIC
0.025 BASIC
h
0.381
0.508
0.635
1.016
.015
.020
.025
.040
L
SEE VARIATIONS
SEE VARIATIONS
N
α
0°
8°
0°
8°
VARIATIONS
N
D mm.
D (inch)
MIN
MAX
MIN
MAX
16.002
18.542
48
56
15.748
18.288
.620
.720
.630
.730
JEDEC MO-118
6/1/00
DOC# 10-0034
REV B
Ordering Information
ICS9248yF-138
Example:
ICS XXXX y F - PPP - T
Designation for tape and reel packaging
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
ADVANCE INFORMATION documents contain information on products
in the formative or design phase development. Characteristic data and
other specifications are design goals. ICS reserves the right to change or
discontinue these products without notice.
Third party brands and names are the property of their respective owners.
12
相关型号：
ICS9248YF-146-T
Processor Specific Clock Generator, 166.67MHz, PDSO48, 0.300 INCH, MO-118, SSOP-48
IDT
ICS9248YF-146LF-T
Processor Specific Clock Generator, 166.67MHz, PDSO48, 0.300 INCH, LEAD FREE, MO-118, SSOP-48
IDT
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