ICS9248YF-90-T [ICSI]
Frequency Generator & Integrated Buffers for PENTIUM/ProTM; 频率发生器和缓冲器集成奔腾/ ProTM
| 型号： | ICS9248YF-90-T |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Frequency Generator & Integrated Buffers for PENTIUM/ProTM |
| 文件： | 总16页 (文件大小：283K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated
Circuit
Systems, Inc.
ICS9248-90
Frequency Generator & Integrated Buffers for PENTIUM/ProTM
General Description
Features
•
•
•
•
•
3.3V outputs: SDRAM, PCI, REF, 48/24MHz
The ICS9248-90 generates all clocks required for high speed
RISC or CISC microprocessor systems such as Intel
PentiumPro or Cyrix. Eight different reference frequency
multiplying factors are externally selectable with smooth
frequency transitions.
2.5V outputs: CPU, IOAPIC
20 ohm CPU clock output impedance
20 ohm PCI clock output impedance
Skew from CPU (earlier) to PCI clock - 1.5 to 4 ns,
center 2.6 ns.
•
•
•
•
No external load cap for CL=18pF crystals
±175 ps CPU clock skew
Features include two CPU, six PCI and thirteen SDRAM
clocks. Two reference outputs are available equal to the crystal
frequency. Plus the IOAPIC output powered by VDDL1. One
48 MHz for USB, and one 24 MHz clock for Super IO. Spread
Spectrum built in at ±0.25% modulation to reduce the EMI.
Serial programming I2C interface allows changing functions,
stop clock programing and Frequency selection.Additionally,
the device meets the Pentium power-up stabilization, which
requires that CPU and PCI clocks be stable within 2ms after
power-up. It is not recommended to use I/O dual function pin
for the slots (ISA, PIC, CPU, DIMM). The add on card might
have a pull up or pull down.
250ps (cycle to cycle) CPU jitter
Smooth frequency switch, with selections from 66.8
to 133 MHz CPU.
•
•
•
•
•
•
I2C interface for programming
3ms power up clock stable time
Clock duty cycle 45-55%.
48 pin 300 mil SSOP package
3.3V operation, 5V tolerant inputs (with series R)
<5ns propagation delay SDRAM from Buffer Input
Pin Configuration
High drive PCICLK and SDRAM outputs typically provide
greaterthan1V/nsslewrateinto30pFloads. CPUCLKoutputs
typically provide better than 1V/ns slew rate into 20pF loads
while maintaining 50 ±5% duty cycle. The REF and 24 and
48 MHz clock outputs typically provide better than 0.5V/ns
slew rates into 20pF.
Block Diagram
PLL2
48MHz
24MHz
/2
X1
X2
XTAL
OSC
48-Pin SSOP
STOP
IOAPIC
* Internal Pull-up Resistor of 240K to VDD
** Internal Pull-down resistor of 240K to GND
BUFFER IN
REF(0:1)
2
CPUCLK_F
CPUCLK 1
PLL1
Spread
Spectrum
STOP
STOP
Power Groups
VDDREF = REF (0:1), X1, X2
VDDPCI=PCICLK_F, PCICLK(0:4)
VDDSDR = SDRAM (0:12), supply for PLL core
VDD48 = 24MHz, 48MHz
4
FS(0:3)
MODE
SDRAM (0:11)
SDRAM_F
LATCH
POR
12
4
PCI
CLOCK
DIVDER
CPU_STOP#
PCI_STOP#
STOP
PCICLK (0:4)
PCICLKF
5
VDDLIOAPIC=IOAPIC
VDDLCPU=CPUCLK1, CPUCLK_F
Control
Logic
SDATA
SCLK
Config.
Reg.
Pentium is a trademark of Intel Corporation
I2C is a trademark of Philips Corporation
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
9248-90RevC4/19/00
information being relied upon by the customer is current and accurate.
ICS9248-90
Pin Descriptions
PIN NUMBER
PIN NAME
TYPE
DESCRIPTION
1
VDDREF
PWR Ref (0:2), XTAL power supply, nominal 3.3V
14.318 Mhz reference clock.This REF output is the STRONGER
buffer for ISA BUS loads
REF0
OUT
2
Halts PCICLK(0:4) clocks at logic 0 level, when input low (In
mobile mode, MODE=0)
PCI_STOP#1
GND
IN
3,9,16,22,
33,39,45
PWR Ground
Crystal input, has internal load cap (36pF) and feedback
resistor from X2
4
X1
IN
Crystal output, nominally 14.318MHz. Has internal load
cap (36pF)
5
X2
OUT
6,14
VDDPCI
PCICLK_F
PWR Supply for PCICLK_F and PCICLK (0:4), nominal 3.3V
Free running PCI clock not affected by PCI_STOP# for power
management.
OUT
7
Pin 17, pin 18 function select pin, 1=Desktop Mode, 0=Mobile
Mode. Latched Input.
MODE 2
FS3 2
IN
IN
Frequency select pin. Latched Input. Internal Pull-down to GND
8
PCI clock outputs. Syncheronous to CPU clocks with 1-48ns skew
(CPU early)
PCICLK0
OUT
PCI clock output. Syncheronous to CPU clocks with 1-48ns skew
(CPU early)
Frequency select pin. Latched Input.
PCICLK1
FS4 2
OUT
IN
10
PCI clock outputs. Syncheronous to CPU clocks with 1-48ns skew
(CPU early)
Input to Fanout Buffers for SDRAM outputs.
11, 12, 13
15
PCICLK(2:4)
BUFFER IN
OUT
IN
17, 18, 20, 21,
28, 29, 31, 32,
34, 35,37,38
SDRAM clock outputs, Fanout Buffer outputs from BUFFER IN pin
(controlled by chipset).
SDRAM (11:0)
OUT
19,30,36
23
VDDSDR
SDATA
SCLK
PWR Supply for SDRAM (0:12) and CPU PLL Core, nominal 3.3V.
IN
IN
Data input for I2C serial input, 5V tolerant input
Clock input of I2C input, 5V tolerant input
24
24MHz
FS2
OUT 24MHz output clock
25
26
IN
Frequency select pin. Latched Input.
48MHz
FS02
OUT 48MHz output clock
IN
Frequency select pin. Latched Input
27
40
VDD48
SDRAM_F
PWR Power for 24 & 48MHz output buffers and fixed PLL core.
OUT Free running SDRAM clock output. Not affected by CPU_STOP#
This asynchronous input halts CPUCLK1, IOAPIC & SDRAM
(0:11) at logic "0" level when driven low.
41
CPU_STOP#1
IN
42
43
44
VDDLCPU
CPUCLK1
CPUCLK_F
REF1
PWR Supply for CPU clocks, either 2.5V or 3.3V nominal
OUT CPU clock outputs, powered by VDDL2. Low if CPU_STOP#=Low
OUT Free running CPU clock. Not affected by the CPU_STOP#
OUT 14.318 MHz reference clock.
46
FS22
IN
Frequency select pin. Latched Input
47
48
IOAPIC
OUT IOAPIC clock output. 14.318 MHz Powered by VDDL1.
PWR Supply for IOAPIC, either 2.5 or 3.3V nominal
VDDLIOAPIC
Notes:
1: Internal Pull-up Resistor of 240K to 3.3V on indicated inputs
2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor to
program logic Hi to VDD or GND for logic low.
2
ICS9248-90
Mode Pin - Power Management Input Control
MODE, Pin 7
Pin 2
(Latched Input)
PCI_STOP#
0
(Input)
REF0
(Output)
1
Functionality
VDD = 3.3V±5%, VDDL = 2.5V±5% TA=0 to 70°C
Crystal (X1, X2) = 14.31818MHz
FS4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
FS3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
FS2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
FS1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
FS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CPU MHz
66.82
68.01
71.99
75.00
78.00
80.00
82.00
83.00
84.00
85.01
85.91
86.99
88.00
89.01
90.00
90.99
91.99
93.07
94.00
95.00
96.00
97.01
98.01
98.99
100.23
102.02
104.00
106.00
108.01
109.99
124.00
132.99
PCI MHz
33.40
34.00
35.99
37.49
38.99
39.99
41.00
41.50
41.99
42.50
42.95
43.49
43.99
44.50
44.99
45.49
30.66
31.02
31.33
31.66
31.99
32.33
32.67
32.99
33.41
34.01
34.66
35.33
36.00
36.66
30.99
33.25
3
ICS9248-90
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default = 0)
Bit
Description
PWD
CPUCLK
MHz
PCICLK
MHz
Bit (2, 7:4)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
66.82
68.01
71.99
75.00
78.00
80.00
82.00
83.00
84.00
85.01
85.91
86.99
88.00
89.01
90.00
90.99
91.99
93.07
94.00
95.00
96.00
97.01
98.01
98.99
100.23
102.02
104.00
106.00
108.01
109.99
124.00
132.99
33.40
34.00
35.99
37.49
38.99
39.99
41.00
41.50
41.99
42.50
42.95
43.49
43.99
44.50
44.99
45.49
30.66
31.02
31.33
31.66
31.99
32.33
32.67
32.99
33.41
34.01
34.66
35.33
36.00
36.66
30.99
33.25
Bit
(2, 7:4)
XXX
Note1
0-Frequency is selected by hardware select, latched inputs
1-Frequency is selected by Bit 7:4,2
Bit 3
Bit 1
Bit 0
0
1
0
0- Normal
1- Spread spectrum enable
0- Running
1- Tristate all outputs
Note1: Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
4
ICS9248-90
Byte 1: CPU,Active/Inactive Register (1 = enable, 0 = disable)
Bit
Pin #
-
-
-
-
40
-
43
44
PWD
Description
Latched FS2#
Latched FS4#
(Reserved)
(Reserved)
SDRAM12 (Act/Inact)
(Reserved)
CPUCLK1 (Act/Inact)
CPUCLK_F (Act/Inact)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
X
1
1
1
1
1
1
Byte 2: PCI Active/Inactive Register (1 = enable, 0 = disable)
Bit
Pin #
-
7
PWD
Description
(Reserved)
PCICLK_F (Act/Inact)
(Reserved)
PCICLK4 (Act/Inact)
PCICLK3 (Act/Inact)
PCICLK2 (Act/Inact)
PCICLK1 (Act/Inact)
PCICLK0 (Act/Inact)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
1
1
1
1
-
14
12
11
10
8
Byte 3: SDRAMActive/Inactive Register (1 = enable, 0 = disable)
Bit
Pin #
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
26
25
-
X
X
1
1
1
1
1
1
MODE#
Latched FS0#
48MHz (Act/Inact)
24 MHz (Act/Inact)
(Reserved)
SDRAM (8:11) (Active/Inactive)
SDRAM (4:7) (Active/Inactive)
SDRAM (0:3) (Active/Inactive)
21,20,18,17
32,31,29,28
38,37,35,34
Notes:
1. Inactive means outputs are held LOW and are disabled from switching.
2. Latched Frequency Selects (FS#) will be inverted logic load of the input frequency select pin conditions.
5
ICS9248-90
Byte 4: Reserved Active/Inactive Register (1 = enable, 0 = disable)
Bit
Pin #
PWD
1
1
1
1
X
1
X
1
Description
(Reserved)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
(Reserved)
(Reserved)
(Reserved)
Latched FS1#
(Reserved)
Latched FS3#
(Reserved)
Byte 5: Peripheral Active/Inactive Register (1 = enable, 0 = disable)
Bit
Pin #
-
-
-
47
-
-
46
2
PWD
Description
(Reserved)
(Reserved)
(Reserved)
IOAPIC0 (Act/Inact)
(Reserved)
(Reserved)
REF1 (Act/Inact)
REF0 (Act/Inact)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
1
1
1
1
Notes:
1. Inactive means outputs are held LOW and are disabled from switching.
2. Latched Frequency Selects (FS#) will be inverted logic load of the input frequency select pin conditions.
6
ICS9248-90
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . 115°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70º C; Supply Voltage VDD, VDDL = 3.3 V+/-5% (unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input Low Current
SYMBOL
VIH
CONDITIONS
MIN
2
TYP
MAX UNITS
VDD+0.3
V
V
VIL
VSS-0.3
0.8
5
µA
IIH
VIN = VDD
0.1
2.0
A
µ
IIL1
VIN = 0 V; Inputs with no pull-up resistors
VIN = 0 V; Inputs with pull-up resistors
-5
A
µ
IIL2
-200
-100
87
IDD3.3OP66 CL = 0 pF; Select @ 66MHz
IDD3.3OP100 CL = 0 pF; Select @ 100MHz
IDD3.3OP124 CL = 0 pF; Select @ 124MHz
IDD3.3OP133 CL = 0 pF; Select @ 133MHz
170
180
mA
mA
Operating
Supply Current
120
144
149
Input frequency
Fi
VDD = 3.3 V
12
27
14.318
16
5
MHz
pF
Input Capacitance1
CIN
Logic Inputs
CINX
X1 & X2 pins
36
45
3
pF
Clk Stabilization1
TSTAB
From VDD = 3.3 V to 1% target Freq.
ms
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70º C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V+/-5% (unless otherwise stated)
PARAMETER
SYMBOL
IDD2.5OP66
IDD2.5OP100
IDD2.5OP124
IDD2.5OP133
tCPU-PCI
CONDITIONS
CL = 0 pF; Select @ 66.8 MHz
CL = 0 pF; Select @ 100 MHz
CL = 0 pF; Select @ 124 MHz
CL = 0 pF; Select @ 133 MHz
VT = 1.5 V; VTL = 1.25 V
MIN
TYP
7
MAX UNITS
30
mA
30
Operating
10
11
14
Supply Current
30
30
Skew1
1.5
2.7
4
ns
1Guaranteed by design, not 100% tested in production.
7
ICS9248-90
Electrical Characteristics - CPUCLK
TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
VOH2B
VOL2B
IOH2B
CONDITIONS
MIN
2
TYP
2.3
0.31
-36
26
MAX UNITS
V
IOH = -12.0 mA
IOL = 12 mA
VOH = 1.7 V
VOL = 0.7 V
0.4
-19
V
mA
mA
ns
IOL2B
19
1
tr2B
VOL = 0.4 V, VOH = 2.0 V
VOH = 2.0 V, VOL = 0.4 V
VT = 1.25 V, Freq. < 124 MHz
VT = 1.25 V, Freq. >= 124 MHz
VT = 1.25 V
1.1
1.1
49
1.6
1.6
1
Fall Time
tf2B
ns
1
Duty Cycle
dt2B
45
40
55
%
47
52
%
1
Skew
tsk2B
115
36
175
150
+250
250
ps
1
Jitter, One Sigma
Jitter, Absolute
Jitter, Cycle-to-cycle
tj1σ2B
VT = 1.25 V
ps
1
tjabs2B
VT = 1.25 V
-250
130
140
ps
1
tjcyc-cyc2B VT = 1.25 V
ps
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - SDRAM
TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 30 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
VOH3
CONDITIONS
MIN
2.4
TYP
2.85
0.35
-60
44
MAX UNITS
V
IOH = -25 mA
IOL = 20 mA
VOH = 2.0 V
VOL = 0.8 V
VOL3
0.4
-40
V
mA
mA
ns
IOH3
IOL3
41
45
1
Tr3
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.5
2.4
2.2
55
1
Fall Time
Tf3
1.6
ns
1
Duty Cycle
Dt3
51
%
Skew1
Tsk1
VT = 1.5 V
VT = 1.5 V
220
2.8
500
4
ps
ns
Propagation Delay
Tprop
1Guarenteed by design, not 100% tested in production.
8
ICS9248-90
Electrical Characteristics - PCICLK
TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 30 pF (unless otherwise stated)
PARAMETER
SYMBOL
VOH1
CONDITIONS
MIN
2.4
TYP
3.1
MAX UNITS
V
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
IOH = -11 mA
IOL = 9.4 mA
VOH = 2.0 V
VOL = 0.8 V
VOL1
0.17
-60
44
0.4
-22
V
IOH1
mA
mA
IOL1
25
45
Rise Time1
Fall Time1
Duty Cycle1
Skew1
tr1
tf1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.87
1.5
2.6
2.3
ns
ns
%
dt1
tsk1
49
55
VT = 1.5 V
124
70
500
150
500
400
ps
ps
ps
ps
Jitter, One Sigma1
Jitter, Absolute1
Jitter, Cycle-to-cycle1
tj1 1
σ
VT = 1.5 V
tjabs1
VT = 1.5 V
-500
160
130
tjcyc-cyc1 VT = 1.5 V
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - IOAPIC
TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
VOH4B
VOL4B
IOH4B
CONDITIONS
MIN
2
TYP
2.3
MAX UNITS
V
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
IOH = -8 mA
IOL = 12 mA
VOH = 1.7 V
VOL = 0.7 V
0.31
-25
27
0.4
-15
V
mA
mA
IOL4B
19
Rise Time1
Fall Time1
Duty Cycle1
Tr4B
Tf4 B
Dt4B
Tj1
VOL = 0.4 V, VOH = 2.0 V
VOH = 2.0 V, VOL = 0.4 V
VT = 1.25 V
1.4
1.3
2.2
2
ns
ns
%
ps
ps
ps
45
52
55
Jitter, One Sigma1
Jitter, Absolute1
Jitter, Cycle-to-cycle1
VT = 1.25 V
175
395
475
350
800
800
4B
σ
Tjabs4B
VT = 1.25 V
-800
tjcyc-cyc4B VT = 1.25 V
1Guaranteed by design, not 100% tested in production.
9
ICS9248-90
Electrical Characteristics - REF1:0
TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
VOH5
CONDITIONS
MIN
2.4
TYP
2.9
MAX UNITS
V
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
IOH = -12 mA
IOL = 10 mA
VOH = 2.0 V
VOL = 0.8 V
VOL5
0.33
-30
23
0.4
-22
V
IOH5
mA
mA
IOL5
16
Rise Time1
Fall Time1
Duty Cycle1
tr5
tf5
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
2.1
2.1
4
4
ns
ns
%
ps
ps
ps
dt5
tj1
45
52
55
Jitter, One Sigma1
Jitter, Absolute1
Jitter, Cycle-to-cycle1
VT = 1.5 V
200
520
790
400
800
1300
5
σ
tjabs5
VT = 1.5 V
-800
tjcyc-cyc5 VT = 1.5 V
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - 24MHz, 48MHz
TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
VOH5
CONDITIONS
MIN
2.4
TYP
2.9
0.3
-34
30
MAX UNITS
V
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
IOH = -12 mA
IOL = 12 mA
VOH = 2.0 V
VOL = 0.8 V
VOL5
0.4
-22
V
IOH5
mA
mA
IOL5
16
Rise Time1
Fall Time1
Duty Cycle1
tr5
tf5
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.6
1.7
4
4
ns
ns
%
ps
ps
ps
dt5
45
51.6
100
250
345
55
Jitter, One Sigma1
Jitter, Absolute1
Jitter, Cycle-to-cycle1
tj1 5
σ
VT = 1.5 V
400
800
1000
tjabs5
VT = 1.5 V
-800
tjcyc-cyc5 VT = 1.5 V
1Guaranteed by design, not 100% tested in production.
10
ICS9248-90
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
For more information, contact ICS for an I2C programming application note.
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D2(H)
ICS clock will acknowledge
How to Read:
Controller (host) will send start bit.
Controler (host) sends the read address D3 (H)
ICS clock will acknowledge
Controller (host) sends a dummy command code
ICS clock will acknowledge
ICS clock will send the byte count
Controller (host) acknowledges
Controller (host) sends a dummy byte count
ICS clock will acknowledge
Controller (host) starts sending first byte (Byte 0)
through byte 5
ICS clock sends first byte (Byte 0) through byte 5
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit
ICS clock will acknowledge each byte one at a time.
Controller (host) sends a Stop bit
How to Write:
Controller (Host)
ICS (Slave/Receiver)
How to Read:
Start Bit
Controller (Host)
ICS (Slave/Receiver)
Address
Start Bit
D2(H)
Address
D3(H)
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Dummy Command Code
ACK
Byte Count
Dummy Byte Count
Byte 0
ACK
ACK
ACK
ACK
ACK
ACK
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
ACK
Stop Bit
Stop Bit
Notes:
1.
The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for
verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.
2.
3.
4.
5.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.
6.
At power-on, all registers are set to a default condition, as shown.
11
ICS9248-90
Shared Pin Operation -
Input/Output Pins
Figure 1 shows a means of implementing this function when
a switch or 2 pin header is used. With no jumper is installed
the pin will be pulled high. With the jumper in place the pin
will be pulled low. If programmability is not necessary, than
only a single resistor is necessary.The programming resistors
should be located close to the series termination resistor to
minimize the current loop area. It is more important to locate
the series termination resistor close to the driver than the
programming resistor.
The I/O pins designated by (input/output) on the ICS9248-
90 serve as dual signal functions to the device. During initial
power-up, they act as input pins. The logic level (voltage)
that is present on these pins at this time is read and stored
into a 5-bit internal data latch. At the end of Power-On reset,
(seeAC characteristics for timing values), the device changes
the mode of operations for these pins to an output function.
In this mode the pins produce the specified buffered clocks
to external loads.
To program (load) the internal configuration register for these
pins, a resistor is connected to either the VDD (logic 1) power
supply or the GND (logic 0) voltage potential. A 10 Kilohm
(10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
Via to
VDD
Programming
Header
2K
Via to Gnd
Device
Pad
8.2K
Clock trace to load
Series Term. Res.
Fig. 1
12
ICS9248-90
CPU_STOP# Timing Diagram
CPU_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation.
CPU_STOP# is synchronized by the ICS9248-90. The minimum that the CPU clock is enabled (CPU_STOP# high pulse) is
100 CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be
stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPU clock on latency is
less than 4 CPU clocks and CPU clock off latency is less than 4 CPU clocks.
Notes:
1. All timing is referenced to the internal CPU clock.
2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized
to the CPU clocks inside the ICS9248-90.
3. IOAPIC output is Stopped Glitch Free by CPUSTOP# going low.
4. SDRAM-F output is controlled by Buffer in signal, not affected by the ICS9248-90
CPU_STOP# signal. SDRAM (0:11) are controlled as shown.
5. All other clocks continue to run undisturbed.
13
ICS9248-90
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9248-90. It is used to turn off the PCICLK (0:4) clocks for low power
operation. PCI_STOP# is synchronized by the ICS9248-90 internally. The minimum that the PCICLK (0:4) clocks are enabled
(PCI_STOP# high pulse) is at least 10 PCICLK (0:4) clocks. PCICLK (0:4) clocks are stopped in a low state and started with
a full high pulse width guaranteed. PCICLK (0:4) clock on latency cycles are only one rising PCICLK clock off latency is one
PCICLK clock.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS9248.
3. All other clocks continue to run undisturbed.
4. CPU_STOP# is shown in a high (true) state.
14
ICS9248-90
Ferrite
Bead
Ferrite
Bead
C2
22µF/20V
Tantalum
C2
22µF/20V
Tantalum
General Layout Precautions:
1) Use a ground plane on the top routing
layer of the PCB in all areas not used
by traces.
VDD
VDD
1
2
48
C3
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
2) Make all power traces and ground
traces as wide as the via pad for lower
inductance.
2
3
2.5V Power Route
C1
4
1
5
Clock Load
C1
C3
Notes:
6
1 All clock outputs should have
provisions for a 15pf capacitor
between the clock output and series
terminating resistor. Not shown in
all places to improve readability of
diagram.
7
C3
8
9
3.3V Power Route
Ground
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
2 Optional crystal load capacitors are
recommended. They should be
included in the layout but not
inserted unless needed.
3.3V Power Route
ConnectionstoVDD:
= Routed Power
= Ground Connection Key (component side copper)
= Ground Plane Connection
= Power Route Connection
= Solder Pads
= Clock Load
15
ICS9248-90
Ordering Information
ICS9248yF-90-T
Example:
ICS XXXX y F - PPP - T
Designation for tape and reel packaging
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
16
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