ICS9250-26_技术文档

Integrated

Circuit

Systems, Inc.

ICS9250-26

Frequency Generator & Integrated Buffers for Celeron & PII/III™

Recommended Application:

810/810E type chipset. Provides three CPU speeds

(66.6, 100, 133MHz) with SDRAM = 133.3MHz.

Pin Configuration

*FS2//REF0

VDD0

1

2

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

GNDL1

IOAPIC0

IOAPIC1

VDDL1

CPUCLK0

VDDL0

CPUCLK1

CPUCLK2

GNDL0

GND5

SDRAM0

SDRAM1

VDD5

SDRAM2

SDRAM3

GND5

SDRAM4

SDRAM5

VDD5

SDRAM6

SDRAM7

GND5

SDRAM_F

VDD5

PD#

Output Features:

X1

X2

GND0

GND1

3V66-0

3V66-1

VDD1

3

4

5

6

7

8

9

•

3 CPU (2.5V) 66.6/133.3MHz (up to 150MHz

achievable through I²C)

•

9 SDRAM (3.3V) @ 133.3MHz (up to 150MHz

achievable through I²C)

VDD2

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

•

8 PCI (3.3 V) @33.3MHz

PCICLK0

PCICLK1

PCICLK2

GND2

PCICLK3

PCICLK4

GND2

PCICLK5

PCICLK6

PCICLK7

VDD2

2 IOAPIC (2.5V) @ 33.3 MHz

2 Hublink clocks (3.3 V) @ 66.6 MHz

2 USB (3.3V) @ 48 MHz ( Non spread spectrum)

1 REF (3.3V) @ 14.318 MHz

Features:

•

Supports spread spectrum modulation ,

down spread 0 to -0.5% and

0.25% center spread.

VDD3

GND3

GND4

•

I²C support for power management

Efficient power management scheme through PD#

Uses external 14.138 MHz crystal

Alternate frequency selections available through I²C

control.

48MHz_0

48MHz_1

VDD4

SCLK

SDATA

FS1

FS0

56-Pin 300mil SSOP

* This input has a 120KΩ pull-down to GND.

Block Diagram

Functionality

FS2

FS1

FS0

Function

X

0

1

Tristate

Test

Active CPU = 66MHz

SDRAM = 100MHz

0

1

0

1

Active CPU = 100MHz

SDRAM = 100MHz

Active CPU = 133MHz

SDRAM = 100MHz

(Special Condition)

Active CPU = 133MHz

SDRAM = 133MHz

1

0

ICS reserves the right to make changes in the device data identified in

this publication without further notice. ICS advises its customers to

obtain the latest version of all device data to verify that any

9250-26 Rev B 01/19/01

Third party brands and names are the property of their respective owners.

information being relied upon by the customer is current and accurate.

ICS9250-26

General Description

The ICS9250-26 is a single chip clock solution for 810/810E type chipset. It provides all necessary clock signals for

such a system.

Spread spectrum may be enabled through I²C programming. Spread spectrum typically reduces EMI by 8dB to 10 dB. This

simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9250-26 employs a

proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations.

Pin Configuration

PIN NUMBER

PIN NAME

FS2

TYPE

DESCRIPTION

Function Select pin. Determines CPU frequency, all output

OUT

functionality (with 50Ω)

1

REF0

X1

OUT 3.3V, 14.318MHz reference clock output.

Crystal input, has internal load cap (33pF) and feedback

resistor from X2

3

4

OUT

Crystal output, nominally 14.318MHz. Has internal load

cap (33pF)

X2

OUT

47, 41, 35, 24, 23,

17, 14, 6, 5

GND (5:0)

3V66 [1:0]

VDD (5:0)

PWR Ground pins for 3.3V supply

8, 7

OUT 3.3V Fixed 66MHz clock outputs for HUB

PWR 3.3V power supply

44, 38, 33, 27, 22,

21, 10, 10, 9, 2

20,19,18,16,

15,13,12,11

PCICLK (7:0)

48MHz (1:0)

FS (1:0)

OUT 3.3V PCI clock outputs, with Synchronous CPUCLKS

OUT 3.3V Fixed 48MHz clock outputs for USB

26, 25

29, 28

30

Function Select pins. Determines CPU frequency, all output

OUT

functionality. Please refer to Functionality table on page 3.

SDATA

IN

Data input for I²C serial input.

31

SCLK

Clock input of I²C input

Asynchronous active low input pin used to power down the device

into a low power state. The internal clocks are disabled and the

VCO and the crystal are stopped. The latency of the power down

will not be greater than 3ms.

32

PD#

IN

36, 37, 39, 40, 42,

43, 45, 46

3.3V output running 100MHz. All SDRAM outputs can be turned

off through I²C

SDRAM (7:0)

SDRAM_F

OUT

34

OUT 3.3V free running 100MHz SDRAM not affected by I²C

PWR Ground for 2.5V power supply for CPU & APIC

56,48

GNDL (1:0)

CPUCLK (2:0)

2.5V Host bus clock output. 66MHz or 100MHz 133MHz

depending on FS pins

52, 50, 49

OUT

51, 53

54, 55

VDDL (1:0)

PWR 2.5V power suypply for CPU & IOAPIC

OUT 2.5V clock outputs running at 33.3MHz.

IOAPIC (1:0)

2

ICS9250-26

Maximum Allowed Current

Max 2.5V supply consumption

Max discrete cap loads,

Vddq2 = 3.465V

Max discrete cap loads,

Vddq2 = 2.625V

810E

Condition

All static inputs = Vddq3 or GND All static inputs = Vddq3 or GND

Powerdown Mode

10mA

70mA

10mA

280mA

(PWRDWN# = 0

Full Active 66MHz

SEL1, 0 = 10

Full Active 100MHz

SEL1, 0 = 11

100mA

Clock Enable Configuration

REF,

48MHz

PD# CPUCLK SDRAM IOAPIC 66MHz PCICLK

Osc VCOs

0

1

LOW

ON

LOW

ON

LOW

ON

LOW

ON

LOW

ON

LOW

ON

OFF

ON

OFF

ON

Power Groups*

VDD0, GND0 = REF & Crystal

VDD1, GND1=3V66

VDD2, GND2=PCICLK

VDD3, GND3 = PLL core

VDD4, GND4 = 48MHz

VDD5, GND5 = SDRAM_F, SDRAM

VDDL0, GNDL0=CPUCLK

VDDL1, GNDL1=IOAPIC

* To ensure the processor will power up to the desired frequency, the 3.3V supply to the ICS9250-26 needs to reach a stable

condition before the 2.5V supply does. In most systems, the power up ramp of the 2.5V is slower than the 3.3V ramp. For those

instances, no special requirements are necessary.

3

ICS9250-26

General I²C serial interface information

The information in this section assumes familiarity with I²C programming.

For more information, contact ICS for an I²C programming application note.

How to Write:

• Controller (host) sends a start bit.

• Controller (host) sends the write address D2 _(H)

• ICS clock will acknowledge

How to Read:

• Controller (host) will send start bit.

• Controller (host) sends the read address D3 _(H)

• ICS clock will acknowledge

• Controller (host) sends a dummy command code

• ICS clock will acknowledge

• ICS clock will send the byte count

• Controller (host) acknowledges

• Controller (host) sends a dummy byte count

• ICS clock will acknowledge

• Controller (host) starts sending first byte (Byte 0)

through byte 5

• ICS clock sends first byte (Byte 0) through byte 5

• Controller (host) will need to acknowledge each byte

• Controller (host) will send a stop bit

• ICS clock will acknowledge each byte one at a time.

• Controller (host) sends a Stop bit

How to Write:

Controller (Host)

ICS (Slave/Receiver)

How to Read:

Start Bit

Controller (Host)

ICS (Slave/Receiver)

Address

Start Bit

D2_(H)

Address

D3_(H)

ACK

Dummy Command Code

ACK

Byte Count

Dummy Byte Count

Byte 0

ACK

Byte 0

Byte 1

Byte 2

Byte 3

Byte 4

Byte 5

Byte 1

Byte 2

Byte 3

Byte 4

Byte 5

ACK

Stop Bit

Notes:

1.

The ICS clock generator is a slave/receiver, I²C component. It can read back the data stored in the latches for

verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.

2.

3.

4.

5.

The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)

The input is operating at 3.3V logic levels.

The data byte format is 8 bit bytes.

To simplify the clock generator I²C interface, the protocol is set to use only "Block-Writes" from the controller. The

bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte

has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those

two bytes. The data is loaded until a Stop sequence is issued.

6.

At power-on, all registers are set to a default condition, as shown.

4

ICS9250-26

Byte 5: ICS Reserved Functionality and frequency select register (Default as noted in PWD)

Bit

Desctiption

PWD

Bit7

Bit6

Bit5

ICS RESERVED BIT (Needs to be 0 clock to operate normal)

Bit (3,0)

0

CPUCLK SDRAM 3V66 PCICLK

FS2

(HW)

FS0

SEL1

(Bit3)

SEL0

(Bit0)

MHz

(HW)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

66.67

70.00

100.00

105.00

109.00

112.00

100.00

105.00

109.00

112.00

133.34

105.00

90.00

66.60

70.00

72.67

74.66

66.60

70.00

72.67

74.66

88.66

70.00

60.00

82.66

66.60

75.00

70.00

66.60

33.30

35.00

36.33

37.33

33.30

35.00

36.33

37.33

44.33

35.00

30.00

41.33

33.30

37.50

35.00

33.30

72.67

74.67

100.00

105.00

109.00

112.01

133.34

140.00

120.00

124.00

133.34

150.00

140.00

132.99

Bit

(3,0)

XXXX

Note 1

124.00

100.00

150.00

140.00

132.99

0 = Down Spread Spread Spectrum 0 to -.5%

1 = Center Spread Spread Spectrum ± .25%

Bit4

0

Bit2

Bit1

Not used (Needs to be 1 for normal clock operation)

1

Note1: Default at power-up will be for Bit 3 and Bit 0 to be 00, with external hardware selection of FS0, FS2

defining specific frequency.

5

ICS9250-26

Byte 0: Control Register

(1 = enable, 0 = disable)

Bit

Pin#

Name

Reserved ID

PWD

Description

(Active/Inactive)

Bit 7

Bit 6

Bit 5

Bit 4

0

1

SpreadSpectrum

(1=On/0=Off)

Bit 3

1

(Active/Inactive)

Bit 2

Bit 1

Bit 0

26

25

49

48MHz 1

48MHz 0

CPUCLK2

1

0

(Active/Inactive)

Note: Do not write in ID bits, these bits are for ICS internal use only.

Must write a '1' in bit 0 after read back.

Byte 1: Control Register

(1 = enable, 0 = disable)

Bit

Pin#

36

37

39

40

42

43

45

46

Name

SDRAM7

PWD

Description

(Active/Inactive)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

1

SDRAM6

SDRAM5

SDRAM4

SDRAM3

SDRAM2

SDRAM1

SDRAM0

Byte 2: Control Register

(1 = enable, 0 = disable)

Bit

Pin#

20

19

18

16

15

13

12

-

Name

PCICLK7

PWD

Description

(Active/Inactive)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

1

PCICLK6

PCICLK5

PCICLK4

PCICLK3

PCICLK2

PCICLK1

Reserved

Notes:

1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be

configured at power-on and are not expected to be configured during the normal modes of operation.

2. PWD = Power on Default

6

ICS9250-26

Byte 3: Reserved Register

(1 = enable, 0 = disable)

Bit

Pin#

Name

Reserved

PWD

Description

(Active/Inactive)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

-

0

Reserved

Byte 4: Reserved Register

(1 = enable, 0 = disable)

Bit

Pin#

Name

Reserved

PWD

Description

(Active/Inactive)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

-

0

Reserved

Notes:

1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be

configured at power-on and are not expected to be configured during the normal modes of operation.

2. PWD = Power on Default

7

ICS9250-26

Absolute Maximum Ratings

Core Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . 4.6 V

I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 3.6V

Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to V_DD+0.5 V

Ambient Operating Temperature . . . . . . . . . . . . . 0°C to +70°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C

Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 115°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are

stress specifications only and functional operation of the device at these or any other conditions above those listed in the

operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods

may affect product reliability.

Electrical Characteristics - Input/Supply/Common Output Paramete

T_A= 0 - 70C; Supply Voltage V_DD= 3.3 V +/-5%, V_DDL= 2.5 V +/-5% (unless otherwise stated)

PARAMETER

Input High Voltage

Input Low Voltage

Input High Current

SYMBOL

V_IH

CONDITIONS

MIN

2

TYP

MAX

V_DD+0.3

0.8

UNITS

V

V_IL

V_SS-0.3

-5

I_IH

V_IN= V_DD

5

A

µ

I_IL1

V_IN= 0 V; Inputs with no pull-up resistors

V_IN= 0 V; Inputs with pull-up resistors

C_L= 0 pF; Select @ 66 MHz

-5

2

Input Low Current

A

µ

I_IL2

-200

-100

97

110

105

130

310

300

mA

C_L= 0 pF; Select @ 100 MHz

91

C_L= 0 pF; Select @ 133 MHz

100

275

267

I_DD3.3OP

C_L= Max loads; Select @ 66 MHz

C_L= Max loads; Select @ 100 MHz

C_L= Max loads; Select @ 133 MHz

C_L= 0 pF; Select @ 66 MHz

278

8

350

10

Operating Supply

Current

C_L= 0 pF; Select @ 100 MHz

C_L= 0 pF; Select @ 133 MHz

C_L= Max loads; Select @ 66 MHz

C_L= Max loads; Select @ 100 MHz

11

13

22

31

15

20

I_DD2.5OP

70

100

C_L= Max loads; Select @ 133 MHz

C_L= Max loads

37

130

I^{DD3.3P D}

I^{DD.25P D}

Fⁱ

220

<1

400

10

Powerdown Current

A

µ

Input address VDD or GND

V^DD= 3.3 V

Input Frequency

Pin Inductance

12

27

14.318

7

16

MHz

nH

pF

L^pin

C^IN

Logic Inputs

5

Input Capacitance¹

C^OUT

C^INX

Output pin capacitance

X1 & X2 pins

6

pF

45

5

pF

Transition time¹

Settling time¹

Clk Stabilization¹

T^trans

T^s

To 1st crossing of target frequency

ms

From 1st crossing to 1% target frequency

5

T^STAB

From V^DD= 3.3 V to 1% target frequency

Output enable delay (all outputs)

Output disable delay (all outputs)

5

ms

ns

t^{P ZH},t^{P ZL}

1

10

Delay¹

t^{P HZ},t^{P LZ}

¹Guaranteed by design, not 100% tested in production.

8

ICS9250-26

Electrical Characteristics - CPU

T_A= 0 - 70C; V_DDL= 2.5 V +/-5%; C_L= 10-20 pF (unless otherwise specified)

PARAMETER

Output Impedance

Output High Voltage

Output Low Voltage

SYMBOL

CONDITIONS

MIN

13.5

2

TYP

MAX UNITS

1

R_DSP2B

V_O= V_DD*(0.5)

I_OH= -1 mA

16

21

45

Ω

V

1

R_DSN2B

V_OH2B

V_OL2B

I_OL= 1 mA

0.4

-27

V

_{OH @ MIN}= 1.0 V

_{OH @ MAX}= 2.375 V

-27

27

-68

-9

I_OH2B

I_OL2B

Output High Current

mA

V

V_{OL @ MIN}= 1.2 V

_{OL @ MAX}= 0.3 V

54

11

Output Low Current

V

30

Rise Time¹

Fall Time¹

t_r2B

t_f2B

V_OL= 0.4 V, V_OH= 2.0 V

0.4

1.1

1.6

ns

V_OH= 2.0 V, V_OL= 0.4 V

V_T= 1.25 V, 66, 100 MHz

V_T= 1.25 V, 133 MHz

0.4

45

40

1.1

49

48

1.6

55

Duty Cycle¹

d_t2B

%

ps

Skew window¹

Jitter, Cycle-to-cycle¹

t_sk2B

V_T= 1.25 V

65

90

175

250

t_jcyc-cyc2BV_T= 1.25 V

¹Guaranteed by design, not 100% tested in production.

Electrical Characteristics - 3V66

T_A= 0 - 70C; V_DD= 3.3 V +/-5%; C_L= 10-20 pF (unless otherwise specified)

PARAMETER

Output Impedance

Output High Voltage

Output Low Voltage

SYMBOL

CONDITIONS

MIN

12

TYP

14

MAX UNITS

1

R_DSP1B

V_O= V_DD*(0.5)

I_OH= -1 mA

55

Ω

V

1

R_DSN1B

12

14.5

V_OH1

V_OL1

2.4

I_OL= 1 mA

0.55

-33

V_{OH @ MIN}= 1.0 V

V_{OH @ MAX}= 3.135 V

V_{OL @ MIN}= 1.95 V

-33

30

-108

-9

I_OH1

Output High Current

mA

95

I_OL1

t_r1

Output Low Current

V

_{OL @ MAX}= 0.4 V

29

38

1.6

55

Rise Time¹

Fall Time¹

V_OL= 0.4 V, V_OH= 2.4 V

V_OH= 2.4 V, V_OL= 0.4 V

V_T= 1.5 V

0.4

45

1.2

49

ns

%

ps

t_f1

Duty Cycle¹

d_t1

Skew window¹

t_sk1

V_T= 1.5 V

65

175

500

Jitter, Cycle-to-cycle¹

t_jcyc-cyc1

V_T= 1.5 V

120

¹Guaranteed by design, not 100% tested in production.

9

ICS9250-26

Electrical Characteristics - IOAPIC

T_A= 0 - 70C; V_DDL= 2.5 V +/-5%; C_L= 10-20 pF (unless otherwise specified)

PARAMETER

Output Impedance

Output High Voltage

Output Low Voltage

SYMBOL

CONDITIONS

MIN

TYP

16

MAX UNITS

1

R_DSP4B

V_O= V_DD*(0.5)

I_OH= -1 mA

9

2

30

Ω

V

1

R_DSN4B

20

V_OH4B

V_OL4B

I_OL= 1 mA

0.4

-27

V_{OH @ MIN}= 1.0 V

V_{OH @ MAX}= 2.375 V

V_{OL @ MIN}= 1.2 V

V_{OL @ MAX}= 0.3 V

-27

27

-68

-9

Output High Current

I^OH4B

mA

54

11

Output Low Current

I^OL4B

t^r4B

30

1.6

55

Rise Time¹

Fall Time¹

Duty Cycle¹

Skew window¹

V^OL= 0.4 V, V^OH= 2.0 V

V^OH= 2.0 V, V^OL= 0.4 V

V^T= 1.25 V

0.4

45

1.1

49

ns

%

t^{f4 B}

d^t4B

t^sk4B

V^T= 1.25 V

25

250

500

ps

Jitter, Cycle-to-cycle¹

t^jcyc-cyc4B

V^T= 1.25 V

150

¹Guaranteed by design, not 100% tested in production.

Electrical Characteristics - SDRAM

T_A= 0 - 70C; V_DD= 3.3 V +/-5%; C_L= 20-30 pF (unless otherwise specified)

PARAMETER

Output Impedance

SYMBOL

CONDITIONS

MIN

10

TYP

12

MAX UNITS

1

R_DSP3B

V_O= V_DD*(0.5)

24

Ω

1

R_DSN3B

10

15

V

_{OH @ MIN}= 2.0 V

-54

-92

-16

68

I_OH3

Output High Current

mA

_{OH @ MAX}= 3.135 V

_{OL @ MIN}= 1.0 V

_{OL @ MAX}= 0.4 V

-46

54

I_OL3

t_r3

Output Low Current

mA

29

53

1.6

55

Rise Time¹

Fall Time¹

Duty Cycle¹

Skew window¹

V_OL= 0.4 V, V_OH= 2.4 V

V_OH= 2.4 V, V_OL= 0.4 V

V_T= 1.5 V

0.4

45

1

ns

%

ps

t_f3

1.5

52

d_t3

t_sk3

V_T= 1.5 V

85

250

V_T= 1.5 V, 66, 100 MHz

V_T= 1.5 V, 133 MHz

120

Jitter, Cycle-to-cycle¹

t_jcyc-cyc3

ps

150

300

¹Guaranteed by design, not 100% tested in production.

10

ICS9250-26

Electrical Characteristics - PCI

T_A= 0 - 70C; V_DD= 3.3 V +/-5%; C_L= 10-30 pF (unless otherwise specified)

PARAMETER

Output Impedance

Output High Voltage

Output Low Voltage

SYMBOL

CONDITIONS

MIN

12

TYP

MAX UNITS

1

R_DSP1B

V_O= V_DD*(0.5)

I_OH= -1 mA

15

55

Ω

V

1

R_DSN1B

12

V_OH1

V_OL1

2.4

I_OL= 1 mA

0.55

-33

V_{OH @ MIN}= 1.0 V

V_{OH @ MAX}= 3.135 V

V_{OL @ MIN}= 1.95 V

-33

30

-106

-14

94

I_OH1

Output High Current

mA

I_OL1

t_r1

Output Low Current

V

_{OL @ MAX}= 0.4 V

29

38

2

Rise Time¹

Fall Time¹

V_OL= 0.4 V, V_OH= 2.4 V

V_OH= 2.4 V, V_OL= 0.4 V

V_T= 1.5 V

0.4

45

1.3

1.4

51

ns

%

ps

t_f1

2

Duty Cycle¹

d_t1

55

500

Skew window¹

t_sk1

V_T= 1.5 V

250

150

Jitter, Cycle-to-cycle¹

t_jcyc-cyc1

V_T= 1.5 V

¹Guaranteed by design, not 100% tested in production.

Electrical Characteristics - REF, 48MHz_0 (Pin 25)

T_A= 0 - 70C; V_DD= 3.3 V +/-5%; C_L= 10-20 pF (unless otherwise specified)

PARAMETER

Output Impedance

Output High Voltage

Output Low Voltage

SYMBOL

CONDITIONS

MIN

20

TYP

29

MAX UNITS

1

R_DSP5B

V_O= V_DD*(0.5)

I_OH= -1 mA

60

Ω

V

1

R_DSN5B

20

27

V_OH15

V_OL5

2.4

I_OL= 1 mA

0.55

-23

V_{OH @ MIN}= 1.0 V

V_{OH @ MAX}= 3.135 V

V_{OL @ MIN}= 1.95 V

V_{OL @ MAX}= 0.4 V

-29

29

-54

-11

54

Output High Current

I^OH5

mA

Output Low Current

I^OL5

t^r5

16

27

4

Rise Time¹

Fall Time¹

Duty Cycle¹

V^OL= 0.4 V, V^OH= 2.4 V

V^OH= 2.4 V, V^OL= 0.4 V

V^T= 1.5 V

0.4

45

1.1

1.6

53

ns

%

t^f5

4

d^t5

55

Jitter, Cycle-to-cycle¹

t^jcyc-cyc5

V^T= 1.5 V, Fixed clocks

V^T= 1.5 V, Ref clocks

130

650

500

1000

ps

¹Guaranteed by design, not 100% tested in production.

11

ICS9250-26

Electrical Characteristics - 48MHz_1 (Pin 26)

T_A= 0 - 70C; V_DD= 3.3 V +/-5%; C_L= 20-30 pF (unless otherwise specified)

PARAMETER

Output Impedance

Output High Voltage

Output Low Voltage

SYMBOL

CONDITIONS

MIN

10

TYP

15

MAX UNITS

1

R_DSP3B

V_O= V_DD*(0.5)

I_OH= -1 mA

24

Ω

V

1

R_DSN3B

10

15

V_OH3

V_OL3

2.4

I_OL= 1 mA

0.55

-46

V_{OH @ MIN}= 2.0 V

_{OH @ MAX}= 3.135 V

-54

54

-82

-20

95

I_OH3

Output High Current

mA

V

V_{OL @ MIN}= 1.0 V

V_{OL @ MAX}= 0.4 V

I_OL3

t_r3

Output Low Current

28

53

1.6

55

Rise Time¹

Fall Time¹

Duty Cycle¹

Jitter, Cycle-to-cycle¹

V_OL= 0.4 V, V_OH= 2.4 V

V_OH= 2.4 V, V_OL= 0.4 V

V_T= 1.5 V

0.4

45

1.1

1.3

53

ns

%

ps

t_f3

d_t3

t_jcyc-cyc3BV_T= 1.5 V

130

250

¹Guaranteed by design, not 100% tested in production.

Group Skews (CPU = 66 MHz)

T_A= 0 - 70º C; V_DD= 3.3 V +/-5%, V_DDL= 2.5 V +/-5%

CPU & IOAPIC load (lumped) = 20 pF; PCI, SDRAM, 3V66 load (lumped) = 30 pF

Refer to Group Offset Waveform diagram for definition of transition edges.

PARAMETER

SYMBOL

T_{sk1 CPU-SDRAM}

T_{w1 CPU-SDRAM}

T_{sk1 CPU-3V66}

T_{w1 CPU-3V66}

CONDITIONS

MIN

-3

0

TYP

-2.6

150

7.2

MAX UNITS

CPU to SDRAM

Skew¹

-2

500

8

ns

ps

ns

ps

ns

ps

ns

CPU @ 1.25 V, SDRAM @ 1.5 V

Skew Window¹

Skew¹

7

CPU to 3V66

CPU @ 1.25 V, 3V66 @ 1.5 V

SDRAM, 3V66 @ 1.5 V

Skew Window¹

Skew¹

0

130

100

155

2.4

500

3.5

500

1

T_{sk1 SDRAM-3V66}

T_{w1 SDRAM-3V66}

T_{sk1 3V66-PCI}

-500

0

SDRAM to 3V66

3V66 to PCI

Skew Window¹

Skew¹

1.5

0

3V66, PCI @ 1.5 V

Skew Window¹

Skew¹

T_{w1 3V66-PCI}

275

-0.4

0.25

T_{sk1 IOAPIC-PCI}

-1

0

IOAPIC to PCI

IOAPIC @ 1.25 V, PCI @ 1.5 V

Skew Window¹

T_{w1 IOAPIC-PCI}

1

¹Guaranteed by design, not 100% tested in production.

12

ICS9250-26

Group Skews (CPU = 100 MHz)

T_A= 0 - 70º C; V_DD= 3.3 V +/-5%, V_DDL= 2.5 V +/-5%

CPU & IOAPIC load (lumped) = 20 pF; PCI, SDRAM, 3V66 load (lumped) = 30 pF

Refer to Group Offset Waveform diagram for definition of transition edges.

PARAMETER

SYMBOL

T_{sk2 CPU-SDRAM}

T_{w2 CPU-SDRAM}

T_{sk2 CPU-3V66}

T_{w2 CPU-3V66}

CONDITIONS

MIN

4.5

0

TYP

MAX UNITS

CPU to SDRAM

Skew¹

4.9

140

4.8

5.5

500

5.5

500

3.5

500

1

ns

ps

ns

ps

ns

ps

ns

CPU @ 1.25 V, SDRAM @ 1.5 V

Skew Window¹

Skew¹

4.5

0

CPU to 3V66

CPU @ 1.25 V, 3V66 @ 1.5 V

SDRAM, 3V66 @ 1.5 V

Skew Window¹

Skew¹

150

100

155

2.4

T_{sk2 SDRAM-3V66}

T_{w2 SDRAM-3V66}

T_{sk2 3V66-PCI}

-500

0

SDRAM to 3V66

3V66 to PCI

Skew Window¹

Skew¹

1.5

0

3V66, PCI @ 1.5 V

Skew Window¹

Skew¹

T_{w2 3V66-PCI}

275

-0.4

0.25

T_{sk2 IOAPIC-PCI}

-1

IOAPIC to PCI

IOAPIC @ 1.25 V, PCI @ 1.5 V

Skew Window¹

T_{w2 IOAPIC-PCI}

0

1

¹Guaranteed by design, not 100% tested in production.

Group Skews (CPU = 133 MHz)

T_A= 0 - 70º C; V_DD= 3.3 V +/-5%, V_DDL= 2.5 V +/-5%

CPU & IOAPIC load (lumped) = 20 pF; PCI, SDRAM, 3V66 load (lumped) = 30 pF

Refer to Group Offset Waveform diagram for definition of transition edges.

PARAMETER

SYMBOL

T_{sk3 CPU-SDRAM}

T_{w3 CPU-SDRAM}

T_{sk3 CPU-3V66}

T_{w3 CPU-3V66}

CONDITIONS

MIN

-500

0

TYP

70

MAX UNITS

CPU to SDRAM

Skew¹

500

3.5

500

1

ps

ns

ps

ns

CPU @ 1.25 V, SDRAM @ 1.5 V

Skew Window¹

Skew¹

125

-145

220

100

155

2.4

-500

0

CPU to 3V66

CPU @ 1.25 V, 3V66 @ 1.5 V

SDRAM, 3V66 @ 1.5 V

Skew Window¹

Skew¹

T_{sk3 SDRAM-3V66}

T_{w3 SDRAM-3V66}

T_{sk3 3V66-PCI}

-500

0

SDRAM to 3V66

3V66 to PCI

Skew Window¹

Skew¹

1.5

0

3V66, PCI @ 1.5 V

Skew Window¹

Skew¹

T_{w3 3V66-PCI}

275

-0.4

0.25

T_{sk3 IOAPIC-PCI}

-1

IOAPIC to PCI

IOAPIC @ 1.25 V, PCI @ 1.5 V

Skew Window¹

T_{w3 IOAPIC-PCI}

0

1

¹Guaranteed by design, not 100% tested in production.

13

ICS9250-26

Power Down Waveform

Note

1. After PD# is sampled active (Low) for 2 consective rising edges of CPUCLKs, all

the output clocks are driven Low on their next High to Low tranistiion.

2. Power-up latency <3ms.

3. Waveform shown for 100MHz

Group Offset Waveforms

14

ICS9250-26

SYMBOL

In Millimeters

In Inches

COMMON DIMENSIONS

MIN

MAX

2.794

0.406

0.343

0.254

MIN

.095

.008

.005

MAX

.110

.016

.0135

.010

A

A1

b

2.413

0.203

0.127

c

SEE VARIATIONS

D

E

10.033

7.391

10.668

7.595

.395

.291

.420

.299

E1

e

0.635 BASIC

0.025 BASIC

h

0.381

0.508

0.635

1.016

.015

.020

.025

.040

L

SEE VARIATIONS

N

α

0°

8°

0°

8°

VARIATIONS

D mm.

D (inch)

N

MIN

MAX

MIN

.720

MAX

.730

56

18.288

18.542

JEDEC MO-118

6/1/00

DOC# 10-0034

REV B

Ordering Information

ICS9250yF-26-T

Example:

ICS XXXX y F - PPP - T

Designation for tape and reel packaging

Pattern Number (2 or 3 digit number for parts with ROM code patterns)

Package Type

F=SSOP

Revision Designator (will not correlate with datasheet revision)

Device Type (consists of 3 or 4 digit numbers)

Prefix

ICS, AV = Standard Device

ICS reserves the right to make changes in the device data identified in

this publication without further notice. ICS advises its customers to

obtain the latest version of all device data to verify that any

15

information being relied upon by the customer is current and accurate.


型号：	ICS9250-26
厂家：	INTEGRATED CIRCUIT SOLUTION INC
描述：	Frequency Generator & Integrated Buffers for Celeron & PII/III⑩ 频率发生器和缓冲器集成的赛扬和PII / III⑩
文件：	总15页 (文件大小：224K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ICS9250-26 [ICSI]

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