ICS9250YF-28-T [ICSI]
Frequency Generator & Integrated Buffers for Celeron & PII/III⑩; 频率发生器和缓冲器集成的赛扬和PII / III⑩
| 型号： | ICS9250YF-28-T |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Frequency Generator & Integrated Buffers for Celeron & PII/III⑩ |
| 文件： | 总17页 (文件大小：198K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated
Circuit
Systems, Inc.
ICS9250-28
Frequency Generator & Integrated Buffers for Celeron & PII/III™
Recommended Application:
Pin Configuration
810/810E and 815 type chipset.
IOAPIC
VDDL
GND
1
2
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
VDDL
GND
Output Features:
2 CPU (2.5V) (up to 133MHz achievable through I2C)
3
4
5
6
7
8
9
CPUCLK0
CPUCLK1
GND
SDRAM0
SDRAM1
VDDSDR
GND
SDRAM2
SDRAM3
SDRAM4
VDDSDR
GND
SDRAM5
SDRAM6
VDDSDR
GND
SDRAM7
SDRAM8
SDRAM9
VDDSDR
GND
SDRAM10
SDRAM11
VDDSDR
GND
•
•
*FS1/REF0
VDDREF
X1
13 SDRAM (3.3V) (up to 133MHz achievable
through I2C)
X2
GND
•
•
•
•
•
2 PCI (3.3 V) @33.3MHz
VDD3V66
3V66_0
3V66_1
3V66_2
GND
VDDPCI
PCICLK0
PCICLK1
GND
1 IOAPIC (2.5V) @ 33.3 MHz
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
3 Hublink clocks (3.3 V) @ 66.6 MHz
2 (3.3V) @ 48 MHz (Non spread spectrum)
1 REF (3.3V) @ 14.318 MHz
Features:
•
Supports spread spectrum modulation,
0 to -0.5% down spread.
FS0
GND
VDDA
PD#
•
•
•
•
I2C support for power management
Efficient power management scheme through PD#
Uses external 14.138 MHz crystal
Alternate frequency selections available through I2C
control.
SCLK
SDATA
GND
VDD48
48MHz_0
48MHz_1
FS2
SDRAM12
56-Pin 300mil SSOP
* This input has a 50KW pull-down to GND.
Functionality
Block Diagram
FS2
FS0
FS1
Function
0
0
0
1
X
X
Tristate
Test
X1
X2
XTAL
OSC
REF0
Active CPU = 66MHz
SDRAM = 100MHz
1
1
1
1
0
1
0
1
0
0
1
1
PLL1
Spread
Spectrum
Active CPU = 100MHz
SDRAM = 100MHz
/2
/3
Active CPU = 133MHz
SDRAM = 133MHz
CPU66/100/133 [1:0]
2
3V66 (2:0)
FS(2:0)
PD#
3
Control
Logic
Active CPU = 133MHz
SDRAM = 100MHz
SDRAM (12:0)
13
Config
Reg
PCICLK (1:0)
IOAPIC
/2
2
SDATA
SCLK
Power Groups
/2
Analog
Digital
VDD3V66, VDDPCI
VDDSDR, VDDL
VDDREF = X1, X2
VDDA = PLL1
VDD48 = PLL2
48MHz (1:0)
PLL2
2
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
9250-28 Rev B 10/26/00
Third party brands and names are the property of their respective owners.
information being relied upon by the customer is current and accurate.
ICS9250-28
General Description
The ICS9250-28 is part of a two chip clock solution for 810/810E and 815 type chipset. Combined with the
ICS9112-17, the ICS9250-28 provides all necessary clock signals for such a system.
Spread spectrum may be enabled through I2C programming. Spread spectrum typically reduces EMI by 8dB to 10
dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The
ICS9250-28 employs a proprietary closed loop design, which tightly controls the percentage of spreading over
process and temperature variations.
Pin Configuration
PIN NUMBER PIN NAME
TYPE
DESCRIPTION
1
IOAPIC
VDDL
FS1
OUT 2.5V clock output running at 33.3MHz.
PWR 2.5V power supply for CPU & IOAPIC
2, 56
IN
Function Select pin. Determines CPU frequency, all output functionality
4
REF0
OUT 3.3V, 14.318MHz reference clock output.
PWR 3.3V power supply
5, 9, 14, 20, 25,
31, 35, 40, 44, 49
VDD
X1
Crystal input, has internal load cap (33pF) and feedback
resistor from X2
6
IN
Crystal output, nominally 14.318MHz. Has internal load
cap (33pF)
7
X2
OUT
3, 8, 13, 17, 19,
24, 30, 34, 39, GND
43, 48, 52, 55
PWR Ground pins for 3.3V supply
12, 11, 10
28, 18
3V66 (2:0)
OUT 3.3V Fixed 66MHz clock outputs for HUB
Function Select pins. Determines CPU frequency, all output functionality.
FS (2, 0)
IN
Please refer to Functionality table on page 3.
16, 15
PCICLK[1:0]
OUT 3.3V PCI clock outputs
Asynchronous active low input pin used to power down the device into
a low power state. The internal clocks are disabled and the VCO and
21
PD#
IN
the crystal are stopped. The latency of the power down will not be
greater than 3ms.
22
23
SCLK
IN
Clock pin of I2C circuitry 5V tolerant
SDATA
48MHz_0
I/O
Data pin for I2C circuitry 5V tolerant
26, 27
OUT 3.3V Fixed 48MHz clock outputs.
29, 32, 33, 36,
37, 38, 41, 42,
45, 46, 47, 50, 51
SDRAM
(12:0)
3.3V output running 100MHz. All SDRAM outputs can be turned off
OUT
through I2C
2.5V Host bus clock output. 66MHz, 100MHz or 133MHz depending
on FS (2:0) pins.
54, 53
CPUCLK (1:0)
OUT
2
ICS9250-28
Power Down Waveform
Note
1. After PD# is sampled active (Low) for 2 consective rising edges of CPUCLKs, all
the output clocks are driven Low on their next High to Low tranistiion.
2. Power-up latency <3ms.
3. Waveform shown for 100MHz
Maximum Allowed Current
Max 2.5V supply consumption
Max discrete cap loads,
Vddq2 = 2.625V
Max 2.5V supply consumption
Max discrete cap loads,
Vddq2 = 3.465V
815
Condition
All static inputs = Vddq3 or GND All static inputs = Vddq3 or GND
Powerdown Mode
10mA
70mA
10mA
400mA
400mA
450mA
(PWRDWN# = 0
Full Active 66MHz
FS[2:0] = 010
Full Active 100MHz
FS[2:0] = 011
100mA
130mA
Full Active 133MHz
FS[2:0] = 111
Clock Enable Configuration
REF,
48MHz
PD# CPUCLK SDRAM IOAPIC 66MHz PCICLK
Osc VCOs
0
1
LOW
ON
LOW
ON
LOW
ON
LOW
ON
LOW
ON
LOW
ON
OFF
ON
OFF
ON
3
ICS9250-28
Truth Table
FS2 FS0 FS1
CPU
SDRAM
Tristate
3V66
Tristate
TCLK/3
PCI
48MHz
Tristate
TCLK/2
48 MHz
48 MHz
48 MHz
48 MHz
REF
IOAPIC
Tristate
TCLK/6
0
0
1
1
1
1
0
1
0
1
0
1
X
X
0
Tristate
Tristate
TCLK/6
Tristate
TCLK
TCLK/2
66.6 MHz
100 MHz
133 MHz
133 MHz
TCLK/2
100 MHz
100 MHz
133 MHz
100 MHz
66.6 MHz 33.3 MHz
66.6 MHz 33.3 MHz
66.6 MHz 33.3 MHz
66.6 MHz 33.3 MHz
14.318 MHz 33.3 MHz
14.318 MHz 33.3 MHz
14.318 MHz 33.3 MHz
14.318 MHz 33.3 MHz
0
1
1
Byte 3: ICS Reserved Functionality and frequency select register (Default as noted in PWD)
Bit
Desctiption
PWD
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
ICS Reserved bit (Note 2)
ICS Reserved bit (Note 2)
ICS Reserved bit (Note 2)
ICS Reserved bit (Note 2)
ICS Reserved bit (Note 2)
Undefined bit (Note 3)
0
0
0
0
0
X
X
Undefined bit (Note 3)
CPUCLK SDRAM 3V66 PCICLK IOAPIC
Bit 0
FS0
FS1
MHz
MHz
100.0
100.0
133.32
100.0
100.0
100.0
133.32
133.32
MHz
66.66
66.66
66.66
66.66
66.66
66.66
66.66
66.66
MHz
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
MHz
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
0
0
0
0
1
1
1
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
66.66
100.0
133.32
133.32
66.66
0
Bit 0
Note 1
100.0
133.32
133.32
Note 1: For system operation, the BSEL lines of the CPU will program FS0, FS2 for the appropriate CPU speed, always
with SDRAM = 100MHz. After BIOS verifies the SDRAM is PC133 speed, then bit 0 can be written from the
default 0 to 1 to change the SDRAM output frequency from 100MHz to 133MHz. This will only change if the
CPU is at the 133MHz FSB speed as shown in this table. The CPU, 3V66, PCI, and IOAPIC clocks will be glitch
free during this transition, and only SDRAM will change.
Note 2: "ICS RESERVED BITS" must be writtern as "0".
Note3: Undefined bits can be written either as "1 or 0"
4
ICS9250-28
Byte 0: Control Register
(1 = enable, 0 = disable)
Bit
Pin#
Name
Reserved ID
Reserved ID
Reserved ID
Reserved ID
PWD
Description
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
Bit 7
Bit 6
Bit 5
Bit 4
-
-
-
-
0
0
0
1
SpreadSpectrum
(1=On/0=Off)
Bit 3
-
1
(Active/Inactive)
Bit 2
Bit 1
Bit 0
27
26
-
48MHz 1
48MHz 0
Reserved ID
1
1
0
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
Note: Reserved ID bits must be written as "0"
Byte 1: Control Register
(1 = enable, 0 = disable)
Bit
Pin#
38
41
42
45
46
47
50
51
Name
SDRAM7
PWD
Description
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
1
1
1
1
SDRAM6
SDRAM5
SDRAM4
SDRAM3
SDRAM2
SDRAM1
SDRAM0
Byte 2: Control Register
(1 = enable, 0 = disable)
Bit
Pin#
12
29
32
33
36
37
16
-
Name
3V66-2 (AGP)
SDRAM12
SDRAM11
SDRAM10
SDRAM9
SDRAM8
PCICLK1
Reserved
PWD
Description
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
1
1
1
0
Notes:
1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be
configured at power-on and are not expected to be configured during the normal modes of operation.
2. PWD = Power on Default
3. Undefined bit can be wirtten with either a "1" or "0".
5
ICS9250-28
Byte 4: Reserved Register
(1 = enable, 0 = disable)
Bit
Pin#
Name
Reserved
PWD
Description
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
0
0
0
0
0
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Notes:
1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be
configured at power-on and are not expected to be configured during the normal modes of operation.
2. PWD = Power on Default
Group Timing Relationship Table1
Group
CPU 66MHz
SDRAM 100MHz
CPU 100MHz
SDRAM 100MHz
CPU 133MHz
SDRAM 100MHz
CPU 133MHz
SDRAM 133MHz
Offset
-2.5ns
7.5ns
0.0ns
Tolerance
500ps
Offset
5.0ns
5.0ns
0.0ns
Tolerance
500ps
Offset
0.0ns
0.0ns
0.0ns
Tolerance
500ps
Offset
3.75ns
0.0ns
Tolerance
500ps
CPU to SDRAM
CPU to 3V66
500ps
500ps
500ps
500ps
SDRAM to 3V66
500ps
500ps
500ps
-3.75ns
500ps
3V66 to PCI
PCI to PCI
1.5-3.5ns
0.0ns
500ps
500ps
N/A
1.5-3.5ns
0.0ns
500ps
500ps
N/A
1.5-3.5ns
500ps
500ps
1.0ns
N/A
1.5 -3.5ns
0.0ns
500ps
500ps
N/A
USB & DOT
Asynch
Asynch
Asynch
Asynch
6
ICS9250-28
Absolute Maximum Ratings
Core Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . 4.6 V
I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . 3.6V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . . 0°C to +70°C
Maximum Case Operating Temperature . . . . . . +135°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
SYMBOL
VIH
CONDITIONS
MIN
2
TYP
MAX UNITS
VDD+0.3
V
V
VIL
VSS-0.3
-5
0.8
5
IIH
VIN = VDD
µA
IIL1
IIL2
VIN = 0 V; Inputs with no pull-up resistors
VIN = 0 V; Inputs with pull-up resistors
-5
Input Low Current
µA
-200
CL = 0 pF; @ 66/100 MHz
138
126
172
141
339
328
383
200
200
200
200
400
400
450
CL = 0 pF; @ 100/100 MHz
CL = 0 pF; @ 133/133 MHz
CL = 0 pF; @ 133/100 MHz
CL = Max loads; @ 66/100 MHz
CL = Max loads; @ 100/100 MHz
CL = Max loads; @ 133/133 MHz
mA
IDD3.3OP
mA
mA
CL = Max loads; @ 133/100 MHz
CL = 0 pF; @ 66/100 MHz
340
9
400
15
18
20
20
35
60
Operating Supply
Current
CL = 0 pF; @ 100/100 MHz
CL = 0 pF; @ 133/133 MHz
CL = 0 pF; @ 133/100 MHz
CL = Max loads; @ 66/100 MHz
CL = Max loads; @ 100/100 MHz
11
13
13
13
23
IDD2.5OP
mA
CL = Max loads; @ 133/133 MHz
29
60
CL = Max loads; @ 133/100 MHz
CL = Max loads
30
251
60
400
10
IDD3.3PD
IDD.25PD
Fi
Powerdown Current
µA
<1
Input address VDD or GND
VDD = 3.3 V
Input Frequency
Transition time1
Settling time1
12
14.318
16
MHz
ms
Ttrans
Ts
To 1st crossing of target frequency
3
3
From 1st crossing to 1% target frequency
ms
Clk Stabilization1
TSTAB From VDD = 3.3 V to 1% target frequency
tPZH,tPZL Output enable delay (all outputs)
3
ms
ns
1
1
10
10
Delay1
tPHZ,tPLZ
Output disable delay (all outputs)
ns
1Guaranteed by design, not 100% tested in production.
7
ICS9250-28
Electrical Characteristics - CPU
TA = 0 - 70C; VDDL = 2.5 V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
SYMBOL
CONDITIONS
MIN
13.5
13.5
2
TYP
16
MAX UNITS
1
RDSP2B
VO = VDD*(0.5)
VO = VDD*(0.5)
IOH = -1 mA
45
45
Ω
Ω
V
V
1
RDSN2B
21
VOH2B
VOL2B
IOL = 1 mA
0.4
-27
VOH @ MIN = 1.0 V
VOH @ MAX = 2.375 V
VOL @ MIN = 1.2 V
-27
27
-68
-9
IOH2B
Output High Current
mA
mA
54
11
IOL2B
tr2B
Output Low Current
V
OL @ MAX = 0.3 V
30
1.6
1.6
55
Rise Time1
Fall Time1
VOL = 0.4 V, VOH = 2.0 V
VOH = 2.0 V, VOL = 0.4 V
VT = 1.25 V
0.4
0.4
45
1.1
1.1
49
ns
ns
%
ps
ps
tf2B
Duty Cycle1
dt2B
Skew window1
tsk2B
VT = 1.25 V
45
175
250
Jitter, Cycle-to-cycle1
tjcyc-cyc2B VT = 1.25 V
135
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - 3V66
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
SYMBOL
CONDITIONS
MIN
12
TYP
14
MAX UNITS
1
RDSP1B
VO = VDD*(0.5)
VO = VDD*(0.5)
IOH = -1 mA
55
55
Ω
Ω
V
V
1
RDSN1B
12
14.5
VOH1
VOL1
2.4
IOL = 1 mA
0.55
-33
VOH @ MIN = 1.0 V
VOH @ MAX = 3.135 V
VOL @ MIN = 1.95 V
-33
30
-108
-9
IOH1
Output High Current
mA
mA
95
IOL1
tr1
Output Low Current
V
OL @ MAX = 0.4 V
29
38
1.6
1.6
55
Rise Time1
Fall Time1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
0.4
0.4
45
1.2
1.2
49
ns
ns
%
ps
ps
tf1
Duty Cycle1
dt1
Skew window1
tsk1
VT = 1.5 V
135
175
175
500
Jitter, Cycle-to-cycle1
tjcyc-cyc1
VT = 1.5 V
1Guaranteed by design, not 100% tested in production.
8
ICS9250-28
Electrical Characteristics - IOAPIC
TA = 0 - 70C; VDDL = 2.5 V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
1
RDSP4B
VO = VDD*(0.5)
VO = VDD*(0.5)
IOH = -1 mA
9
9
2
16
20
30
30
Ω
Ω
V
V
1
RDSN4B
VOH4B
VOL4B
IOL = 1 mA
0.4
-27
VOH @ MIN = 1.0 V
OH @ MAX = 2.375 V
-27
27
-68
-9
IOH4B
Output High Current
mA
mA
V
VOL @ MIN = 1.2 V
VOL @ MAX = 0.3 V
54
11
IOL4B
tr4B
Output Low Current
30
1.6
1.6
55
Rise Time1
Fall Time1
Duty Cycle1
Jitter, Cycle-to-cycle1
VOL = 0.4 V, VOH = 2.0 V
VOH = 2.0 V, VOL = 0.4 V
VT = 1.25 V
0.4
0.4
45
1.1
1.1
49
ns
ns
%
ps
tf4B
dt4B
tjcyc-cyc4B VT = 1.25 V
180
500
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - SDRAM
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 20-30 pF (unless otherwise specified)
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
SYMBOL
CONDITIONS
MIN
10
TYP
12
MAX UNITS
1
RDSP3B
VO = VDD*(0.5)
VO = VDD*(0.5)
IOH = -1 mA
24
24
Ω
Ω
V
V
1
RDSN3B
10
15
VOH3
VOL3
2.4
IOL = 1 mA
0.4
-46
VOH @ MIN = 2.0 V
VOH @ MAX = 3.135 V
VOL @ MIN = 1.0 V
-54
54
-92
-16
68
IOH3
Output High Current
mA
mA
IOL3
tr3
Output Low Current
V
OL @ MAX = 0.4 V
29
53
1.6
1.6
55
Rise Time1
Fall Time1
Duty Cycle1
Skew window1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
0.4
0.4
45
1
ns
ns
%
ps
ps
tf3
1.5
52
dt3
tsk3
VT = 1.5 V
120
135
250
250
Jitter, Cycle-to-cycle1
tjcyc-cyc3
VT = 1.5 V
1Guaranteed by design, not 100% tested in production.
9
ICS9250-28
Electrical Characteristics - PCI
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise specified)
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
SYMBOL
CONDITIONS
MIN
12
TYP
15
MAX UNITS
1
RDSP1B
VO = VDD*(0.5)
VO = VDD*(0.5)
IOH = -1 mA
55
55
Ω
Ω
V
V
1
RDSN1B
12
15
VOH1
VOL1
2.4
IOL = 1 mA
0.55
-33
VOH @ MIN = 1.0 V
VOH @ MAX = 3.135 V
VOL @ MIN = 1.95 V
-33
30
-106
-14
94
IOH1
Output High Current
mA
mA
IOL1
tr1
Output Low Current
V
OL @ MAX = 0.4 V
29
38
2
Rise Time1
Fall Time1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
0.4
0.4
45
1.3
1.4
51
ns
ns
%
ps
ps
tf1
2
Duty Cycle1
dt1
55
500
500
Skew window1
tsk1
VT = 1.5 V
20
Jitter, Cycle-to-cycle1
tjcyc-cyc1
VT = 1.5 V
175
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - REF, 48MHz_0 (Pin 26)
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
SYMBOL
CONDITIONS
MIN
20
TYP
29
MAX UNITS
1
RDSP5B
VO = VDD*(0.5)
VO = VDD*(0.5)
IOH = -1 mA
60
60
Ω
Ω
V
V
1
RDSN5B
20
27
VOH15
VOL5
2.4
IOL = 1 mA
0.55
-23
V
V
V
V
OH @ MIN = 1.0 V
-29
29
-54
-11
54
IOH5
Output High Current
mA
mA
OH @ MAX = 3.135 V
OL @ MIN = 1.95 V
OL @ MAX = 0.4 V
IOL5
tr5
Output Low Current
16
27
4
Rise Time1
Fall Time1
Duty Cycle1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
0.4
0.4
45
1.3
1.6
53
ns
ns
%
ps
ps
tf5
4
dt5
55
Jitter, Cycle-to-cycle1
Jitter, Cycle-to-cycle1
tjcyc-cyc5
tjcyc-cyc5
VT = 1.5 V, Fixed clocks
VT = 1.5 V, Ref clocks
160
420
500
1000
1Guaranteed by design, not 100% tested in production.
10
ICS9250-28
Electrical Characteristics - 48MHz_1 (Pin 27)
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-15 pF (unless otherwise specified)
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
SYMBOL
CONDITIONS
MIN
10
TYP
MAX UNITS
1
RDSP3B
VO = VDD*(0.5)
VO = VDD*(0.5)
IOH = -1 mA
15
15
24
24
Ω
Ω
V
V
1
RDSN3B
10
VOH3
VOL3
2.4
IOL = 1 mA
0.55
-46
VOH @ MIN = 2.0 V
OH @ MAX = 3.135 V
-54
54
-82
-20
95
IOH3
Output High Current
mA
mA
V
VOL @ MIN = 1.0 V
VOL @ MAX = 0.4 V
IOL3
tr3
Output Low Current
28
53
1.6
1.6
55
Rise Time1
Fall Time1
Duty Cycle1
Jitter, Cycle-to-cycle1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
0.4
0.4
45
1.1
1.3
53
ns
ns
%
ps
tf3
dt3
tjcyc-cyc3B VT = 1.5 V
145
500
1Guaranteed by design, not 100% tested in production.
11
ICS9250-28
Group Skews (CPU 66 MHz, SDRAM 100MHz)
TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%
CPU & IOAPIC load (lumped) = 20 pF; PCI, SDRAM, 3V66 load (lumped) = 30 pF
Refer to Group Offset Waveforms diagram for definition of transition edges.
PARAMETER
SYMBOL
Tsk1 CPU-SDRAM
Tw1 CPU-SDRAM
Tsk1 CPU-3V66
Tw1 CPU-3V66
CONDITIONS
MIN
-3
0
TYP
-2.7
165
7.6
105
180
210
2.1
90
MAX UNITS
CPU to SDRAM
Skew1
-2
500
8
ns
ps
ns
ps
ps
ps
ns
ps
ns
ns
CPU @ 1.25 V, SDRAM @ 1.5 V
Skew Window1
Skew1
7
CPU to 3V66
CPU @ 1.25 V, 3V66 @ 1.5 V
SDRAM, 3V66 @ 1.5 V
Skew Window1
Skew1
0
500
500
500
3.5
500
1
Tsk1 SDRAM-3V66
Tw1 SDRAM-3V66
Tsk1 3V66-PCI
-500
0
SDRAM to 3V66
3V66 to PCI
Skew Window1
Skew1
1.5
0
3V66, PCI @ 1.5 V
Skew Window1
Skew1
Tw1 3V66-PCI
Tsk1 IOAPIC-PCI
-1
0
-0.1
0
IOAPIC to PCI
IOAPIC @ 1.25 V, PCI @ 1.5 V
Skew Window1
Tw1 IOAPIC-PCI
1
1Guaranteed by design, not 100% tested in production.
Group Skews (CPU 100 MHz, SDRAM 100MHz)
TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%
CPU & IOAPIC load (lumped) = 20 pF; PCI, SDRAM, 3V66 load (lumped) = 30 pF
Refer to Group Offset Waveforms diagram for definition of transition edges.
PARAMETER
SYMBOL
Tsk2 CPU-SDRAM
Tw2 CPU-SDRAM
Tsk2 CPU-3V66
Tw2 CPU-3V66
CONDITIONS
MIN
4.5
0
TYP
4.9
180
5
MAX UNITS
CPU to SDRAM
Skew1
5.5
500
5.5
500
500
500
3.5
500
1
ns
ps
ns
ps
ps
ps
ns
ps
ns
ns
CPU @ 1.25 V, SDRAM @ 1.5 V
Skew Window1
Skew1
4.5
0
CPU to 3V66
CPU @ 1.25 V, 3V66 @ 1.5 V
SDRAM, 3V66 @ 1.5 V
Skew Window1
Skew1
100
175
200
2.1
90
Tsk2 SDRAM-3V66
Tw2 SDRAM-3V66
Tsk2 3V66-PCI
-500
0
SDRAM to 3V66
3V66 to PCI
Skew Window1
Skew1
1.5
0
3V66, PCI @ 1.5 V
Skew Window1
Skew1
Tw2 3V66-PCI
Tsk2 IOAPIC-PCI
-1
-0.1
0
IOAPIC to PCI
IOAPIC @ 1.25 V, PCI @ 1.5 V
Skew Window1
Tw2 IOAPIC-PCI
0
1
1Guaranteed by design, not 100% tested in production.
12
ICS9250-28
Group Skews (CPU 133 MHz, SDRAM 133MHz)
TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%
CPU & IOAPIC load (lumped) = 20 pF; PCI, SDRAM, 3V66 load (lumped) = 30 pF
Refer to Group Offset Waveforms diagram for definition of transition edges.
PARAMETER
SYMBOL
Tsk3 CPU-SDRAM
Tw3 CPU-SDRAM
Tsk3 CPU-3V66
Tw3 CPU-3V66
CONDITIONS
MIN
3.25
0
TYP
MAX UNITS
CPU to SDRAM
Skew1
3.45
155
120
120
-3.08
175
2.2
4.25
500
500
500
-4.25
500
3.5
500
1
ns
ps
ps
ps
ps
ps
ns
ps
ns
ns
CPU @ 1.25 V, SDRAM @ 1.5 V
Skew Window1
Skew1
-500
0
CPU to 3V66
CPU @ 1.25 V, 3V66 @ 1.5 V
SDRAM, 3V66 @ 1.5 V
Skew Window1
Skew1
Tsk3 SDRAM-3V66
Tw3 SDRAM-3V66
Tsk3 3V66-PCI
-3.25
0
SDRAM to 3V66
3V66 to PCI
Skew Window1
Skew1
1.5
0
3V66, PCI @ 1.5 V
Skew Window1
Skew1
Tw3 3V66-PCI
80
Tsk3 IOAPIC-PCI
-1
-0.1
0
IOAPIC to PCI
IOAPIC @ 1.25 V, PCI @ 1.5 V
Skew Window1
Tw3 IOAPIC-PCI
0
1
1Guaranteed by design, not 100% tested in production.
Group Skews (CPU133 MHz, SDRAM 100MHz)
TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%
CPU & IOAPIC load (lumped) = 20 pF; PCI, SDRAM, 3V66 load (lumped) = 30 pF
Refer to Group Offset Waveforms diagram for definition of transition edges.
PARAMETER
SYMBOL
Tsk3 CPU-SDRAM
Tw3 CPU-SDRAM
Tsk3 CPU-3V66
Tw3 CPU-3V66
CONDITIONS
CPU @ 1.25 V, SDRAM @ 1.5 V -500
0
MIN
TYP
-15
165
165
105
185
185
2.2
60
MAX UNITS
CPU to SDRAM
Skew1
500
500
500
500
500
500
3.5
500
1
ps
ps
ps
ps
ps
ps
ns
ps
ns
ns
Skew Window1
Skew1
CPU @ 1.25 V, 3V66 @ 1.5 V
-500
0
CPU to 3V66
Skew Window1
Skew1
Tsk3 SDRAM-3V66
Tw3 SDRAM-3V66
Tsk3 3V66-PCI
SDRAM, 3V66 @ 1.5 V
-500
0
SDRAM to 3V66
3V66 to PCI
Skew Window1
Skew1
3V66, PCI @ 1.5 V
1.5
0
Skew Window1
Skew1
Tw3 3V66-PCI
Tsk3 IOAPIC-PCI
IOAPIC @ 1.25 V, PCI @ 1.5 V
-1
-0.1
0
IOAPIC to PCI
Skew Window1
Tw3 IOAPIC-PCI
0
1
1Guaranteed by design, not 100% tested in production.
13
ICS9250-28
0ns
10ns
20ns
30ns
40ns
Cycle Repeats
CPU 66MHz
CPU 100MHz
CPU 133MHz
SDRAM 100MHz
SDRAM 133MHz
3V66MHz
PCI 33MHz
APIC 33MHz
REF 14.318MHz
USB 48MHz
Group Offset Waveforms
14
ICS9250-28
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
For more information, contact ICS for an I2C programming application note.
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
How to Read:
Controller (host) will send start bit.
Controller (host) sends the read address D3 (H)
ICS clock will acknowledge
Controller (host) sends a dummy command code
ICS clock will acknowledge
ICS clock will send the byte count
Controller (host) acknowledges
Controller (host) sends a dummy byte count
ICS clock will acknowledge
Controller (host) starts sending first byte (Byte 0)
through byte 5
ICS clock sends first byte (Byte 0) through byte 5
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit
ICS clock will acknowledge each byte one at a time.
Controller (host) sends a Stop bit
How to Write:
Controller (Host)
ICS (Slave/Receiver)
How to Read:
Start Bit
Controller (Host)
ICS (Slave/Receiver)
Address
Start Bit
D2(H)
Address
D3(H)
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Dummy Command Code
ACK
Byte Count
Dummy Byte Count
Byte 0
ACK
ACK
ACK
ACK
ACK
ACK
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
ACK
Stop Bit
Stop Bit
Notes:
1.
The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for
verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.
2.
3.
4.
5.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.
6.
At power-on, all registers are set to a default condition, as shown.
15
ICS9250-28
General Layout Precautions:
1) Use a ground plane on the top routing
layer of the PCB in all areas not used
by traces.
Ferrite
Bead
Ferrite
Bead
C2
22µF/20V
Tantalum
C2
22µF/20V
Tantalum
VDD
VDD
2) Make all power traces and ground
traces as wide as the via pad for lower
inductance.
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
2.5V Power Route
2
3
Notes:
1
1 All clock outputs should have
provisions for a 15pf capacitor
between the clock output and series
terminating resistor. Not shown in
all places to improve readability of
diagram.
Clock Load
4
C3
5
2
C1
C1
6
7
8
2 Optional crystal load capacitors are
recommended. They should be
included in the layout but not
inserted unless needed.
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Component Values:
C1 : Crystal load values determined by user
C2 : 22µF/20V/D case/Tantalum
AVX TAJD226M020R
C3 : 15pF capacitor
Ground
FB = Fair-Rite products 2512066017X1
All unmarked capacitors are 0.01µF ceramic
3.3V Power Route
Connections to VDD:
16
ICS9250-28
SYMBOL
In Millimeters
In Inches
COMMON DIMENSIONS COMMON DIMENSIONS
MIN
MAX
2.794
0.406
0.343
0.254
MIN
.095
.008
.008
.005
MAX
.110
.016
.0135
.010
A
A1
b
2.413
0.203
0.203
0.127
c
SEEVARIATIONS
SEEVARIATIONS
D
E
10.033
7.391
10.668
7.595
.395
.291
.420
.299
E1
e
0.635 BASIC
0.025 BASIC
h
0.381
0.508
0.635
1.016
.015
.020
.025
.040
L
SEEVARIATIONS
SEEVARIATIONS
N
0°
8°
0°
8°
α
VARIATIONS
N
D mm.
D (inch)
MIN
MAX
MIN
MAX
9.652
28
34
48
56
64
9.398
11.303
15.748
18.288
20.828
.370
.445
.620
.720
.820
.380
.455
.630
.730
.830
11.557
16.002
18.542
21.082
Ordering Information
ICS9250yF-28-T
Example:
ICS XXXX y F - PPP - T
Designation for tape and reel packaging
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
17
information being relied upon by the customer is current and accurate.
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