ICS93725YFT [ICSI]
DDR and SDRAM Zero Delay Buffer; DDR和SDRAM零延迟缓冲器
| 型号： | ICS93725YFT |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | DDR and SDRAM Zero Delay Buffer |
| 文件： | 总8页 (文件大小：67K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS93725
Integrated
Circuit
Systems, Inc.
DDR and SDRAM Zero Delay Buffer
RecommendedApplication:
Pin Configuration
DDR & SDRAM Zero Delay Buffer for SIS 635/640/645/
650 & 735/740/746 style chipsets.
VDD3.3
SDRAM0
SDRAM1
SDRAM2
SDRAM3
GND
1
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
SEL_DDR*
DDRFB_IN
DDRFB_OUT
VDD2.5
DDRT5
DDRC5
DDRT4
DDRC4
GND
VDD2.5
DDRT3
DDRC3
DDRT2
DDRC2
GND
VDD2.5
DDRT1
DDRC1
DDRT0
DDRC0
GND
VDD2.5
SCLK
SDATA
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
ProductDescription/Features:
•
•
Low skew, Zero Delay Buffer
1 to 13 SDRAM PC133 clock distribution
VDD3.3
SDRAM4
SDRAM5
BUFFER_IN
SDRAM6
SDRAM7
GND
•
•
•
1 to 6 pairs of DDR clock distribution
I2C for functional and output control
Separate feedback path for both memory mode to
adjust synchronization.
VDD3.3
•
•
•
•
Supports up to 2 DDR DIMMs or 3 SDRAM DIMMs
Frequency support for up to 200MHz
Individual I2C clock stop for power mananagement
CMOS level control signal input
SDRAM8
SDRAM9
SDRAM10
SDRAM11
GND
VDD3.3
SDRAM12
SDFB_OUT
SDFB_IN
GND
SwitchingCharacteristics:
•
OUTPUT - OUTPUT skew: <100ps
•
Output Rise and Fall Time for DDR outputs: 550ps -
1150ps
48-Pin SSOP
•
DUTY CYCLE: 47% - 53%
*Internal Pull-up Resistor of 120K to VDD
Block Diagram
Functionality
VDD
3.3_2.5
MODE
PIN 48
SDRAMFB_OUT
DDRFB_OUT
BUFFER_IN
SDRAMFB_IN
DDRFB_IN
PLL1
DDR
Mode
SEL_DDR=1
SEL_DDR=0
2.5V
SDRAM (12:0)
DDR/SD
Mode
3.3V
Control
Logic
DDRT (5:0)
DDRCC (5:0)
SEL_DDR*
SDATA
3
3
SCLK
Config.
Reg.
0606A—08/01/03
ICS93725
Pin Descriptions
PIN NUMBER
PIN NAME
VDD3.3
TYPE
DESCRIPTION
1, 7, 14, 20
PWR 3.3V voltage supply for SDRAM.
PWR Ground
6, 13, 19, 24, 34,
28, 40
GND
44, 42, 38,
36, 32, 30
DDRT (5:0)
DDRC (5:0)
OUT
OUT
"True" Clock of differential pair outputs.
43, 41, 37,
35, 31, 29
"Complementory" clocks of differential pair outputs.
21, 18, 17, 16, 15,
12, 11, 9, 8, 5,
4, 3, 2
SDRAM (12:0)
OUT
SDRAM clock outputs
27, 39, 45
VDD2.5
PWR 2.5V voltage supply for DDR.
10
22
23
25
BUFFER_IN
SDRAMFB_OUT
SDFB_IN
IN
OUT
IN
Single ended buffer input
Feedback output for SDRAM
Feedback input for SDRAM
Data pin for I2C circuitry 5V tolerant
SDATA
I/O
26
SCLK
IN
Clock input of I2C input, 5V tolerant input
46
47
DDRFB_OUT
DDRFB_IN
OUT
IN
Feedback output for DDR
Feedback input for DDR
Select input for DDR mode or DDR/SD mode
0=SD mode 1=DDR mode
48
SEL_DDR
IN
0606A—08/01/03
2
ICS93725
Byte6:OutputControl
(1= enable, 0 = disable)
Byte7:OutputControl
(1= enable, 0 = disable)
BIT
Bit 7 30, 29
Bit 6 21
PIN# PWD
DESCRIPTION
BIT
Bit 7
Bit 6
Bit 5
PIN# PWD
DESCRIPTION
SEL_DDR (Read back only)
(Reserved)
48
-
-
1
1
DDRT0, DDRC0
1
1
1
1
1
1
1
SDRAM12
SDRAM10
SDRAM11
SDRAM8
SDRAM9
SDRAM6
SDRAM7
SDRAM4
SDRAM5
SDRAM2
SDRAM3
SDRAM1
SDRAM0
-
(Reserved)
Bit 5 17, 18
Bit 4 15, 16
Bit 3 11, 12
1
1
1
1
1
1
Bit 4 44, 43
Bit 3 42, 41
Bit 2 38, 37
Bit 1 36, 35
Bit 0 32, 31
DDRT5, DDRC5
DDRT4, DDRC4
DDRT3, DDRC3
DDRT2, DDRC2
DDRT1, DDRC1
Bit 2
Bit 1
Bit 0
8, 9
4, 5
2, 3
0606A—08/01/03
3
ICS93725
Absolute Maximum Ratings
Supply Voltage (VDD &VDD2.5) . . . . . . . . . -0.5V to 3.6V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient OperatingTemperature . . . . . . . . . . 0°C to +85°C
CaseTemperature . . . . . . . . . . . . . . . . . . . . . 115°C
StorageTemperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device.These
ratingsarestressspecificationsonlyandfunctionaloperationofthedeviceattheseoranyotherconditionsabovethose
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
SEL_DDR=0 SDRAM Outputs VDD=3.3V, TA=0 - 85°C; (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
130
173
MAX
-18
UNITS
mA
100MHz, RL=0Ω, CL = 0pF
133MHz, RL=0Ω, CL = 0pF
IDD3.3
Operating Supply Current
200MHz, RL=0Ω, CL = 0pF
VDD=3.3V, VOUT=1V
VDD=3.3V, VOUT=1.2V
VDD=3.3V
247
-40
34
mA
mA
mA
IOH
IOL
Output High Current
Output Low Current
26
VOH
High-level output voltage
1.7
2
V
IOH = -12 mA
VDD=3.3V
VOL
CIN
Low-level output voltage
Input Capacitance1
0.4
2
0.6
V
IOH = 12 mA
VI = GND or VDD
pF
1Guaranteed by design, not 100% tested in production.
Recommended Operating Condition
SEL_DDR=0 SDRAM Outputs VDD=3.3V, TA=0 - 85°C; (unless otherwise stated)
PARAMETER
Power Supply Voltage
Input High Voltage
Input Low Voltae
SYMBOL
VDD3.3
VIH
CONDITIONS
MIN
3
TYP
3.3
MAX
3.6
UNITS
V
V
V
V
SEL_DDR, PD# input
SEL_DDR, PD# input
2
VIL
0.8
3.6
VIN
Input Voltage Level
1Guaranteed by design, not 100% tested in production.
0
3.3
0606A—08/01/03
4
ICS93725
Electrical Characteristics - Input/Supply/Common Output Parameters
SEL_DDR=1 DDR Outputs VDD=2.5V, TA=0 - 85°C; (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
100MHz, RL=0Ω, CL = 0pF
133MHz, RL=0Ω, CL = 0pF
200MHz, RL=0Ω, CL = 0pF
VDD=2.5V, VOUT=1V
VDD=2.5V, VOUT=1.2V
VDD=2.5V
MIN
TYP
141
188
271
-43
38
MAX
-18
UNITS
mA
mA
mA
mA
IDD2.5
Operating Supply Current
IOH
IOL
Output High Current
Output Low Current
26
mA
VOH
VOL
High-level output voltage
Low-level output voltage
1.7
2
V
V
IOH = -12 mA
VDD=2.5V
0.4
0.6
IOH = 12 mA
VDD = 2.5V
Output differential-pair
Crossing voltage
VOC
CIN
1.05
2
1.25
1.45
V
100/133/166/ 200 Mhz
VI = GND or VDD
Input Capacitance1
pF
1Guaranteed by design, not 100% tested in production.
Recommended Operating Condition
SEL_DDR=1 DDR Outputs VDD=2.5V, TA=0 - 85°C; (unless otherwise stated)
PARAMETER
Power Supply Voltage
Input High Voltage
Input Low Voltage
SYMBOL
VDD2.5
VIH
CONDITIONS
MIN
2.3
2
TYP
2.5
MAX
2.7
UNITS
V
V
V
V
SEL_DDR, PD# input
SEL_DDR, PD# input
VIL
0.8
2.7
VIN
Input Voltage Level
0
2.5
1Guaranteed by design, not 100% tested in production.
0606A—08/01/03
5
ICS93725
Switching Characteristics
PARAMETER
Operating Frequency
Input Clock Duty Cycle
DDR Static Phase Error
SDRAM Static Phase Error
SYMBOL
CONDITIONS
MIN
66
40
-100
-100
TYP
MAX
200
60
100
100
UNITS
MHz
%
ps
ps
din
tped
tpes
-50
-20
Not including FBOUT
to outputs
Not including FBOUT
to outputs
66MHz to 100MHz
101MHz to 200MHz
66MHz to 100MHz
101MHz to 200MHz
Tskewd
DDR output to output Skew
SDRAM output to output Skew
DDR Duty Cycle
60
100
300
ps
ps
Tskews
200
48
48
48
48
52
53
52
56
%
%
%
%
2
DC
2
SDRAM Duty Cycle
DC
DDR Rise Time
DDR Fall Time
trd
tfd
Measured between
0.55
0.68
0.91
0.95
1.15
ns
ns
20% and 80% output, CL=16pF 0.63
VOL = 0.4V, VOH = 2.4V,
CL=30pF
SDRAM Rise Time
SDRAM Fall Time
trs
tfs
0.5
0.5
1.4
1.65
1.7
1.8
ns
ns
SEL_DDR=1,VDD=2.5V ,
CL=16pF
t(C-C)D
DDR Cycle to Cycle Jitter
23
38
57
ps
ps
SEL_DDR=0,VDD=3.3V ,
CL=30pF
t(C-C)S
SDRAM Cycle to Cycle Jitter
36
1Guaranteed by design, not 100% tested in production.
2 While the pulse skew is almost constant over frequency, the duty cycle error increases at
higher frequencies. This is due to the formula: duty cycle=t2/t1, where the cycle (t1) decreases
as the frequency goes up.
Switching Waveforms
Duty CycleTiming
t1
t2
1.5V
1.5V
1.5V
SDRAMBufferLHandHLPropagationDelay
INPUT
OUTPUT
t6
t7
0606A—08/01/03
6
ICS93725
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
For more information, contact ICS for an I2C programming application note.
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D4 (H)
• ICS clock will acknowledge
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the read address D5 (H)
• ICS clock will acknowledge
• Controller (host) sends a dummy command code
• ICS clock will acknowledge
• ICS clock will send the byte count
• Controller (host) acknowledges
• Controller (host) sends a dummy byte count
• ICS clock will acknowledge
• Controller (host) starts sending first byte (Byte 0)
through byte 6
• ICS clock sends first byte (Byte 0) through byte 7
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a stop bit
• ICS clock will acknowledge each byte one at a time.
• Controller (host) sends a Stop bit
How to Write:
How to Read:
Controller (Host)
ICS (Slave/Receiver)
Controller (Host)
ICS (Slave/Receiver)
Start Bit
Address
Start Bit
Address
D4(H)
D5(H)
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Byte Count
Dummy Command Code
Dummy Byte Count
Byte 0
ACK
ACK
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte 7
ACK
Byte 1
ACK
Byte 2
ACK
Byte 3
ACK
Byte 4
ACK
Byte 5
ACK
Byte 6
Stop Bit
Byte 7
Stop Bit
Notes:
1.
The ICS clock generator is a slave/receiver, I2C component.It can read back the data stored in the latches for
verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.
2.
3.
4.
5.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller.
The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any
complete byte has been transferred. The Command code and Byte count shown above must be sent, but the
data is ignored for those two bytes. The data is loaded until a Stop sequence is issued.
At power-on, all registers are set to a default condition, as shown.
6.
0606A—08/01/03
7
ICS93725
In Millimeters
In Inches
c
N
SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS
MIN
2.41
0.20
0.20
0.13
MAX
2.80
0.40
0.34
0.25
MIN
.095
.008
.008
.005
MAX
.110
.016
.0135
.010
A
A1
b
L
E1
E
c
INDEX
AREA
D
E
E1
e
SEE VARIATIONS
10.03
7.40
SEE VARIATIONS
.395
.291
10.68
7.60
.420
.299
0.635 BASIC
0.025 BASIC
1
2
h
L
N
α
0.38
0.50
0.64
1.02
.015
.020
.025
.040
α
h xx 4455°°
D
SEE VARIATIONS
0°
SEE VARIATIONS
0°
8°
8°
VARIATIONS
D mm.
D (inch)
A
N
MIN
15.75
MAX
16.00
MIN
.620
MAX
48
.630
A1
Reference Doc.: JEDEC Publication 95, MO-118
- CC --
10-0034
e
SEATING
PLANE
b
.10 ((..000044)) CC
300 mil SSOP Package
Ordering Information
ICS93725yFT
Example:
ICS XXXX y F - T
Designation for tape and reel packaging
Package Type
F = SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
0606A—08/01/03
8
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