ICS93V850YGT [ICSI]
DDR Phase Lock Loop Clock Driver; DDR锁相环时钟驱动器
| 型号： | ICS93V850YGT |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | DDR Phase Lock Loop Clock Driver |
| 文件： | 总8页 (文件大小：168K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS93V850
Preliminary Product Preview
Integrated
Circuit
Systems, Inc.
DDR Phase Lock Loop Clock Driver
Recommended Application:
DDR Clock Driver
Pin Configuration
GND
CLKC0
CLKT0
VDD
CLKT1
CLKC1
GND
1
2
3
4
5
6
7
8
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
GND
CLKC5
CLKT5
VDD
CLKT6
CLKC6
GND
Product Description/Features:
•
•
•
Low skew, low jitter PLL clock driver
I2C for functional and output control
Feedback pins for input to output synchronization
GND
GND
•
•
Spread Spectrum tolerant inputs
With bypass mode mux
CLKC2
CLKT2
VDD
9
CLKC7
CLKT7
VDD
SDATA
FB_INC
FB_INT
VDD
FB_OUTT
FB_OUTC
GND
CLKC8
CLKT8
VDD
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
•
Operating frequency 60 to 140 MHz
SCLK
CLK_INT
CLK_INC
VDDI2C
AVDD
AGND
GND
CLKC3
CLKT3
VDD
SwitchingCharacteristics:
•
•
•
•
•
•
PEAK - PEAK jitter (66MHz): <120ps
PEAK - PEAK jitter (>100MHz): <75ps
CYCLE - CYCLE jitter (66MHz):<120ps
CYCLE - CYCLE jitter (>100MHz):<65ps
OUTPUT - OUTPUT skew: <100ps
Slew Rate: 1V/ns - 2V/ns
CLKT4
CLKC4
GND
CLKT9
CLKC9
GND
48-Pin TSSOP
Block Diagram
Functionality
INPUTS
OUTPUTS
PLL State
AVDD CLK_INT CLK_INC CLKT CLKC FB_OUTT FB_OUTC
FB_OUTT
FB_OUTC
GND
GND
L
H
L
L
H
L
L
H
L
Bypassed/Off
Bypassed/Off
H
H
H
CLKT0
CLKC0
2.5V
(nom)
L
H
L
L
H
L
L
H
H
L
On
On
Off
CLKT1
CLKC1
2.5V
(nom)
H
H
Control
SCLK
CLKT2
CLKC2
2.5V
(nom)
Logic
SDATA
<20 MHz <20 MHz Hi-Z Hi-Z
Hi-Z
Hi-Z
CLKT3
CLKC3
CLKT4
CLKC4
FB_INT
FB_INC
CLKT5
CLKC5
PLL
CLK_INC
CLK_INT
CLKT6
CLKC6
CLKT7
CLKC7
CLKT8
CLKC8
AVDD
CLKT9
CLKC9
0423H—07/03/03
PRODUCT PREVIEW documents contain information on new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to
changewithoutnotice.
ICS93V850
Preliminary Product Preview
Pin Descriptions
PIN NUMBER
PIN NAME
TYPE
DESCRIPTION
1, 7, 8, 18, 24, 25,
31, 41, 42, 48
GND
PWR Ground
26, 30, 40, 43, 47,
23, 19, 9, 6, 2
CLKC(9:0)
CLKT(9:0)
VDD
OUT
OUT
"Complementary" clocks of differential pair outputs.
"True" Clock of differential pair outputs.
27, 29, 39, 44, 46,
22, 20, 10, 5, 3
4, 11, 21, 28,
34, 38, 45,
PWR Power supply 2.5V
12
13
14
15
16
17
SCLK
IN
IN
IN
Clock input of I2C input, 5V tolerant input
CLK_INT
CLK_INC
VDDI2C
AVDD
"True" reference clock input
"Complementary" reference clock input
PWR 3.3V power for I2C
PWR Analog power supply, 2.5V
AGND
PWR Analog ground.
"Complementary" Feedback output, dedicated for external feedback. It
32
FB_OUTC
OUT
switches at the same frequency as the CLK. This output must be wired
to FB_INC.
"True" " Feedback output, dedicated for external feedback. It switches
at the same frequency as the CLK. This output must be wired to
FB_INT.
33
35
FB_OUTT
FB_INT
OUT
IN
"True" Feedback input, provides feedback signal to the internal PLL for
synchronization with CLK_INT to eliminate phase error.
"Complementary" Feedback input, provides signal to the internal PLL
for synchronization with CLK_INC to eliminate phase error.
36
37
FB_INC
SDATA
IN
IN
Data input for I2C serial input, 5V tolerant input
0423H—07/03/03
2
ICS93V850
Preliminary Product Preview
Byte 0: Output Control
(1= enable, 0 = disable)
Byte 1: Output Control
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
PIN# PWD
DESCRIPTION
CLKT0, CLKC0
BIT PIN# PWD
DESCRIPTION
CLKT8, CLKC8
3, 2
5, 6
1
1
1
1
1
1
1
1
Bit 7 29, 30
Bit 6 27, 26
1
1
0
0
0
0
0
0
CLKT9, CLKC9
Reserved
CLKT1, CLKC1
CLKT2, CLKC2
CLKT3, CLKC3
CLKT4, CLKC4
CLKT5, CLKC5
CLKT6, CLKC6
CLKT7, CLKC7
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
10, 9
20, 19
Reserved*
Reserved*
Reserved
Bit 3 22, 23
Bit 2 46, 47
Bit 1 44, 43
Bit 0 39, 40
Reserved
Reserved
* Note: Do not change this bit value.
Byte 2: Reserved
(1= enable, 0 = disable)
Byte 3: Reserved
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN# PWD
DESCRIPTION
BIT PIN# PWD
DESCRIPTION
-
-
-
-
-
-
-
-
1
1
1
1
1
1
1
1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
1
1
1
1
1
1
1
1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Byte 4: Reserved
Byte 5: Reserved
(1= enable, 0 = disable)
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
Reserved
BIT PIN# PWD
DESCRIPTION
Reserved (Note)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
1
1
1
1
1
1
1
1
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
-
-
-
-
-
-
-
-
0
0
0
0
0
1
1
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Note: Don’t write into this register, writing into this
register can cause malfunction
0423H—07/03/03
3
ICS93V850
Preliminary Product Preview
Absolute Maximum Ratings
Supply Voltage: (VDD & AVDD) . . . . . . . . . . . . . . . -0.5V to 3.6V
(VDDI) . . . . . . . . . . . . . . . . . . . -0.5V to 4.6V
Logic Inputs: VI (except SCLK and SDATA) . . . . . . –0.5 V to VDD +0.5 V
VI (SCLK and SDATA) . . . . . . . . . –0.5 V to VDDI2C +0.5 V
Logic Outputs: VO (except SDATA) . . . . . . . . . . . . . –0.5 V to VDD +0.5 V
VO (SDATA) . . . . . . . . . . . . . . . . –0.5 V to VDDI2C +0.5 V
Input clamp current: IIK (VI < 0 or VI > VDD) . . . . +/- 50mA
Output clamp current: IOK (VO < 0 or VO > VDD) +/- 50mA
Continuous output current: IO (VO = 0 to VDD) . . +/- 50mA
Package thermal impedance, theta JA: DGG package +89°C/W
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device.These
ratings are stress specifications only and functional operation of the device at these or any other conditions above
those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)
PARAMETER
Input High Current
Input Low Current
SYMBOL
CONDITIONS
VI = VDD or GND
VI = VDD or GND
MIN
TYP
MAX
UNITS
µA
IIH
IIL
µA
Operating Supply
Current
IDD2.5 CL = 0pf
IDDPD CL = 0pf
mA
mA
mA
100
±10
Output High Current
Output Low Current
IOH
IOL
VDD = 2.3V, VOUT = 1V
-18
26
VDD = 2.3V, VOUT = 1.2V
mA
High Impedance
Output Current
VDD=2.7V, Vout=VDD or
GND
IOZ
VIK
mA
V
Input Clamp Voltage
Iin = -18mA
VDD = min to max,
IOH = -1 mA
VDD = 2.3V,
IOH = -12 mA
VDD = min to max
IOL=1 mA
V
V
High-level output
voltage
VOH
0.1
0.6
Low-level output voltage
VOL
VDD = 2.3V
IOH=12 mA
V
Input Capacitance1
Output Capacitance1
CIN
VI = GND or VDD
pF
pF
COUT
VOUT = GND or VDD
3
1Guaranteed by design, not 100% tested in production.
0423H—07/03/03
4
ICS93V850
Preliminary Product Preview
Recommended Operating Condition
TA = 0 - 85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
DD, AVDD
2.3
2.5
2.7
V
Analog/core supply
voltage
VDDI2C
2.3
3.6
V
VIL
VIH
-0.3
0.4
VDD-0.4
VDD+0.3
V
V
V
V
Input voltage level
Input differential-pair
voltage swing1
DC - CLK_INT, FB_INT
AC - CLK_INT, FB_INT
0.36
0.5
VDDQ +0.6
VDDQ +0.6
VID
VIC
Input differential-pair
crossing voltage
Output differential-pair
crossing voltage
0.45x(VIH-VIL)
0.55x(VIH-VIL)
V
V
VOC
1 Differential inputs signal voltages specifies the differential voltage [VTR - VCP] required for switching,
where VT is the true input level and VCP is the complementary input level.
Timing Requirements
TA = 0 - 85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)
CONDITIONS
PARAMETER
Operating clock frequency
Input clock duty cycle
SYMBOL
freqop
dtin
MIN
66
MAX UNITS
170
60
MHz
%
40
from VDD = 3.3V to 1%
target freq.
CLK stabilization
TSTAB
100
µs
Switching Characteristics
PARAMETER
CONDITION
66MHz
100/125/133/167MHz
66MHz
SYMBOL
MIN
TYP
MAX UNITS
120
75
110
65
ps
ps
ps
ps
ps
Jitter; Absoulte Jitter
Tjabs
Cycle to Cycle Jitter1
Tcyc-Tcyc
100/125/133/167MHz
Phase error
t(phase error)
Tskew
-150
150
Output to Output Skew
Pulse skew
100
100
75
ps
ps
ps
Tskewp
Half Period Jitter
Tjitter Hp
66/100/133/166MHz
-75
1
Typ: Propagation Delay
Time
Bypass Mode CLK to
any output
4
ns
Slew Rate
tSLEW
Load = 120Ω/14pF
1.8
2
V/ns
Notes:
1. Refers to transition on noninverting output.
2. While the pulse skew is almost constant over frequency, the duty cycle error
increases at higher frequencies.This is due to the formula: duty cycle=twH/tc, were
the cycle (tc) decreases as the frequency goes up.
0423H—07/03/03
5
ICS93V850
Preliminary Product Preview
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
For more information, contact ICS for an I2C programming application note.
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2 (H)
• ICS clock will acknowledge
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the read address D3 (H)
• ICS clock will acknowledge
• Controller (host) sends a dummy command code
• ICS clock will acknowledge
• ICS clock will send the byte count
• Controller (host) acknowledges
• Controller (host) sends a dummy byte count
• ICS clock will acknowledge
• Controller (host) starts sending first byte (Byte 0)
through byte 5
• ICS clock sends first byte (Byte 0) through byte 5
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a stop bit
• ICS clock will acknowledge each byte one at a time.
• Controller (host) sends a Stop bit
How to Write:
Controller (Host)
ICS (Slave/Receiver)
How to Read:
Start Bit
Controller (Host)
ICS (Slave/Receiver)
Address
Start Bit
D2(H)
Address
D3(H)
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Dummy Command Code
ACK
Byte Count
Dummy Byte Count
Byte 0
ACK
ACK
ACK
ACK
ACK
ACK
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
ACK
Stop Bit
Stop Bit
Notes:
1.
The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches
for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
2.
3.
4.
5.
The data byte format is 8 bit bytes.
To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the
controller.The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop
after any complete byte has been transferred. The Command code and Byte count shown above must be
sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued.
At power-on, all registers are set to a default condition, as shown.
6.
0423H—07/03/03
6
ICS93V850
Preliminary Product Preview
Recommended Layout for the ICS93V850
General Layout Precautions:
Use copper flooded ground on the top signal layer under the
clock buffer The area under U1 on the right is an example.
Flood over the ground vias.
1) Use power vias for power and ground. Vias 20 mil or
larger in diameter have lower high frequency impedance.
Vias for signals may be minimum drill size.
2) Make all power and ground traces are as wide as the via
pad for lower inductance.
3) VAA for pin 16 has a low pass RC filter to decouple the
digital and analog supplies. The 4.7uF capacitors may be
replaced with a single low ESR device with the same
total capacitance. VAA is routed on a outside signal
layer. Do not cut a power or ground plane and route in it.
4) Notice that ground vias are never shared.
5) When ever possible, VCC (net V2P5 in the schematic)
pins have a decoupling capacitor. Power is always routed
from the plane connection via to the capacitor pad to the
VCC pin on the clock buffer. Moats or plane cuts are not
used to isolate power.
6) Differential mode clock output traces are routed:
a. With a ground trace between the pairs. Trace is
grounded on both ends.
b. Without a ground trace, clock pairs are routed with a
separation of at least 5 times the thickness of the
dielectric. If the dielectric thickness is 4.5 mil, the
trace separation is at least 18 mils.
7) Terminate differential CLK_IN and FB_IN traces after
routing to buffer pads.
Component Values:
Ref Desg. Value
Description
CERAMIC MLC
Package
0603
C1,C4,C5,
C7,C11,C12
C2,C3,C8,
C9
.01uF
4.7uF
.22uF
CERAMIC MLC
1206
C10
CERAMIC MLC
0603
0603
0603
C6
2200pF CERAMIC MLC
R9,R12
120 Ω
R9
U1
0603
4.7 Ω
ICS93701AG
TSSOP48
0423H—07/03/03
7
ICS93V850
Preliminary Product Preview
c
N
In Millimeters
In Inches
SYMBOL
COMMON DIMENSIONS COMMON DIMENSIONS
L
MIN
--
0.05
0.80
0.17
0.09
MAX
1.20
0.15
1.05
0.27
0.20
MIN
--
.002
.032
.007
.0035
MAX
.047
.006
.041
.011
.008
A
A1
A2
b
E1
E
INDEX
AREA
c
1
22
D
E
SEE VARIATIONS
8.10 BASIC
SEE VARIATIONS
0.319 BASIC
a
D
E1
e
6.00
6.20
.236
0.020 BASIC
.244
0.50 BASIC
L
0.45
0.75
.018
.030
N
SEE VARIATIONS
SEE VARIATIONS
A
A2
0°
--
8°
0.10
0°
--
8°
.004
α
aaa
A1
- CC --
VARIATIONS
e
SEATING
PLANE
b
D mm.
D (inch)
N
MIN
MAX
12.60
MIN
.488
MAX
.496
aaa
C
48
12.40
Reference Doc.: JEDEC Publication 95, M O-153
6.10 mm. Body, 0.50 mm. pitch TSSOP
(20 mil)
10 - 0 0 3 9
(240 mil)
Ordering Information
ICS93V850yGT
Example:
ICS XXXX y G - PPP - T
Designation for tape and reel packaging
Pattern Number (2 or 3 digit number for parts with ROM code
patterns)
PackageType
G = TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS, AV = Standard Device
0423H—07/03/03
8
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