ICS93V855AG-T [IDT]
93V SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28, 4.40 MM, 0.65 MM PITCH, MO-153, TSSOP-28;
| 型号： | ICS93V855AG-T |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | 93V SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28, 4.40 MM, 0.65 MM PITCH, MO-153, TSSOP-28 驱动 光电二极管 输出元件 逻辑集成电路 |
| 文件： | 总10页 (文件大小：93K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS93V855I
Integrated
Circuit
Systems, Inc.
DDR Phase Lock Loop Clock Driver
RecommendedApplication:
Pin Configuration
DDR Clock Driver
GND
1
2
3
4
5
6
7
8
9
28 DDRC4
27 DDRT4
26 VDD2.5
25 GND
24 FB_OUTC
23 FB_OUTT
22 VDD2.5
21 FB_INT
20 FB_INC
19 GND
ProductDescription/Features:
DDRC0
DDRT0
VDD2.5
CLK_INT
CLK_INC
AVDD2.5
AGND
•
•
Low skew, low jitter PLL clock driver
External feedback pins for input to output
synchronization
•
•
•
•
Spread Spectrum tolerant inputs
With bypass mode mux
Operating frequency 60 to 170 MHz
OperatingTemperature–45°Cto+85°C
GND
DDRC1 10
DDRT1 11
VDD2.5 12
DDRT2 13
DDRC2 14
18 VDD2.5
17 DDRT3
16 DDRC3
15 GND
SwitchingCharacteristics:
•
•
CYCLE - CYCLE jitter:<75ps
OUTPUT - OUTPUT skew: <60ps
•
Output Rise and Fall Time: 650ps - 950ps
28-Pin 4.4mm TSSOP
Block Diagram
Functionality
INPUTS
OUTPUTS
PLL State
AVDD CLK_INT CLK_INC DDRT DDRC FB_OUTT FB_OUTC
GND
GND
L
H
L
L
H
L
L
H
L
Bypassed/Off
Bypassed/Off
FB_OUTT
FB_OUTC
H
H
H
2.5V
(nom)
L
H
L
L
H
H
L
L
H
H
L
On
On
Off
DDRT0
DDRC0
2.5V
(nom)
H
DDRT1
DDRC1
2.5V
(nom)
<20 MHz <20 MHz
Hi-Z
Hi-Z
Hi-Z
Hi-Z
DDRT2
DDRC2
Control
Logic
DDRT3
DDRC3
DDRT4
DDRC4
FB_INT
FB_INC
PLL
CLK_INC
CLK_INT
AVDD2.5
0783C—06/01/04
ICS93V855I
Pin Descriptions
PIN #
PIN NAME
PIN TYPE
PWR
OUT
OUT
PWR
IN
DESCRIPTION
1
2
3
4
5
6
7
8
GND
Ground pin.
DDRC0
DDRT0
VDD2.5
CLK_INT
CLK_INC
AVDD2.5
AGND
"Complimentary" Clock of differential pair output.
"True" Clock of differential pair output.
Power supply, nominal 2.5V
"True" reference clock input.
IN
"Complimentary" reference clock input.
2.5V Analog Power pin for Core PLL
Analog Ground pin for Core PLL
Ground pin.
"Complimentary" Clock of differential pair output.
"True" Clock of differential pair output.
Power supply, nominal 2.5V
"True" Clock of differential pair output.
"Complimentary" Clock of differential pair output.
Ground pin.
"Complimentary" Clock of differential pair output.
"True" Clock of differential pair output.
Power supply, nominal 2.5V
PWR
PWR
PWR
OUT
OUT
PWR
OUT
OUT
PWR
OUT
OUT
PWR
PWR
9
GND
10
11
12
13
14
15
16
17
18
19
DDRC1
DDRT1
VDD2.5
DDRT2
DDRC2
GND
DDRC3
DDRT3
VDD2.5
GND
Ground pin.
Complement single-ended feedback input, provides feedback signal to
internal PLL for synchronization with CLK_INT to eliminate phase error.
20
FB_INC
IN
True single-ended feedback input, provides feedback signal to internal
PLL for synchronization with CLK_INT to eliminate phase error.
21
22
23
FB_INT
VDD2.5
IN
PWR
OUT
Power supply, nominal 2.5V
True single-ended feedback output, dedicated external feedback. It
switches at the same frequency as other DDR outputs, This output must
be connect to FB_INT.
FB_OUTT
Complement single-ended feedback output, dedicated external feedback.
It switches at the same frequency as other DDR outputs, This output must
be connect to FB_INC.
24
FB_OUTC
OUT
25
26
27
28
GND
PWR
PWR
OUT
OUT
Ground pin.
Power supply, nominal 2.5V
"True" Clock of differential pair output.
"Complimentary" Clock of differential pair output.
VDD2.5
DDRT4
DDRC4
0783C—06/01/04
2
ICS93V855I
Absolute Maximum Ratings
Supply Voltage: (VDD & AVDD) . . . . . . . . . . -0.5V to 3.6V
(VDDI) . . . . . . . . . . . . . . -0.5V to 4.6V
Logic Inputs: VI . . . . . . . . . . . . . . . . . . . . . . . VSS –0.5 V to VDD +0.5 V
Logic Outputs:VO. . . . . . . . . . . . . . . . . . . . . VSS –0.5 V to VDD +0.5 V
Input clamp current: IIK (VI < 0 or VI > VDD) +/- 50mA
Output clamp current: IOK (VO < 0 or VO > VDD)
+/- 50mA
Continuous output current: IO (VO = 0 to VDD) +/- 50mA
StorageTemperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device.These
ratings are stress specifications only and functional operation of the device at these or any other conditions above
those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = -45°C to +85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)
SYMBOL
MIN
5
TYP
MAX
UNITS
µA
PARAMETER
Input High Current
Input Low Current
CONDITIONS
VI = VDD or GND
IIH
IIL
VI = VDD or GND
5
µA
CL = 0pf, RL = 120 ohms
CL = 0pf, RL = 120 ohms
VDD = 2.3V, VOUT = 1V
Operating Supply
Current
IDD2.5
IDDPD
IOH
250
100
mA
µA
Output High Current
Output Low Current
-18
26
mA
IOL
IOZ
VIK
VDD = 2.3V, VOUT = 1.2V
mA
High Impedance
Output Current
Input Clamp Voltage
VDD=2.7V, Vout=VDD or GND
±10
-1.2
µA
Iin = -18mA
V
VDD = min to max,
VDD - 0.1
1.7
V
V
I
OH = -1 mA
DD = 2.3V,
OH = -12 mA
DD = min to max
IOL=1 mA
DD = 2.3V
OH=12 mA
VOH
High-level output voltage
V
I
V
0.1
0.6
VOL
Low-level output voltage
V
V
I
Input Capacitance1
Output Capacitance1
CIN
COUT
VI = VDD or GND
3
3
pF
pF
VI = VDD or GND
1Guaranteed by design and characterization, not 100% tested in production.
0783C—06/01/04
3
ICS93V855I
DC Electrical Characteristics
TA = -45°C to +85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)
SYMBOL
DDQ, AVDD
MIN
2.3
TYP
2.5
MAX
2.7
UNITS
V
PARAMETER
Supply Voltage
CONDITIONS
V
CLK_INT, CLK_INC, FB_INC,
FB_INT
CLK_INT, CLK_INC, FB_INC,
VIL
VDD/2 - 0.18
Low level input voltage
High level input voltage
0.4
2.1
V
V
VIH
VIN
VDD/2 + 0.18
-0.3
FB_INT
DC input signal voltage (note
2)
VDD + 0.3
V
DC - CLK_INT, CLK_INC,
FB_INC, FB_INT
AC - CLK_INT, CLK_INC,
VDD + 0.6
VDD + 0.6
VDD/2 + 0.15
VDD/2 + 0.2
85
0.36
V
Differential input signal
voltage (note 3)
VID
0.7
V
FB_INC, FB_INT
Output differential cross-
voltage (note 4)
Input differential cross-
voltage (note 4)
Operating free-air
temperature
VOX
VIX
TA
VDD/2 - 0.15
VDD/2 - 0.2
V
VDD/2
V
-45
°C
Notes:
1 Unused inputs must be held high or low to prevent them from floating.
2 DC input signal voltage specifies the allowable DC excursion of differential input.
3 Differential inputs signal voltages specifies the differential voltage [VT-VCP] required for switching,
where VTR is the true input level and VCP is the complementary input level.
4 Differential cross-point voltage is expected to track variations of VDD and is the voltage at which the
differential signal must be crossing.
0783C—06/01/04
4
ICS93V855I
Switching Characteristics
TA = -45°C to +85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)
PARAMETER
Max clock frequency3
SYMBOL
freqop
CONDITION
MIN
33
TYP
MAX UNITS
233
MHz
Application Frequency
Range3
freqApp
60
170
MHz
dtin
tsl(o)
Input clock duty cycle
Output clock slew rate
40
1
60
2
%
v/ns
µs
TSTAB
CLK stabilization
100
Low-to high level propagation
delay time
High-to low level propagation
delay time
1
CLK_IN to any output
CLK_IN to any output
5.5
5.5
ns
ns
tPLH
1
tPHL
ten
tdis
Output enable time
PD# to any output
PD# to any output
5
5
ns
ns
Output disable time
Period jitter
tjit (per)
tjit(hper)
tsl(I)
-75
-100
1
75
100
2
ps
Half-period jitter
Input clock slew rate
Cycle to Cycle Jitter
Phase error4
Output to Output Skew
Rise Time, Fall Time
ps
Over the application
frequency range
v/ns
ps
t
cyc-tcyc
t(phase error)
tskew
-75
-50
75
50
ps
40
60
ps
tr, tf
Load = 120Ω/16pF
650
800
950
ps
Notes:
1. Refers to transition on noninverting output in PLL bypass mode.
2. While the pulse skew is almost constant over frequency, the duty cycle error
increases at higher frequencies. This is due to the formula: duty cycle=twH/tc,
were the cycle (tc) decreases as the frequency goes up.
3. Switching characteristics are guaranteed for application frequency range. The PLL
Locks over the Max Clock Frequency range, but the device doe not necessarily
meet other timing parameters.
4. Does not include jitter.
0783C—06/01/04
5
ICS93V855I
Parameter Measurement Information
V
DD
V
(CLKC)
R = 60Ω
V
/2
R = 60Ω
DD
V
(CLKC)
ICS93V855I
GND
Figure 1. IBIS Model Output Load
V
DD/2
C = 16 pF
ICS93V855I
-V
DD/2
SCOPE
R = 10Ω Z = 50Ω
Z = 60Ω
Z = 60Ω
R = 50Ω
(TT)
V
R = 10Ω
Z = 50Ω
R = 50Ω
C = 16 pF
DD/2
V
(TT)
-V
-V
DD/2
NOTE: V
(TT) = GND
Figure 2. Output Load Test Circuit
YX, FB_OUTC
YX, FB_OUTT
t
t
c(n+1)
c(n)
t
= t
± t
jit(cc) c(n) c(n+1)
Figure 3. Cycle-to-Cycle Jitter
0783C—06/01/04
6
ICS93V855I
Parameter Measurement Information
CLK_INC
CLK_INT
FB_INC
FB_INT
t
t
( ) n
( ) n+1
n = N
t
1
( ) n
t
=
( )
N
(N is a large number of samples)
Figure 4. Static Phase Offset
YX
#
YX
YX, FB_OUTC
YX, FB_OUTT
t(skew)
Figure 5. Output Skew
YX, FB_OUTC
YX, FB_OUTT
tC(n)
YX, FB_OUTC
YX, FB_OUTT
1
fO
1
t(jit_per) = tc(n) -
fO
Figure 6. Period Jitter
0783C—06/01/04
7
ICS93V855I
Parameter Measurement Information
YX, FB_OUTC
YX, FB_OUTT
t
t
jit(hper_n+1)
jit(hper_n)
1
f
o
tjit(hper) = tjit(hper_n)
1
2xfO
-
Figure 7. Half-Period Jitter
80%
80%
V , V
ID OD
20%
20%
Clock Inputs
and Outputs
t
t
slf
slr
Figure 8. Input and Output Slew Rates
0783C—06/01/04
8
ICS93V855I
In Millimeters
COMMON DIMENSIONS COMMON DIMENSIONS
In Inches
c
SYMBOL
N
MIN
--
0.05
0.80
0.19
0.09
MAX
1.20
0.15
1.05
0.30
0.20
MIN
--
.002
.032
.007
.0035
MAX
.047
.006
.041
.012
.008
A
A1
A2
b
L
E1
E
INDEX
AREA
c
D
E
SEE VARIATIONS
6.40 BASIC
SEE VARIATIONS
0.252 BASIC
E1
e
L
4.30
0.65 BASIC
0.45
4.50
.169
0.0256 BASIC
.018
.177
1
2
α
0.75
.030
D
N
SEE VARIATIONS
SEE VARIATIONS
a
aaa
0°
--
8°
0.10
0°
--
8°
.004
A
A2
VARIATIONS
A1
D mm.
D (inch)
N
- CC --
MIN
9.60
MAX
9.80
MIN
.378
MAX
.386
28
e
SEATING
PLANE
Reference Doc.: JEDEC Publication 95, MO-153
b
10-0035
aaa
C
4.40 mm. Body, 0.65 mm. pitch TSSOP
(0.0256 Inch)
(173 mil)
Ordering Information
ICS93V855yGILF-T
Example:
ICS XXXX y G LF- T
Designation for tape and reel packaging
Lead Free (Optional)
Package Type
G = TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
0783C—06/01/04
9
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93V855A (DDR PLL)
Description
Market Group
DIMM
Additional Info
Related Orderable Parts
Attributes
Package
93V855AG
93V855AGI
93V855AGIT
93V855AGLF
93V855AGLFT
93V855AGT
TSSOP 28 (PG28)
TSSOP 28 (PG28)
TSSOP 28 (PG28)
TSSOP 28 (PGG28)
TSSOP 28 (PGG28)
TSSOP 28 (PG28)
NA
C
NA
I
NA
I
NA
C
NA
C
NA
C
Speed
Temperature
Voltage
Status
3.3 V
Active
No
3.3 V
Active
No
3.3 V
Active
No
3.3 V
Active
No
3.3 V
Active
No
3.3 V
Active
No
Sample
Minimum Order
Quantity
384
48
288
48
2000
2000
384
48
1000
1000
1000
1000
Factory Order
Increment
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