ICS950227 [ICSI]
Programmable Timing Control Hub for P4; 可编程定时控制中心的P4
| 型号： | ICS950227 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Programmable Timing Control Hub for P4 |
| 文件： | 总17页 (文件大小：129K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated
Circuit
ICS950227
Systems, Inc.
Programmable Timing Control Hub™ for P4™
Recommended Application:
CK-408 clock Intel® 845 with P4 processor.
Output Features:
Pin Configuration
VDDREF
X1
1
2
3
4
5
6
7
8
9
56 REF
55 FS1
54 FS0
53 CPU_STOP#*
52 CPUCLKT0
51 CPUCLKC0
50 VDDCPU
49 CPUCLKT1
48 CPUCLKC1
47 GND
46 VDDCPU
45 CPUCLKT2
44 CPUCLKC2
43 MULTSEL0*
42 IREF
•
•
•
•
•
•
•
•
3 Differential CPU Clock Pairs @ 3.3V
X2
GND
7 PCI (3.3V) @ 33.3MHz
3 PCI_F (3.3V) @ 33.3MHz
1 USB (3.3V) @ 48MHz
PCICLK_F0
PCICLK_F1
PCICLK_F2
VDDPCI
GND
PCICLK0 10
PCICLK1 11
PCICLK2 12
PCICLK3 13
VDDPCI 14
GND 15
1 DOT (3.3V) @ 48MHz
1 REF (3.3V) @ 14.318MHz
5 3V66 (3.3V) @ 66.6MHz
1 VCH/3V66 (3.3V) @ 48MHz or 66.6MHz
Features/Benefits:
PCICLK4 16
PCICLK5 17
PCICLK6 18
VDD3V66 19
GND 20
41 GND
40 FS2
39 48MHz_USB
38 48MHz_DOT
37 VDD48
•
•
•
•
•
•
Programmable output frequency.
Programmable output divider ratios.
Programmable output rise/fall time.
Programmable output skew.
Programmable spread percentage for EMI control.
Watchdog timer technology to reset system
if system malfunctions.
3V66_2 21
3V66_3 22
3V66_4 23
3V66_5 24
*PD# 25
36 GND
35 3V66_1/VCH_CLK
34 PCI_STOP#*
33 3V66_0
32 VDD3V66
31 GND
VDDA 26
•
•
Programmable watch dog safe frequency.
GND 27
30 SCLK
Support I2C Index read/write and block read/write
operations.
Vtt_PWRGD# 28
29 SDATA
56-Pin 300-mil SSOP
•
Uses external 14.318MHz crystal.
* These inputs have 150K internal pull-up resistor to VDD.
Key Specifications:
•
•
•
CPU Output Jitter <150ps
3V66 Output Jitter <250ps
CPU Output Skew <100ps
Block Diagram
Frequency Table
66Buff[2:0]
3V66[4:2]
(MHz)
PCI_F
PCI
(MHz)
CPU
(MHz)
3V66
(MHz)
FS2 FS1 FS0
PLL2
48MHz_USB
48MHz_DOT
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
66.66
100.00
200.00
133.33
Tristate
66.66
66.66
66.66
66.66
Tristate
66.66
66.66
33.33
33.33
X1
XTAL
OSC
3V66_1/VCH_CLK
REF
0
66.66
33.33
PLL1
Spread
Spectrum
0
66.66
33.33
CPUCLKT (2:0)
CPUCLKC (2:0)
CPU
DIVDER
3
Stop
Stop
3
Mid
Mid
Mid
Mid
Tristate
TCLK/4
Tristate
TCLK/8
PCI
DIVDER
PCICLK (6:0)
TCLK/2 TCLK/4
WDEN
PD#
7
3
PCICLK_F (2:0)
Reserved Reserved Reserved Reserved
Reserved Reserved Reserved Reserved
Control
Logic
CPU_STOP#
PCI_STOP#
MULTSEL0
FS (2:0)
3V66
DIVDER
3V66 (5:2,0)
I REF
5
Config.
Reg.
SDATA
SCLK
Vtt_PWRGD#
0641D—07/03/03
Integrated
Circuit
ICS950227
Systems, Inc.
Pin Description
PIN NUMBER
PIN NAME
TYPE
DESCRIPTION
1, 8, 14, 19, 26,
32, 37, 46, 50
VDD
PWR
3.3V power supply
X2 Crystal
Input
2
3
X1
X2
14.318MHz Crystal input
14.318MHz Crystal output
X1 Crystal
Output
Free running PCI clock not affected by PCI_STOP#
for power management.
7, 6, 5
PCICLK_F (2:0)
GND
OUT
PWR
OUT
4, 9, 15, 20, 27,
31, 36, 41, 47
Ground pins for 3.3V supply
PCI clock outputs
18, 17, 16, 13,
12,11, 10
PCICLK (6:0)
24, 23, 22, 21
25
3V66 (5:2)
PD#
OUT
IN
66MHz reference clocks, from internal VCO
Invokes power-down mode. Active Low.
This 3.3V LVTTL input is a level sensitive strobe used to
determine when FS(2:0) and MULTISEL0 inputs are valid
and are ready to be sampled
28
Vtt_PWRGD#
IN
(active low)
Data pin for I2C circuitry 5V tolerant
Clock pin of I2C circuitry 5V tolerant
66MHz reference clocks, from internal VCO
29
30
33
SDATA
SCLK
I/O
IN
3V66_0
OUT
Halts PCICLK clocks at logic 0 level, when input low except
PCICLK_F which are free running
34
PCI_STOP#
IN
3.3V output selectable through I2C to be 66MHz from internal VCO
or
35
3V66_1/VCH_CLK
OUT
48MHz (non-SSC)
38
39
40
48MHz_DOT
48MHz_USB
FS2
OUT
OUT
IN
48MHz output clock for DOT
48MHz output clock for USB
Special 3.3V input for Mode selection, cannot be logic 1
This pin establishes the reference current for the CPUCLK pairs.
This pin requires a fixed precision resistor tied to ground in order to
establish the appropriate current.
42
I REF
OUT
43
MULTSEL0
IN
3.3V LVTTL input for selecting the current multiplier for CPU outputs
"Complementory" clocks of differential pair CPU outputs. These are
current outputs and external resistors are required for voltage bias.
44, 48, 51
CPUCLKC (2:0)
OUT
"True" clocks of differential pair CPU outputs. These are current
outputs and external resistors are required for voltage bias.
45, 49, 52
CPUCLKT (2:0)
OUT
53
55, 54
56
CPU_STOP#
FS (1:0)
REF
IN
IN
Halts CPUCLK clocks at logic 0 level, when input low
Frequency select pins
OUT
14.318MHz reference clock.
Power Groups
(Analog)
(Digital)
VDDA = Analog Core PLL1
VDDREF = REF, Xtal
VDD48 = 48MHz, PLL
VDDPCI
VDD3V66
VDDCPU
0641D—07/03/03
2
Integrated
Circuit
ICS950227
Systems, Inc.
Truth Table
PCI_F
PCI
(MHz)
CPU
(MHz)
3V66 (5:0)
(MHz)
REF0
(MHz)
USB/DOT
(MHz)
FS2
FS1
FS0
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
66.66
100.00
200.00
133.33
Tristate
TCLK/2
66.66
66.66
33.33
33.33
14.318
14.318
48.00
48.00
0
66.66
33.33
14.318
48.00
0
66.66
33.33
14.318
48.00
Mid
Mid
Mid
Mid
Tristate
TCLK/4
Tristate
TCLK/8
Tristate
TCLK
Tristate
TCLK/2
Reserved
Reserved
Reserved Reserved Reserved
Reserved Reserved Reserved
Reserved
Reserved
Maximum Allowed Current
Max 3.3V supply consumption
Max discrete cap loads,
Vdd = 3.465V
Condition
All static inputs = Vdd or GND
Powerdown Mode
(PWRDWN# = 0)
40mA
Full Active
360mA
Host Swing Select Functions
Reference R,
Iref =
VDD/(3*Rr)
Board Target
MULTISEL0
Output
Current
Voh @ Z
Trace/Term Z
Rr = 475 1%,
Iref = 2.32mA
1
50 ohms
Ioh = 6* I REF 0.7V @ 50
0641D—07/03/03
3
Integrated
Circuit
ICS950227
Systems, Inc.
General I2C serial interface information
How to Read:
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2 (H)
• ICS clock will acknowledge
• Controller (host) will send start bit.
• Controller (host) sends the write address D2 (H)
• ICS clock will acknowledge
• Controller (host) sends the begining byte location = N
• ICS clock will acknowledge
• Controller (host) sends the begining byte
location = N
• Controller (host) sends the data byte count = X
• ICS clock will acknowledge
• Controller (host) starts sending Byte N through
Byte N + X -1
• ICS clock will acknowledge
• Controller (host) will send a separate start bit.
• Controller (host) sends the read address D3 (H)
• ICS clock will acknowledge
(see Note 2)
• ICS clock will send the data byte count = X
• ICS clock sends Byte N + X -1
• ICS clock sends Byte 0 through byte X (if X(H)
was written to byte 8).
• ICS clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
• Controller (host) will need to acknowledge each
byte
• Controllor (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
Index Block Read Operation
Index Block Write Operation
Controller (Host)
ICS (Slave/Receiver)
Controller (Host)
ICS (Slave/Receiver)
T
starT bit
starT bit
T
Slave Address D2(H)
Slave Address D2(H)
WR
WRite
WR
WRite
ACK
ACK
ACK
ACK
ACK
ACK
Beginning Byte = N
Beginning Byte = N
Data Byte Count = X
Beginning Byte N
RT
Repeat starT
Slave Address D3(H)
RD
ReaD
ACK
Data Byte Count = X
Beginning Byte N
ACK
ACK
Byte N + X - 1
ACK
P
stoP bit
Byte N + X - 1
N
P
Not acknowledge
stoP bit
0641D—07/03/03
4
Integrated
Circuit
ICS950227
Systems, Inc.
I2C Table: Frequency Select Register
Byte 0
Pin #
Name
Control Function
Frequency H/W IIC
Select
Type
0
1
PWD
-
SPREAD ENABLE
RW
OFF
ON
0
Bit 7
CENTER/DOWNSP CENTER/DOWNSPRE
READ SELECT AD SELECT
3V66/VCH SELECT 48MHz/66.66MHz SEL
DOWN
SPREAD
66.66MHz
CENTER
SPREAD
48.00MHz
-
RW
RW
R
0
0
X
Bit 6
Bit 5
Bit 4
35
53
READBACK
CPU_STOP#
CPU STOP Read Back
Freq Select Bit 3
PCI_STOP#
HW/SW SELECT
PCI
RUNNING
34
40
55
54
RW/R
PCI STOP
1
Bit 3
Bit 2
Bit 1
Bit 0
Freq Select 2 Read
Back
Freq Select 1 Read
Back
Freq Select 0 Read
Back
FS2
FS1
FS0
R
R
R
X
X
X
READBACK
I2C Table: Spreading and Device Behavior Control Register
Byte 1
Pin #
Name
Control Function
MULTSEL0
READBACK
Watchdog Alarm Read
Back
Type
0
1
PWD
43
-
READBACK
MULTSEL0
R
X
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
WD ALARM
CPU2/CPUC2
CPU1/CPUC1
CPU0/CPUC0
R
NO ALARM ALARM SET
STOPPABLE FREE-RUN
STOPPABLE FREE-RUN
STOPPABLE FREE-RUN
0
0
0
0
45, 44
49, 48
52, 51
RW
RW
RW
CPU FREE-RUN NING
CONTROL
CPU2/CPUC2
CPU1/CPUC1
CPU0/CPUC0
Output Control
Output Control
Output Control
RW
RW
RW
Disable
Disable
Disable
Enable
Enable
Enable
1
1
1
45, 44
49, 48
52, 51
Bit 2
Bit 1
Bit 0
I2C Table: Output Control Register
Byte 2
Pin #
Name
Control Function
Reserved
Type
RW
RW
RW
RW
RW
RW
RW
0
-
1
-
PWD
-
Reserved
PCICLK6
PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLK1
0
1
1
1
1
1
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
18
17
16
13
12
11
10
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Disable
Disable
Disable
Disable
Disable
Disable
Enable
Enable
Enable
Enable
Enable
Enable
PCICLK0
Output Control
RW
Disable
Enable
1
I2C Table: Output Control Register
Byte 3
Pin #
Name
48MHz_DOT
48MHz_USB
Control Function
Output Control
Output Control
Type
RW
RW
0
1
PWD
1
1
38
39
Disable
Disable
Enable
Enable
Bit 7
Bit 6
7
6
5
PCIF2
PCIF1
PCIF0
RW
RW
RW
FREE-RUN STOPPABLE
FREE-RUN STOPPABLE
FREE-RUN STOPPABLE
0
0
0
Bit 5
Bit 4
Bit 3
CPU FREE-RUN NING
CONTROL
7
6
5
Output Control
Output Control
Output Control
RW
RW
RW
Disable
Disable
Disable
Enable
Enable
Enable
1
1
1
PCICLK_F2
PCICLK_F1
PCICLK_F0
Bit 2
Bit 1
Bit 0
0641D—07/03/03
5
Integrated
Circuit
ICS950227
Systems, Inc.
I2C Table: Output Control Register
Byte 4
Pin #
Name
RESERVED
RESERVED
3V66_0
Control Function
RESERVED
Type
-
`
RW
RW
RW
RW
RW
0
-
-
1
-
-
PWD
-
-
0
0
1
1
1
1
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RESERVED
33
35
24
23
22
21
Output Control
Output Control
Output Control
Output Control
Output Control
Disable
Disable
Disable
Disable
Disable
Enable
Enable
Enable
Enable
Enable
3V66_1/VHC_CLK
3V66_5
3V66_4
3V66_3
3V66_2
Output Control
RW
Disable
Enable
1
I2C Table: Output Control and Fix Frequecy Register
Byte 5
Pin #
Name
Control Function
Type
-
-
-
-
0
-
-
-
-
1
-
-
-
-
PWD
-
-
-
-
RESERVED
RESERVED
RESERVED
RESERVED
-
-
-
-
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
RW
00= MEDIUM (DEFAULT)
10= LOW
DOT CLOCK EDGE
RATE CONTROL
38
48MHz_DOT
RW
RW
0
0
Bit 2
Bit 1
01= HIGH
00= MEDIUM (DEFAULT)
01= LOW
USB EDGE RATE
CONTROL
39
48MHz_USB
RW
0
Bit 0
10= HIGH
I2C Table: Vendor & Revision ID Register
Byte 6
Pin #
Name
RID3
RID2
RID1
RID0
VID3
VID2
VID1
Control Function
Type
R
R
R
R
R
R
R
0
-
-
-
-
-
-
-
1
-
-
-
-
-
-
-
PWD
-
-
-
-
-
-
-
-
1
1
1
1
1
1
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
REVISION ID
VENDOR ID
VID0
R
-
-
1
I2C Table: DEVICE ID
Byte 7
Pin #
Name
Control Function
Type
R
R
R
R
R
R
R
0
-
-
-
-
-
-
-
1
-
-
-
-
-
-
-
PWD
-
-
-
-
-
-
-
-
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R
-
-
1
0641D—07/03/03
6
Integrated
Circuit
ICS950227
Systems, Inc.
I2C Table: Byte Count Register
Byte 8
Pin #
Name
BC7
BC6
BC5
BC4
BC3
BC2
BC1
Control Function
Type
RW
RW
RW
RW
RW
RW
RW
0
-
-
-
-
-
-
-
1
-
-
-
-
-
-
-
PWD
-
-
-
-
-
-
-
-
0
0
0
0
1
1
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Writing to this register
will configure how
many bytes will be read
back, default is 0F = 15
bytes.
BC0
RW
-
-
1
I2C Table: Watchdog Timer Register
Byte 9
Pin #
Name
RESERVED
RESERVED
Control Function
RESERVED
Type
RW
RW
0
-
-
1
-
-
PWD
0
0
-
-
-
-
-
-
-
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
RESERVED
RESERVED
WD4
RESERVED
RW
RW
RW
RW
RW
-
-
-
-
-
-
-
-
-
-
0
0
1
0
1
These bits represent
X*290ms the watchdog
timer will wait before it
goes to alarm mode.
Default is10X 290ms
=2.9seconds
WD3
WD2
WD1
-
WD0
RW
-
-
0
Bit 0
I2C Table: VCO Control Select Bit & WD Timer Control Register
Byte 10
Pin #
Name
Control Function
Type
0
1
PWD
M/N Programming
Enable
Watchdog Enable
WD Safe Frequency
Mode
Latched
Input
OFF
Latched
IIC Prog.
B(11:17)
ON
WD B10
-
-
-
M/NEN
WDEN
RW
RW
RW
0
0
0
Bit 7
Bit 6
Bit 5
WDFSEN
FS/Byte0
b(4:0)
-
-
-
-
-
WD SS EN
WD MultSEL
WD FS2
RW
RW
RW
RW
RW
-
-
-
-
-
-
-
-
0
0
0
0
0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Writing to these bit will
configure the safe
frequency configuration
WD FS1
WD FS0
-
-
I2C Table: VCO Frequency Control Register
Byte 11
Bit 7
Pin #
Name
N Div8
M Div6
M Div5
M Div4
M Div3
M Div2
M Div1
Control Function
N Divider Bit 8
Type
RW
RW
RW
RW
RW
RW
RW
0
-
-
-
-
-
-
-
1
-
-
-
-
-
-
-
PWD
X
X
X
X
X
X
X
-
-
-
-
-
-
-
-
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
The decimal
representation of M Div
(6:0) is equal to
reference divider value.
Default at power up =
latch-in or Byte 0 Rom
table.
M Div0
RW
-
-
X
0641D—07/03/03
7
Integrated
Circuit
ICS950227
Systems, Inc.
I2C Table: VCO Frequency Control Register
Byte 12
Bit 7
Pin #
Name
N Div7
N Div6
N Div5
N Div4
N Div3
N Div2
N Div1
Control Function
Type
RW
RW
RW
RW
RW
RW
RW
0
-
-
-
-
-
-
-
1
-
-
-
-
-
-
-
PWD
X
X
X
X
X
X
X
-
-
-
-
-
-
-
-
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
The decimal
representation of N Div
(8:0) is equal to VCO
divider value. Default
at power up = latch-in
or Byte 0 Rom table.
N Div0
RW
-
-
X
I2C Table: Spread Spectrum Control Register
Byte 13
Bit 7
Pin #
Name
SSP7
SSP6
SSP5
SSP4
SSP3
SSP2
SSP1
Control Function
Type
RW
RW
RW
RW
RW
RW
RW
0
-
-
-
-
-
-
-
1
-
-
-
-
-
-
-
PWD
X
X
X
X
X
X
X
-
-
-
-
-
-
-
-
These Spread
Spectrum bits will
program the spread
pecentage. It is
recommended to use
ICS Spread % table for
spread programming.
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SSP0
RW
-
-
X
I2C Table: Spread Spectrum Control Register
Byte 14
Bit 7
Pin #
Name
Reserved
Reserved
SSP13
SSP12
SSP11
Control Function
Reserved
Type
RW
RW
RW
RW
RW
RW
RW
0
-
-
-
-
-
-
-
1
-
-
-
-
-
-
-
PWD
0
0
X
X
X
X
X
-
-
-
-
-
-
-
-
Reserved
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
It is recommended to
use ICS Spread %
table for spread
SSP10
SSP9
programming.
SSP8
RW
-
-
X
I2C Table: Output Divider Control Register
Byte 15
Bit 7
Pin #
Name
Control Function
Reserved
Type
RW
RW
RW
RW
RW
RW
RW
0
-
-
-
-
1
-
-
-
-
PWD
-
-
-
-
-
-
-
-
Reserved
Reserved
Reserved
Reserved
CPU Div3
CPU Div2
CPU Div1
0
0
0
0
X
X
X
Reserved
Reserved
Reserved
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CPU divider ratio can
be configured via these
4 bits individually.
See Table 3: Divider Ratio
Combination Table 2-3-5-7
CPU Div0
RW
X
I2C Table: Output Divider Control Register
Byte 16
Bit 7
Pin #
Name
Control Function
Reserved
Type
RW
RW
RW
RW
RW
RW
RW
0
-
-
-
-
1
-
-
-
-
PWD
-
-
-
-
-
-
-
-
Reserved
Reserved
Reserved
Reserved
3V66 Div3
3V66 Div2
3V66 Div1
0
0
0
0
X
X
X
Reserved
Reserved
Reserved
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
3V66 divider ratio can
be configured via these
4 bits individually.
See Table 3: Divider Ratio
Combination Table
3V66 Div0
RW
X
0641D—07/03/03
8
Integrated
Circuit
ICS950227
Systems, Inc.
I2C Table: Output Divider Control Register
Byte 17
Bit 7
Pin #
Name
Control Function
Reserved
Reserved
Reserved
CPU Phase Invert
Reserved
Type
RW
RW
RW
RW
RW
RW
RW
0
-
-
-
1
-
-
-
PWD
-
-
-
-
-
-
-
-
Reserved
Reserved
Reserved
CPUINV
Reserved
Reserved
Reserved
0
0
0
0
0
0
0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default
Inverse
-
-
-
-
-
-
Reserved
Reserved
Reserved
Reserved
RW
-
-
0
I2C Table: Group Skew Control Register
Byte 18
Bit 7
Pin #
Name
Control Function
Reserved
Type
RW
RW
RW
RW
RW
RW
RW
0
-
-
-
-
-
-
-
1
-
-
-
-
-
-
-
PWD
-
-
-
-
-
-
-
-
Reserved
Reserved
Reserved
Reserved
CPUSkw1
CPUSkw0
Reserved
0
0
0
0
0
1
0
Reserved
Reserved
Reserved
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CPUCLKT/C (2:0)
Skew Control
Reserved
Reserved
Reserved
RW
-
-
0
I2C Table: Group Skew Control Register
Byte 19
Bit 7
Pin #
Name
Control Function
Reserved
Type
RW
RW
RW
RW
RW
RW
RW
0
-
-
-
-
1
-
-
-
-
PWD
-
-
-
-
-
-
-
-
Reserved
Reserved
Reserved
Reserved
PCISkw3
PCISkw2
PCISkw1
0
0
0
0
0
1
0
Reserved
Reserved
Reserved
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
16-Steps Skew Control.
This byte will advance or
delay the skew by 100ps
per step
PCI (6:1) AND
PCIF(2:0) Skew
Control
PCISkw0
RW
0
I2C Table: Slew Rate Control Register
Byte 20
Bit 7
Pin #
Name
3V66ISkw
Control Function
Type
RW
0
1
PWD
0
-
-
Skew Control This byte
will advance or delay the
skew by 250 ps per step
3V66 (5:0) Skew
Control
3V66ISkw
RW
1
Bit 6
-
-
-
-
-
-
Reserved
Reserved
RESERVED
RESERVED
RESERVED
RESERVED
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
RW
RW
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
0
0
0
0
0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0641D—07/03/03
9
Integrated
Circuit
ICS950227
Systems, Inc.
I2C Table: Slew Rate Control Register
Byte 21
Bit 7
Pin #
Name
Control Function
Type
0
1
PWD
1
10=STRONG
00= MEDIUM
01= WEAK
PCICLK_F2 Slew Rate
Control
-
PCISlw
RW
0
Bit 6
10=STRONG
00= MEDIUM
01= WEAK
10=STRONG
00= MEDIUM
01= WEAK
10=STRONG
00= MEDIUM
01= WEAK
1
0
1
0
1
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PCICLK_F1:0 Slew
Rate Control
-
-
PCISlw
RW
RW
RW
3V66 (5:2) Slew Rate
Control
3V66SLW
3V66SLW
-
-
3V66 (1:0) Slew Rate
Control
0
I2C Table: Slew Rate Control Register
Byte 22
Pin #
Name
Control Function
Type
0
1
PWD
10=STRONG
00= MEDIUM
01= WEAK
10=STRONG
00= MEDIUM
01= WEAK
10=STRONG
00= MEDIUM
01= WEAK
10=STRONG
00= MEDIUM
01= WEAK
-
-
-
-
-
-
-
-
RW
1
Bit 7
PCISlw
REF Slew Rate Control
RW
RW
RW
RW
RW
RW
RW
0
1
0
1
0
1
0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PCICLK (6:4) Slew
Rate Control
PCISlw
PCISlw
PCISlw
PCICLK (3:1) Slew
Rate Control
PCICLK0 Slew Rate
Control
I2C Table: Slew Rate Control Register
Byte 23
Pin #
Name
Control Function
Type
0
1
PWD
PCI (6:4) Slew Rate
Control
-
PCISlw1
RW
-
-
1
Bit 7
-
-
-
Reserved
Reserved
Reserved
Reserved
RW
RW
RW
-
-
-
-
0
0
1
Bit 7
Bit 6
Bit 5
10=STRONG
VCH Slew Rate
Control
VCSLW
00= MEDIUM
01= WEAK
-
RW
0
Bit 4
-
-
-
-
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
RW
RW
RW
RW
-
-
-
-
-
0
0
0
0
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
0641D—07/03/03
10
Integrated
Circuit
ICS950227
Systems, Inc.
Absolute Maximum Ratings
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . 115°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN
2
TYP
MAX
UNITS
V
Input High Voltage
VIH
VDD + 0.3
Input Low Voltage
Input High Current
VIL
IIH
VSS - 0.3
-5
0.8
5
V
VIN = VDD
VIN = 0 V; Inputs with no pull-up
resistors
mA
IIL1
-5
mA
Input Low Current
VIN = 0 V; Inputs with pull-up
resistors
IIL2
-200
Operating Supply Current
IDD3.3OP
CL = Full load
283
360
25
mA
Powerdown Current
Input Frequency
Pin Inductance
IDD3.3PD
Fi
IREF=2.32 mA
VDD = 3.3 V
23
mA
MHz
nH
14.32
Lpin
7
5
CIN
Logic Inputs
pF
Input Capacitance1
Clk Stabilization1,2
COUT
CINX
Output pin capacitance
X1 & X2 pins
6
pF
27
45
pF
From PowerUp or deassertion of
PowerDown to 1st clock.
TSTAB
1.8
10
10
ms
ns
ns
tPZH,tPZL
Output enable delay (all outputs)
1
1
Delay1
t
PHZ,tPLZ
Output disable delay (all outputs)
1Guaranteed by design, not 100% tested in production.
2See timing diagrams for buffered and un-buffered timing requirements.
0641D—07/03/03
11
Integrated
Circuit
ICS950227
Systems, Inc.
Electrical Characteristics - CPU 0.7V Current Mode Differential Pair
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF
PARAMETER
SYMBOL
Zo1
CONDITIONS
VO = Vx
MIN
TYP
MAX
850
UNITS NOTES
Current Source Output
Impedance
3000
Ω
1
Statistical measurement on single
ended signal using oscilloscope
math function.
Voltage High
Voltage Low
VHigh
VLow
660
770
5
1
1
mV
-150
150
Measurement on single ended
signal using absolute value.
Max Voltage
Min Voltage
Crossing Voltage (abs)
Vovs
Vuds
Vcross(abs)
756
-7
350
1150
1
1
1
mV
mV
mV
-300
250
550
140
Variation of crossing over all
edges
see Tperiod min-max values
200MHz nominal
Crossing Voltage (var)
Long Accuracy
d-Vcross
ppm
12
1
-300
300
ppm
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
ps
ps
ps
1,2
2
2
2
2
2
2
2
2
1,2
1,2
1,2
1,2
1
4.9985
4.9985
5.9982
5.9982
7.4978
7.4978
9.9970
9.9970
4.8735
5.8732
7.3728
9.8720
175
5.0015
5.0266
6.0018
6.0320
7.5023
5.4000
10.0030
10.0533
200MHz spread
166.66MHz nominal
166.66MHz spread
133.33MHz nominal
133.33MHz spread
100.00MHz nominal
100.00MHz spread
Average period
Tperiod
200MHz nominal
166.66MHz nominal/spread
133.33MHz nominal/spread
100.00MHz nominal/spread
VOL = 0.175V, VOH = 0.525V
Tabsmin
Absolute min period
tr
tf
Rise Time
Fall Time
332
344
30
700
700
125
125
VOH = 0.525V VOL = 0.175V
175
1
d-tr
d-tf
Rise Time Variation
Fall Time Variation
1
30
1
Measurement from differential
wavefrom
dt3
tsk3
Duty Cycle
Skew
45
49
8
55
%
ps
ps
1
1
1
VT = 50%
100
150
Measurement from differential
wavefrom
1Guaranteed by design, not 100% tested in production.
2 All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref output is at
14.31818MHz
tjcyc-cyc
Jitter, Cycle to cycle
60
0641D—07/03/03
12
Integrated
Circuit
ICS950227
Systems, Inc.
Electrical Characteristics - 3V66 [5:0]
TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified)
PARAMETER
Output Frequency
Output Impedance
Output High Voltage
Output Low Voltage
SYMBOL
CONDITIONS
MIN
TYP MAX
UNITS
FO
66.66
MHz
Ω
1
VO = VDD*(0.5)
IOH = -1 mA
12
55
RDSP1
1
2.4
V
VOH
1
IOL = 1 mA
0.55
-33
V
VOL
V OH@MIN = 1.0 V,
-33
30
-110
-20
110
37
1
Output High Current
V
OH@MAX = 3.135 V
mA
IOH
VOL @MIN = 1.95 V,
VOL @MAX = 0.4 V
1
Output Low Current
Rise Time
Fall Time
Duty Cycle
Skew
38
2
mA
ns
ns
%
IOL
1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
0.5
0.5
45
1.8
1.3
tr1
1
2
tf1
1
dt1
51.2
136
241
55
250
250
1
tsk1
VT = 1.5 V
ps
ps
1
Jitter
tjcyc-cyc
VT = 1.5 V 3V66
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - PCICLK
TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified)
PARAMETER
Output Frequency
Output Impedance
Output High Voltage
Output Low Voltage
SYMBOL
CONDITIONS
MIN
TYP MAX
33.33
UNITS
FO
MHz
Ω
1
VO = VDD*(0.5)
IOH = -1 mA
12
55
RDSP1
1
2.4
3.28
V
VOH
1
IOL = 1 mA
0.08
-110
-20
0.55
-33
V
VOL
VOH@MIN = 1.0 V,
-33
30
1
Output High Current
V
OH@MAX = 3.135 V
OL@MIN = 1.95 V,
mA
IOH
V
110
37
1
Output Low Current
Rise Time
VOL @MAX = 0.4 V
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
38
2
mA
ns
ns
%
IOL
1
0.5
0.5
45
1.51
1.32
tr1
1
Fall Time
2
tf1
1
Duty Cycle
dt1
51.1
101
226
55
500
250
1
Skew
VT = 1.5 V
ps
ps
tsk1
1
Jitter,cycle to cyc
tjcyc-cyc
VT = 1.5 V
1Guaranteed by design, not 100% tested in production.
0641D—07/03/03
13
Integrated
Circuit
ICS950227
Systems, Inc.
Electrical Characteristics - VCH, 48MHz DOT, 48MHz, USB
TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
Output Frequency
Output Impedance
Output High Voltage
Output Low Voltage
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
FO
48.008
MHz
Ω
1
VO = VDD*(0.5)
IOH = -1 mA
20
60
RDSP1
1
2.4
3.27
V
VOH
1
IOL = 1 mA
0.4
V
VOL
V OH@MIN = 1.0 V,
-29
-61
-12
1
Output High Current
Output Low Current
V
OH@MAX = 3.135 V
-23
27
mA
mA
IOH
VOL @MIN = 1.95 V, VOL @MAX
0.4 V
=
1
29
IOL
1
48DOT Rise Time
48DOT Fall Time
VOL = 0.4 V, VOH = 2.4 V
0.5
0.5
1
0.84
0.92
1.74
1.84
53.2
52.5
151
1
1
ns
ns
ns
ns
%
tr1
1
VOH = 2.4 V, VOL = 0.4 V
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
tf1
1
VCH 48 USB Rise Time
VCH 48 USB Fall Time
48 DOT Duty Cycle
VCH 48 USB Duty Cycle
48 DOT Jitter
2
tr1
1
1
2
tf1
1
dt1
45
45
55
55
350
1
1
VT = 1.5 V
%
dt1
1
VT = 1.5 V
ps
ns
ps
tjcyc-cyc
1
USB to DOT Skew
VT = 1.5 V (0 OR 180 degrees)
0.53
187
tsk1
1
VCH Jitter
tjcyc-cyc
VT = 1.5 V
350
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - REF
TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
Output Frequency
Output Impedance
Output High Voltage
Output Low Voltage
SYMBOL
FO1
CONDITIONS
MIN
TYP
MAX
60
UNITS
14.318
MHz
Ω
1
VO = VDD*(0.5)
IOH = -1 mA
20
RDSP1
1
2.4
3.28
V
VOH
1
IOL = 1 mA
0.4
-33
V
VOL
V OH@MIN = 1.0 V
V OH@MAX = 3.135 V
VOL @MIN = 1.95 V
VOL @MAX = 0.4 V
-33
30
-110
-20
1
Output High Current
mA
IOH
110
37
1
Output Low Current
Rise Time
Fall Time
38
2
mA
ns
ns
%
IOL
1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
1
1
1.38
1.31
tr1
1
2
tf1
1
Duty Cycle
dt1
VT = 1.5 V
VT = 1.5 V
45
54.7
276
55
1000
1
Jitter
tjcyc-cyc
ps
1Guaranteed by design, not 100% tested in production.
0641D—07/03/03
14
Integrated
Circuit
ICS950227
Systems, Inc.
3V66 & PCI Phase Relationship
All3V66clocksaretobeinpphasewitheachother.Inthecasewhere3V66_1isconfiguredas48MHzVCHclock, thereisnodefined
phase relationship between 3V66_1/VCH and other 3V66 clocks.The PCI group should lag 3V66 by the standard skew described
below as Tpci.
3V66 (1:0)
3V66 (4:2)
3V66_5
Tpci
PCICLK_F (2:0) PCICLK (6:0)
Group Skews at Common Transition Edges
GROUP
3V66
SYMBOL
3V66
CONDITIONS
3V66 (5:0) pin to pin skew
PCI_F (2:0) and
MIN
0
TYP
136
MAX
250
UNITS
ps
PCI
PCI
0
101
500
3.5
ps
ns
PCI (6:0) pin to pin skew
3V66 (5:0) leads 33MHz PCI
S3V66-PCI
3V66 to PCI
1.5
2.08
1Guarenteed by design, not 100% tested in production.
PD# Functionality
PCICLK_F
PCICLK
USB/DOT
48MHz
CPU_STOP#
CPUT
CPUC
3V66
66MHz_OUT
PCICLK
1
0
Normal
Normal
Float
66MHz
Low
66MHz_IN
Low
66MHz_IN 66MHz_IN
Low Low
48MHz
Low
iref * Mult
0641D—07/03/03
15
Integrated
Circuit
ICS950227
Systems, Inc.
PCI_STOP# - Assertion (transition from logic "1" to logic "0")
The impact of asserting the PCI_STOP# signal will be the following. All PCI[6:0] and stoppable PCI_F[2,0] clocks will latch low
in their next high to low transition. The PCI_STOP# setup time tsu is 10 ns, for transitions to be recognized by the next rising
edge.
Assertion of PCI_STOP# Waveforms
PCI_STOP#
PCI_F[2:0] 33MHz
PCI[6:0] 33MHz
tsu
CPU_STOP# - Assertion (transition from logic "1" to logic "0")
The impact of asserting the CPU_STOP# pin is all CPU outputs that are set in the I2C configuration to be stoppable via assertion
of CPU_STOP# are to be stopped after their next transition following the two CPU clock edge sampling as shown.The final state
of the stopped CPU signals is CPUT=High and CPUC=Low. There is to be no change to the output drive current values. The
CPUT will be driven high with a current value equal to (MULTSEL0) X (I REF), the CPUC signal will not be driven.
Assertion of CPU_STOP# Waveforms
CPU_STOP#
CPUT
CPUC
CPU_STOP# Functionality
CPU_STOP#
CPUT
CPUC
1
0
Normal
Normal
Float
iref * Mult
0641D—07/03/03
16
Integrated
Circuit
ICS950227
Systems, Inc.
c
N
In Millimeters
In Inches
SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS
MIN
2.41
0.20
0.20
0.13
MAX
2.80
0.40
0.34
0.25
MIN
.095
.008
.008
.005
MAX
.110
.016
.0135
.010
L
A
A1
b
E1
E
INDEX
AREA
c
D
E
E1
e
h
L
SEE VARIATIONS
SEE VARIATIONS
10.03
7.40
10.68
7.60
.395
.291
.420
.299
1
2
0.635 BASIC
0.025 BASIC
α
hh xx 4455°°
0.38
0.50
0.64
1.02
.015
.020
.025
.040
D
N
α
SEE VARIATIONS
SEE VARIATIONS
0°
8°
0°
8°
A
VARIATIONS
D mm.
D (inch)
N
A1
MIN
18.31
MAX
18.55
MIN
.720
MAX
- CC --
56
.730
Reference Doc.: JEDEC Publication 95, MO-118
e
SEATING
PLANE
10-0034
b
.10 ((..000044)) CC
300 mil SSOP Package
Ordering Information
ICS950227yFT
Example:
ICS XXXXXX y F - T
Designation for tape and reel packaging
Package Type
F = SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
0641D—07/03/03
17
相关型号：
ICS950227YFLFT
Processor Specific Clock Generator, 133.33MHz, PDSO56, 0.300 INCH, MO-118, SSOP-56
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ICS950401YFLF-T
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