ICS950812YGLFT [ICSI]
Frequency Generator with 200MHz Differential CPU Clocks; 频率发生器，差分200MHz的CPU时钟
| 型号： | ICS950812YGLFT |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Frequency Generator with 200MHz Differential CPU Clocks |
| 文件： | 总29页 (文件大小：225K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS950812
Integrated
Circuit
Systems,Inc.
Frequency Generator with 200MHz Differential CPU Clocks
Recommended Application:
Pin Configuration
CK-408 clock with Buffered/Unbuffered mode supporting
Almador, Brookdale, ODEM, and Montara-G chipsets with
PIII/P4 processor. Programmable for group to group skew.
Output Features:
VDDREF
X1
X2
GND
PCICLK_F0
PCICLK_F1
1
2
3
4
5
56 REF
55 FS1
54 FS0
53 CPU_STOP#*
52 CPUCLKT0
•
•
•
•
•
•
•
•
3 Differential CPU Clock Pairs @ 3.3V
7 PCI (3.3V) @ 33.3MHz including 2 early PCI clocks
3 PCI_F (3.3V) @ 33.3MHz
CPUCLKC0
51
6
7
8
9
PCICLK_F2
VDDPCI
GND
50 VDDCPU
49 CPUCLKT1
48 CPUCLKC1
47 GND
46 VDDCPU
45 CPUCLKT2
44 CPUCLKC2
43 MULTSEL*
42 IREF
1 USB (3.3V) @ 48MHz, 1 DOT (3.3V) @ 48MHz
1 REF (3.3V) @ 14.318MHz
PCICLK0 10
**E_PCICLK1/PCICLK1 11
PCICLK2 12
**E_PCICLK3/PCICLK3 13
VDDPCI 14
5 3V66 (3.3V) @ 66.6MHz
1 VCH/3V66 (3.3V) @ 48MHz or 66.6MHz
3 66MHz_OUT/3V66 (3.3V) @ 66.6MHz_IN or 66.6MHz
GND 15
PCICLK4 16
PCICLK5 17
PCICLK6 18
VDD3V66 19
41 GND
40 FS2
39 48MHz_USB/FS3**
38 48MHz_DOT
37 VDD48
Features:
•
Provides standard frequencies and additional 5%
and 10% over-clocked frequencies
•
Supports spread spectrum modulation:
No spread, Center Spread (±0.35%, ±0.5%,
or ±0.75%), or Down Spread (-0.5%, -1.0%, or -1.5%)
GND 20
66MHZ_OUT0/3V66_2 21
66MHZ_OUT1/3V66_3 22
66MHZ_OUT2/3V66_4 23
66MHZ_IN/3V66_5 24
*PD# 25
36 GND
35 3V66_1/VCH_CLK/FS4**
34 PCI_STOP#*
33 3V66_0/FS5**
32 VDD3V66
31 GND
•
•
•
Offers adjustable PCI early clock via latch inputs
Selectable 1X or 2X strength for REF via I2C interface
VDDA 26
GND 27
Vtt_PWRGD# 28
Efficient power management scheme through PD#,
CPU_STOP# and PCI_STOP#.
30 SCLK
29 SDATA
•
•
Uses external 14.318MHz crystal
Stop clocks and functional control available through
56-Pin 300mil SSOP
6.10 mm. Body, 0.50 mm. pitch TSSOP
I2C interface.
Key Specifications:
*These inputs have 120K internal pull-up resistors to VDD.
**Internal pull-down resistors to ground.
•
•
•
•
CPU Output Jitter <150ps
3V66 Output Jitter <250ps
66MHz Output Jitter (Additive) (Buffered Mode) <100ps
CPU Output Skew <100ps
Note:
Almador board level designs MUST use pin 22,
66MHZ_OUT1, as the feedback connection from the
clock buffer path to the Almador (GMCH) chipset.
Block Diagram
48MHz_USB
48MHz_DOT
PLL2
Frequency Select
66MHz_OU
66MHz_IN PCICLK_F
X1
X2
XTAL
OSC
Bit
CPUCLK 3V66
T (2:0)
3V66 (4:2)
MHz
3V66_5/66MHz_IN
3V66_5
MHz
PCICLK
MHz
3V66_3/66MHz_OUT1
3V66_(4,2)/66MHz_OUT(2,0)
FS2 FS1 FS0
MHz
MHz
66.66
66.66
66.66
66.66
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
66.66
66.66
66.66
66.66
66.66
66.66
Input
Input
Input
Input
33.33
PLL1
Spread
Spectrum
REF
100.00
200.00
133.33
66.66
66.66
33.33
CPUCLKT (2:0)
CPUCLKC (2:0)
CPU
DIVDER
3
Stop
Stop
66.66
33.33
3
66.66
33.33
PCI
DIVDER
PD#
CPU_STOP#
PCI_STOP#
MULTSEL
FS (5:0)
7 PCICLK (6:4, 2, 0)
66.66 66MHz_IN
66.66 66MHz_IN
66.66 66MHz_IN
66.66 66MHz_IN
66MHz_IN/2
66MHz_IN/2
66MHz_IN/2
66MHz_IN/2
Control
Logic
2 E_PCICLK(1,3)/PCICLK(1,3)
3 PCICLK_F (2:0)
3V66
DIVDER
100.00
200.00
133.33
3V66_0
SDATA
Config.
Reg.
3V66_1/VCH_CLK
I REF
SCLK
TT_PWRGD#
V
0542G—08/21/03
ICS950812
Pin Configuration
PIN # PIN NAME
PIN TYPE
PWR
IN
DESCRIPTION
1
VDDREF
Ref, XTAL power supply, nominal 3.3V
Crystal input, Nominally 14.318MHz.
Crystal output, Nominally 14.318MHz
Ground pin.
2
X1
3
X2
OUT
PWR
OUT
OUT
OUT
PWR
PWR
OUT
I/O
4
GND
5
PCICLK_F0
PCICLK_F1
PCICLK_F2
VDDPCI
Free running PCI clock not affected by PCI_STOP# .
Free running PCI clock not affected by PCI_STOP# .
Free running PCI clock not affected by PCI_STOP# .
Power supply for PCI clocks, nominal 3.3V
Ground pin.
6
7
8
9
GND
10
11
12
13
14
15
16
17
18
19
20
21
22
23
PCICLK0
PCI clock output.
**E_PCICLK1/PCICLK1
PCICLK2
Early/Normal PCI clock output latched at power up.
PCI clock output.
OUT
I/O
**E_PCICLK3/PCICLK3
VDDPCI
Early/Normal PCI clock output latched at power up.
Power supply for PCI clocks, nominal 3.3V
Ground pin.
PWR
PWR
OUT
OUT
OUT
PWR
PWR
OUT
OUT
OUT
GND
PCICLK4
PCI clock output.
PCICLK5
PCI clock output.
PCICLK6
PCI clock output.
VDD3V66
Power pin for the 3V66 clocks.
Ground pin.
GND
66MHZ_OUT0/3V66_2
66MHZ_OUT1/3V66_3
66MHZ_OUT2/3V66_4
3.3V 66.66MHz clock output selected via buffered or internal VCO.
3.3V 66.66MHz clock output selected via buffered or internal VCO.
3.3V 66.66MHz clock output selected via buffered or internal VCO.
3.3V 66.66MHz clock from internal VCO, 66MHZ input to 66MHz output and
PCI.
24
66MHZ_IN/3V66_5
I/O
Asynchronous active low input pin used to power down the device into a low
power state. The internal clocks are disabled and the VCO and the crystal
are stopped. The latency of the power down will not be greater than 1.8ms.
25
*PD#
IN
26
27
VDDA
GND
PWR
PWR
3.3V power for the PLL core.
Ground pin.
This 3.3V LVTTL input is a level sensitive strobe used to determine when
latch inputs are valid and are ready to be sampled. This is an active low
input.
28
Vtt_PWRGD#
IN
0542G—08/21/03
2
ICS950812
Pin Configuration (Continued)
PIN # PIN NAME
PIN TYPE
I/O
DESCRIPTION
29
30
31
32
33
SDATA
Data pin for I2C circuitry 5V tolerant
Clock pin of I2C circuitry 5V tolerant
Ground pin.
SCLK
IN
GND
PWR
PWR
I/O
VDD3V66
3V66_0/FS5**
Power pin for the 3V66 clocks.
Frequency select latch input pin / 3.3V 66.66MHz clock output.
Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level, when input
low
Frequency select latch input pin / 3.3V 66.66MHz clock output / 48MHz
VCH clock output.
Ground pin.
34
35
PCI_STOP#*
IN
3V66_1/VCH_CLK/FS4**
I/O
36
37
38
39
40
41
GND
PWR
PWR
OUT
I/O
VDD48
Power pin for the 48MHz output.3.3V
48MHz clock output.
48MHz_DOT
48MHz_USB/FS3**
FS2
Frequency select latch input pin / 3.3V 48MHz clock output.
Frequency select pin.
IN
GND
PWR
Ground pin.
This pin establishes the reference current for the differential current-mode
output pairs. This pin requires a fixed precision resistor tied to ground in
order to establish the appropriate current. 475 ohms is the standard value.
42
IREF
OUT
43
44
MULTSEL*
CPUCLKC2
IN
3.3V LVTTL input for selection the current multiplier for CPU outputs
Complimentary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
Supply for CPU clocks, 3.3V nominal
OUT
45
CPUCLKT2
OUT
46
47
VDDCPU
GND
PWR
PWR
Ground pin.
Complimentary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
Supply for CPU clocks, 3.3V nominal
Complimentary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
Stops all CPUCLK besides the free running clocks
48
CPUCLKC1
OUT
49
50
51
CPUCLKT1
VDDCPU
OUT
PWR
OUT
CPUCLKC0
52
CPUCLKT0
OUT
53
54
55
56
CPU_STOP#*
FS0
IN
IN
Frequency select pin.
FS1
IN
Frequency select pin.
REF
OUT
14.318 MHz reference clock.
0542G—08/21/03
3
ICS950812
Frequency Select Table 1
66MHz_OU
T (2:0)
Freq Sel
66MHz_IN
3V66 _5
USB/DOT
MHz
CPU MHz
3V66 MHz
PCI MHz
REF MHz
Clocking Mode
FS FS FS
FS(5:3)
3V66 (4:2)
2
1
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
66.66
100.00
200.00
133.33
66.66
66.66
66.66
66.66
66.66
66.66
66.66
66.66
66.66
70.00
70.00
Tristate
70.00
70.00
70.00
Tristate
70.00
73.32
73.32
Test/4
73.32
73.32
73.32
Test/4
66.66
66.66
66.66
66.66
66.66
66.66
66.66
Input
33.33
33.33
33.33
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
Tristate
14.318
14.318
14.318
Tristate
14.318
14.318
14.318
Test
48.008
48.008
48.008
48.008
48.008
48.008
48.008
48.008
48.008
48.008
Tristate
48.008
48.008
48.008
Tristate
48.008
48.008
48.008
Test/2
48.008
48.008
48.008
Test/2
Standard Clocking
Standard Clocking
From
000
to
66.66
33.33
66MHz_IN
66MHz_IN
66MHz_IN
66MHz_IN
70.00
70.00
Tristate
70.00
66MHz_IN
66MHz_IN
Tristate
66MHz_IN
73.32
73.32
Test/4
73.32
66MHz_IN
66MHz_IN
Test/4
66MHz_IN/2
66MHz_IN/2
66MHz_IN/2
66MHz_IN/2
35.00
35.00
Tristate
35.00
66MHz_IN/2
66MHz_IN/2
Tristate
66MHz_IN/2
36.66
36.66
Test/8
36.66
101
(See table 2)
100.00
200.00
133.33
70.00
105.00
Tristate
140.00
70.00
105.00
Tristate
140.00
73.32
110.00
Test/2
146.60
73.32
Input
Input
Input
70.00
70.00
Tristate
70.00
Input
Input
Tristate
Input
73.32
73.32
Test/4
73.32
Input
5% Overclocking
Tristate
110
(See table 2)
5% Overclocking
Tristate
5% Overclocking
10% Overclocking
Test
14.318
14.318
14.318
Test
111
(See table 2)
66MHz_IN/2
66MHz_IN/2
Test/8
10% Overclocking
110.00
Test/2
Input
Test/4
Test
1
1
1
146.60
73.32
66MHz_IN
Input
66MHz_IN/2
14.318
48.008
10% Overclocking
Frequency Select Table 2
Freq Sel
CPU, 3V66, 66MHz_OUT,
Clocking Mode
FS FS FS
66MHz_IN, PCI
5
4
3
No Spread (default)
or +/-0.4%
0
0
0
Standard Clocking
Standard Clocking
Standard Clocking
Standard Clocking
Standard Clocking
Standard Clocking
5% Overclocking
10% Overclocking
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0 to -0.5%, Down Spread
0 to -1.0%, Down Spread
0 to -1.5%, Down Spread
+/-0.5%, Center Spread
+/-0.75%, Center Spread
+/-0.35%, Center Spread
+/-0.35%, Center Spread
Note: To enable spread, Byte 0 Bit 7 must be set to 1.
0542G—08/21/03
4
ICS950812
Maximum Allowed Current
Max 3.3V supply consumption
Max discrete cap loads,
Vdd = 3.465V
Condition
All static inputs = Vdd or GND
Powerdown Mode
(PD# = 0)
40mA
Active Full
280mA
Host Swing Select Functions
Reference R,
Board Target
MULTSEL
Output
Current
Voh @ Z
Trace/Term Z
Iref = VDD/3*Rr
Rr = 221 1%,
Iref = 5.00mA
0
1
50 ohms
50 ohms
Ioh = 4 * I REF
Ioh = 6 * I REF
1.0V @ 50 ohm
0.7V @ 50 ohm
Rr = 475 1%,
Iref = 2.32mA
PCI Select Functions
E_PCICLK(3,1)*
E_PCICLK1 (11)
E_PCICLK3 (13)
0
0
1
1
0
1
0
1
0ns
0.5ns
1.0ns
1.5ns
Note:
E_PCICLK1 = 10Kohm resistor.
E_PCICLK3 = 10Kohm resistor.
0 = No resistor
1 = 10Kohm pull-up to VDD
.
*
Approximate values
0542G—08/21/03
5
ICS950812
BYTE
0
Affected Pin
Name
Bit Control
Control Function
Type
RW
Pin #
-
0
1
PWD
0
Bit 7
Spread Enabled
Spread Spectrum Control
Power down mode output level
0= CPU driven in power down
1= undriven
OFF
ON
Bit 6
-
CPUCLKT(2:0)
RW
HIGH
LOW
0
Bit 5
Bit 4
35
53
3V66_1/VCH_CLK/FS4**
CPU_STOP#*
VCH/66.66 Select
Reflects value of pin
RW
R
66.66
Stop
48.00
Active
0
X
Reflects value of pin at power up.
Also can be set.
Bit 3
34
PCI_STOP#*
RW
Stop
Active
X
Bit 2
Bit 1
Bit 0
39
55
54
FS3
FS1
FS0
Frequency Selection
Frequency Selection
Frequency Selection
RW
R
R
-
-
-
-
-
-
X
X
X
Note: For PCI_STOP# function, refer to table 3.
BYTE
1
Affected Pin
Name
Bit Control
Control Function
Type
R
Pin #
43
0
-
1
-
PWD
x
Bit 7
MULTSEL*
Reflects value of pin
CPU_Stop mode output level
0= CPU driven when stopped
1 = undriven
Bit 6
-
CPUCLKT(2:0)
RW
HIGH
LOW
0
CPUCLKT2, CPUCLKC2
(see note)
CPUCLKT1, CPUCLKC1
(see note)
CPUCLKT0, CPUCLKC0
(see note)
CPUCLKT2, CPUCLKC2
CPUCLKT1, CPUCLKC1
CPUCLKT0, CPUCLKC0
Allow control of output with
assertion of CPU_STOP#.
Allow control of output with
assertion of CPU_STOP#.
Allow control of output with
assertion of CPU_STOP#.
Output control
Not
Freerun
Not
Freerun
Not
Bit 5
Bit 4
Bit 3
45, 44
49, 48
52, 51
RW
RW
RW
Freerun
Freerun
Freerun
0
0
0
Freerun
Bit 2
Bit 1
Bit 0
45, 44
49, 48
52, 51
RW
RW
RW
Disable Enable
Disable Enable
Disable Enable
1
1
1
Output control
Output control
Note: CPUCLK(2:0) can be turned on/off by CPU_STOP#. Refer to table 4.
BYTE
2
Affected Pin
Name
Bit Control
Control Function
Type
Pin #
56
18
17
16
13
12
11
10
0
1
PWD
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
REF
PCICLK6
PCICLK5
1X or 2X Strength control
Output control
Output control
Output control
Output control
Output control
Output control
Output control
RW
RW
RW
RW
RW
RW
RW
RW
1X
2X
0
1
1
1
1
1
1
1
Disable Enable
Disable Enable
Disable Enable
Disable Enable
Disable Enable
Disable Enable
Disable Enable
PCICLK4
**E_PCICLK3/PCICLK3
PCICLK2
**E_PCICLK1/PCICLK1
PCICLK0
Note: PCICLK(6:0) can be turned on/off by PCI_STOP#. Refer to table 3.
BYTE
3
Affected Pin
Name
48MHz_DOT
48MHz_USB/FS3**
Bit Control
Control Function
Type
Pin #
38
39
0
1
PWD
1
1
Bit 7
Bit 6
Output control
Output control
RW
RW
Disable Enable
Disable Enable
Allow control of output with
assertion of PCI_STOP#.
Allow control of output with
assertion of PCI_STOP#.
Allow control of output with
assertion of PCI_STOP#.
Output control
Not
Freerun
Not
Freerun
Not
Freerun
Bit 5
Bit 4
Bit 3
7
6
5
PCICLK_F2 (see note)
PCICLK_F1 (see note)
PCICLK_F0 (see note)
RW
RW
RW
Freerun
0
0
0
Freerun
Freerun
Bit 2
Bit 1
Bit 0
7
6
5
PCICLK_F2
PCICLK_F1
PCICLK_F0
RW
RW
RW
Disable Enable
Disable Enable
Disable Enable
1
1
1
Output control
Output control
Note: PCICLK_F(2:0) can be turned on/off by PCI_STOP#. Refer to table 5.
0542G—08/21/03
6
ICS950812
BYTE
4
Affected Pin
Name
Bit Control
Control Function
Type
Pin #
35
33
33
35
24
23
22
21
0
1
PWD
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
FS4
FS5
3V66_0/FS5**
Frequency Selection
Frequency Selection
Output control
RW
RW
RW
RW
RW
RW
RW
RW
Disable Enable
Disable Enable
Disable Enable
Disable Enable
Disable Enable
Disable Enable
Disable Enable
Disable Enable
X
X
1
1
1
1
1
1
3V66_1/VCH_CLK/FS4**
66MHZ_IN/3V66_5
66MHZ_OUT2/3V66_4
66MHZ_OUT1/3V66_3
66MHZ_OUT0/3V66_2
Output control
Output control
Output control
Output control
Output control
BYTE
5
Affected Pin
Bit Control
Control Function
Type
Pin #
X
X
Name
-
-
0
-
1
-
PWD
0
0
Bit 7
Bit 6
Unused
Reserved
-
X
-
-
3V66(5:2)/66MHZ_OUT(2:0)
(See table 6)
Allow control of output with
assertion of CPU_STOP#.
Allow control of output with
assertion of CPU_STOP#.
00 = Medium (default), 01 = Low,
11,10 =High
Not
Freerun
Not
Freerun
Bit 5
Bit 4
X
X
X
X
Freerun
Freerun
0
0
3V66(1:0) (See table 7)
Bit 3
Bit 2
Bit 1
RW
RW
RW
-
-
-
-
-
-
0
0
0
38
48MHz_DOT Slew Control
00 = Medium (default), 01 = Low,
11,10 =High
39
48MHz_USB Slew Control
Bit 0
RW
-
-
0
Functions in Byte 5 of CK408 were intended as a test and debug byte only.
Note:
BYTE
6
Affected Pin
Bit Control
Control Function
Type
Pin #
X
X
X
X
X
X
X
X
Name
0
-
-
-
-
-
-
-
-
1
-
-
-
-
-
-
-
-
PWD
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Revision ID Bit 3
Revision ID Bit 2
Revision ID Bit 1
Revision ID Bit 0
Vendor ID Bit 3
Vendor ID Bit 2
Vendor ID Bit 1
Vendor ID Bit 0
R
R
R
R
R
R
R
R
X
X
X
X
0
0
0
1
Revision ID Value Based on
Device Revision
(Reserved)
(Reserved)
(Reserved)
(Reserved)
BYTE
7
Affected Pin
Bit Control
Control Function
Type
Pin #
X
X
X
X
X
X
X
X
Name
0
-
-
-
-
-
-
-
-
1
-
-
-
-
-
-
-
-
PWD
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
BYTE
8
Affected Pin
Bit Control
Control Function
(Reserved)
Type
X
Pin #
X
Name
-
0
-
1
-
PWD
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
X
X
X
X
X
-
-
-
-
-
(Reserved)
(Reserved)
(Reserved)
X
X
X
R
R
-
-
-
-
-
-
-
-
-
-
0
0
0
1
1
Readback Byte Count
Bit 1
Bit 0
X
X
-
-
R
R
-
-
-
-
1
1
Note: Byte 8 is for ICS test only. Do not write as system damage may occur. Bit(3:0) contain the readback Byte count.
0542G—08/21/03
7
ICS950812
BYTE
9
Affected Pin
Name
Bit Control
Control Function
Type
Pin #
35
0
1
-
PWD
Bit 7
Bit 6
Bit 5
00 = High(default), 01 = Low,
11,10 = Medium
RW
RW
RW
-
-
-
0
0
0
VCHCLK Slew Control
-
-
00 (default), 11 = Medium
01 = Low, 10 =High
7, 6, 5
PCICLK_F (2:0) Slew Contol
PCICLK (3:0) Slew Contol
PCICLK (6:0) Slew Contol
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RW
RW
RW
RW
RW
-
-
-
-
-
-
-
-
-
-
0
0
0
0
0
13, 12,
11, 10
00 (default), 11 = Medium
10 = Low, 01 =High
00 (default), 11 = Medium
10 = Low, 01 =High
18, 17, 16,
13 , 12 , 11, 10
BYTE
10
Affected Pin
Name
Bit Control
Control Function
Type
RW
Pin #
X
0
1
PWD
0
M/N Enable (Enable access to
Byte 11 - 14)
Byte
(11-14)
Bit 7
-
-
HW/B0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
X
Unused
-
-
-
-
-
-
-
-
-
-
-
-
-
0
0
0
0
0
0
24, 23, 3V66(5:2)/66MHZ_OUT(2:0)
RW
RW
RW
RW
-
Approx 250ps per bit (Ref to PCI)
22, 21
Skew
33, 35
3V66(1:0) Skew
Approx 250ps per bit (Ref to PCI)
X
X
-
-
Unused
Unused
Bit 0
-
-
-
0
BYTE
11
Bit 7
Affected Pin
Bit Control
Control Function
VCO Divider Bit8
Type
RW
Pin #
X
Name
-
0
-
1
-
PWD
X
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
X
X
X
X
X
X
-
-
-
-
-
-
-
REF Divider Bit6
REF Divider Bit5
REF Divider Bit4
REF Divider Bit3
REF Divider Bit2
REF Divider Bit1
REF Divider Bit0
RW
RW
RW
RW
RW
RW
RW
-
-
-
-
-
-
-
-
-
-
-
-
-
-
X
X
X
X
X
X
X
Note: The decimal representation of these 7 bits (Byte 11 bit[6:0]) + 2 is equal to the REF divider value.
Note: See table 8 for Byte 11-14 default information
BYTE
12
Affected Pin
Name
Bit Control
Control Function
VCO Divider Bit7
Type
RW
Pin #
X
0
-
1
-
PWD
X
Bit 7
-
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
X
X
X
X
X
X
-
-
-
-
-
-
-
VCO Divider Bit6
VCO Divider Bit5
VCO Divider Bit4
VCO Divider Bit3
VCO Divider Bit2
VCO Divider Bit1
VCO Divider Bit0
RW
RW
RW
RW
RW
RW
RW
-
-
-
-
-
-
-
-
-
-
-
-
-
-
X
X
X
X
X
X
X
Note: The decimal representation of these 9 bits (Byte 12 bit[7:0]) and Byte 11 bit [7]) + 8 is equal to the VCO divider value.
Note: See table 8 for Byte 11-14 default information
0542G—08/21/03
8
ICS950812
BYTE
13
Affected Pin
Name
Bit Control
Control Function
Type
RW
Pin #
X
0
1
-
PWD
X
Bit 7
-
Spread Spectrum Bit7
-
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
X
X
X
X
X
X
-
-
-
-
-
-
-
Spread Spectrum Bit6
Spread Spectrum Bit5
Spread Spectrum Bit4
Spread Spectrum Bit3
Spread Spectrum Bit2
Spread Spectrum Bit1
Spread Spectrum Bit0
RW
RW
RW
RW
RW
RW
RW
-
-
-
-
-
-
-
-
-
-
-
-
-
-
X
X
X
X
X
X
X
Note: Please utilize software utility provided by ICS Application Engineering to configure spread spectrum. Incorrect spread
percentage may cause system failure.
Note: See table 8 for Byte 11-14 default information
BYTE
14
Affected Pin
Name
Bit Control
Control Function
(Reserved)
Type
RW
Pin #
X
0
1
-
PWD
X
Bit 7
-
-
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
X
X
X
X
X
X
-
-
-
-
-
-
-
(Reserved)
RW
RW
RW
RW
RW
RW
RW
-
-
-
-
-
-
-
-
-
-
-
-
-
-
X
X
X
X
X
X
X
Spread Spectrum Bit13
Spread Spectrum Bit12
Spread Spectrum Bit11
Spread Spectrum Bit10
Spread Spectrum Bit9
Spread Spectrum Bit8
Note: Please utilize software utility provided by ICS Application Engineering to configure spread spectrum. Incorrect spread
percentage may cause system failure.
Note: See table 8 for Byte 11-14 default information
Spread Spectrum Enable Procedure
Step 1: Power-up ---- Latched inputs, FS(5:0), set frequency per Hardware default on board. SS is off.
BIOS program set IIC Byte0, bit7 to 1, SS will be enable Spread. Note that Byte 10,
bit 7 is default to 0. This allows all setup to be controlled by the Frequency Select
Tables, 1 and 2.
Step 2: After power up, SS% can be changed to the fixed selections shown in Frequency Table 2. This
is achieved by Writing to Byte 4, bit 6/7 (FS5:4) and/or Byte 0 (FS3), The data written
to these bytes will overwrite the existing contents and switch to the desired selection.
Step 3: To set up Linear programming and SS% adjust using Byte 11 through 14, the BIOS must set
Byte 10, bit 7 to a 1. This will enable access to Byte 11 and 12, M/N linear programming
and Byte 13 and 14, Spread Spectrum % adjust.
0542G—08/21/03
9
ICS950812
Table 3
PCI_STOP# I2C Control Table-Byte 0, Bit 3
PCI_STOP#
(Pin 34)
Byte 0 Bit 3
Write Bit
Byte 0, Bit 3 Read Bit
(Internal Status)
0
0
1
1
0
1
0
1
0
0
0
1`
When this Byte 0, Bit 3 is low (0), all PCI clocks are stopped.
Note:
Table 4
CPUCLKT/C (2:0) Outputs I2C Control Table
CPU_STOP#
Byte 1
Bit 3, 4, 5
CPUCLKT/C (2:0) Outputs
(Pin 53)
0
0
1
1
0
1
0
1
Stop
Running
Running
Running
Individual CPUCLK outputs are controlled by Byte 1, Bit 3, 4, and 5.
Note:
Table 5
PCICLK_F (2:0) Outputs I2C Control Table
PCI_STOP#
(Pin 34)
Byte 3
Bit 3, 4, 5
PCICLK (2:0) Outputs
0
0
Stop
0
1
1
1
0
1
Running
Running
Running
Individual PCICLK outputs are controlled by Byte 3, Bit 3, 4, and 5.
Note:
Table 6
3V66 (5:2)/66MHz_OUT(2:0)/66MHz_IN I2C Control Table
CPU_STOP#
(Pin 53)
Byte 5
Bit 5
3V66 (5:2) (Driven)
66MHZ_OUT(2:0)/66MHZ_IN (Buffered)
0
0
1
1
0
1
0
1
Running
Stopped
Running
Running
Activating Byte 5, Bit 5 will allow CPU_STOP# to control stop of pins 21, 22, 23, and 24.
Note:
0542G—08/21/03
10
ICS950812
Table 7
3V66 (0:1) I2C Control Table
CPU_STOP#
Byte 5
Bit 4
3V66 (1:0)
(Pin 53)
0
0
1
1
0
1
0
1
Running
Stopped
Running
Running
Activating Byte 5, Bit 4 will allow CPU_STOP# to control stop of pins 33 and 35.
Note:
Table 8: Byte 11-14 Defaults
Bytes
ADDRESS
CPU
Freq
Spread
Center
I2C read back values in Hex.
I2C read back values in binary.
12 13 14
11
12
13
14
11
FS5 FS4 FS3 FS1 FS0
Down
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
66.66 Center
99.99 Center
199.98 Center
133.32 Center
0.40%
0.40%
0.40%
0.40%
-0.48%
-0.48%
-0.48%
-0.48%
-0.98%
-0.98%
-0.98%
-0.98%
-1.52%
-1.52%
-1.52%
-1.52%
0.51%
0.51%
0.51%
0.51%
0.74%
0.74%
0.74%
0.74%
0.35%
0.35%
0.35%
0.35%
0.34%
0.34%
0.34%
0.34%
8D
8D
8D
8D
8D
8D
8D
8D
8D
8D
8D
8D
90
9B
9B
9B
9B
9A
9A
9A
9A
99
02
02
02
02
EF
EF
EF
EF
E7
E7
E7
E7
DD
DD
DD
DD
05
05
05
05
0B
0B
0B
0B
35
35
35
35
68
68
68
68
18
18
18
18
17
17
17
17
17
17
17
17
17
17
17
17
18
18
18
18
18
18
18
18
19
19
19
19
1A
1A
1A
1A
10001101 10011011 00000010 00011000
10001101 10011011 00000010 00011000
10001101 10011011 00000010 00011000
10001101 10011011 00000010 00011000
10001101 10011010 11101111 00010111
10001101 10011010 11101111 00010111
10001101 10011010 11101111 00010111
10001101 10011010 11101111 00010111
10001101 10011001 11100111 00010111
10001101 10011001 11100111 00010111
10001101 10011001 11100111 00010111
10001101 10011001 11100111 00010111
10010000 11101011 11011101 00010111
10010000 11101011 11011101 00010111
10010000 11101011 11011101 00010111
10010000 11101011 11011101 00010111
10001101 10011011 00000101 00011000
10001101 10011011 00000101 00011000
10001101 10011011 00000101 00011000
10001101 10011011 00000101 00011000
10001101 10011011 00001011 00011000
10001101 10011011 00001011 00011000
10001101 10011011 00001011 00011000
10001101 10011011 00001011 00011000
10001101 10110000 00110101 00011001
10001101 10110000 00110101 00011001
10001101 10110000 00110101 00011001
10001101 10110000 00110101 00011001
10001001 01001010 01101000 00011010
10001001 01001010 01101000 00011010
10001001 01001010 01101000 00011010
10001001 01001010 01101000 00011010
1
2
3
4
66.50
99.75
199.50
133.00
66.34
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
5
6
7
8
9
99.51
99
99
99
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
199.02
132.68
66.16
99.23
198.47
132.31
EB
EB
EB
EB
9B
9B
9B
9B
9B
9B
9B
9B
B0
B0
B0
B0
4A
4A
4A
4A
90
90
90
66.66 Center
99.99 Center
199.98 Center
133.32 Center
66.66 Center
99.99 Center
199.98 Center
133.32 Center
70.00 Center
105.00 Center
210.00 Center
140.00 Center
73.33 Center
109.99 Center
219.98 Center
146.65 Center
8D
8D
8D
8D
8D
8D
8D
8D
8D
8D
8D
8D
89
89
89
89
0542G—08/21/03
11
ICS950812
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . 0°C to +90°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . 115°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device.These ratings
are stress specifications only and functional operation of the device at these or any other conditions above those listed
in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 90°C; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN
2
TYP MAX
UNITS
V
V
DD+0.
3
Input High Voltage
VIH
VSS
-
Input Low Voltage
Input High Current
VIL
IIH
0.8
V
0.3
VIN = VDD; Inputs with no pull-down
resistors
5.75
200
mA
µA
VIN = VDD; Inputs with pull-down
resistors
IIH
VIN = 0 V; Inputs with no pull-up
resistors
IIL1
-5.75
-200
mA
µA
Input Low Current
VIN = 0 V; Inputs with pull-up
resistors
IIL2
IDD3.3OP
IDD3.3OP
CL = Full load; Select @ 100 MHz
233
234
280
280
mA
mA
Operating Supply Current
Powerdown Current
CL =Full load; Select @ 133 MHz
IREF=5 mA
IDD3.3PD
IDD3.3PDHIz
Fi
20
52
mA
mA
MHz
nH
0.289
14.32
0.5
Input Frequency
Pin Inductance
VDD = 3.3 V
Lpin
7
5
CIN
Logic Inputs
pF
Input Capacitance1
COUT
CINX
Output pin capacitance
6
pF
X1 & X2 pins
27
30
1
45
pF
From PowerUp or deassertion of
PowerDown to 1st clock.
Output enable delay (all outputs)
Output disable delay (all outputs)
Clk Stabilization1,2
Delay1
TSTAB
2.1
ms
tPZH,tPZL
1
1
12
12
ns
ns
t
PHZ,tPLZ
1Guaranteed by design, not 100% tested in production.
2See timing diagrams for buffered and un-buffered timing requirements.
0542G—08/21/03
12
ICS950812
Electrical Characteristics - CPU (1V Select) 100MHz
TA = 0 - 90°C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
Current Source Output
Impedance
SYMBOL
Zo1
CONDITIONS
MIN
TYP MAX UNITS
VO = Vx
Fig. 5
2500
Ω
Average Period
TPERIOD
VOH3
VOL3
tr3
10.00 10.01 10.20
ns
V
Output High Voltage
Output Low Voltage
Rise Time
0.92
-0.2
175
175
45
1.45
0.35
540
540
55
Measured from Single Ended Waveform
VOL = 0.41V, VOH = 0.86V (Fig. 6)
390
305
51
ps
ps
%
Fall Time
tf3
VOH = 0.86V VOL = 0.41V (Fig.6)
Duty Cycle
dt3
Fig. 5
Skew
tsk3
VT = 50%
VT = 50%
10
100
175
ps
ps
1
Jitter, Cycle to cycle
40
tjcyc-cyc
1Guaranteed by design, not 100% tested in production.
2 IOWT can be varied and is selectable thru the MULTSEL pin.
Electrical Characteristics - CPU (0.7V Select) 100MHz
TA = 0 - 90°C; VDD=3.3V +/-5%; (unless otherwise specified)
PARAMETER
Current Source Output
Impedance
SYMBOL
Zo1
CONDITIONS
MIN
3000
10.00 10.01 10.20
TYP MAX UNITS
VO = Vx
Ω
Average Period
Voltage High
Voltage Low
Max Voltage
Min Voltage
TPERIOD
VHigh
VLow
Vovs
Fig. 1
ns
Statistical measurement on single ended signal
using oscilloscope math function.
Measurement on single ended signal using
absolute value.
660
-150
720
15
850
150
mV
750
-2
319
12
1150
mV
Vuds
-450
250
Crossing Voltage (abs) Vcross(abs)
Crossing Voltage (var)
Rise Time
Fig. 3
550
140
810
mV
mV
ps
d-Vcross
Variation of crossing over all edges (Fig. 4)
VOL = 0.175V, VOH = 0.525V (Fig. 3)
tr
175
175
310
Fall Time
tf
VOH = 0.525V VOL = 0.175V (Fig. 3)
300
10
10
51
16
48
810
125
125
55
ps
ps
ps
%
Rise Time Variation
Fall Time Variation
Duty Cycle
d-tr
d-tf
dt3
tsk3
Measurement from differential wavefrom (Fig 1)
VT = 50%
45
Skew
100
175
ps
ps
1
Jitter, Cycle to cycle
tjcyc-cyc
VT = 50% (Fig. 1)
1Guaranteed by design, not 100% tested in production.
2 IOWT can be varied and is selectable thru the MULTSEL pin.
0542G—08/21/03
13
ICS950812
Electrical Characteristics - CPU (0.7V Select) 133.33MHz
TA = 0 - 90°C; VDD=3.3V +/-5%; (unless otherwise specified)
PARAMETER
Current Source Output
Impedance
SYMBOL
Zo1
CONDITIONS
MIN
TYP MAX UNITS
VO = Vx
3000
Ω
Average Period
Voltage High
Voltage Low
Max Voltage
Min Voltage
TPERIOD
VHigh
VLow
Vovs
Fig. 1
7.50
660
-150
7.51
718
17
730
7
7.65
850
150
ns
Statistical measurement on single ended signal
using oscilloscope math function.
Measurement on single ended signal using
absolute value.
mV
1150
mV
Vuds
-450
250
Crossing Voltage (abs) Vcross(abs)
Crossing Voltage (var)
Fig. 3
340
15
550
140
mV
mV
d-Vcross
Variation of crossing over all edges (Fig. 4)
Rise Time
tr
VOL = 0.175V, VOH = 0.525V (Fig. 3)
VOH = 0.525V VOL = 0.175V (Fig. 3)
175
175
310
315
810
810
ps
ps
Fall Time
tf
Rise Time Variation
Fall Time Variation
d-tr
d-tf
5
5
125
125
ps
ps
Duty Cycle
dt3
Measurement from differential wavefrom (Fig 1)
45
51
55
%
Skew
tsk3
VT = 50%
14
75
100
175
ps
ps
1
Jitter, Cycle to cycle
tjcyc-cyc
VT = 50% (Fig. 1)
1Guaranteed by design, not 100% tested in production.
2 IOWT can be varied and is selectable thru the MULTSEL pin.
Electrical Characteristics - PCICLK Buffered Mode
TA = 0 - 90°C; VDD = 3.3V +/-5%; CL = 10-30 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
VO = VDD*(0.5)
MIN
TYP MAX UNITS
1
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
12
33
65
Ω
V
RDSP1
1
IOH = -1 mA
2.05
VOH
1
IOL = 1 mA
0.65
-28
38
V
VOL
1
VOH@MIN = 1.0V, VOH@MAX = 3.135V
VOL @MIN = 1.95V, VOL @MAX = 0.4V
-33
26
mA
mA
ns
ns
%
IOH
1
IOL
1
Rise Time
Fall Time
tr1
VOL = 0.4 V, VOH = 2.4 V (Fig. 7)
VOH = 2.4 V, VOL = 0.4 V (Fig. 7)
VT = 1.5 V
0.5
0.5
45
1.4
1.2
52
2.3
2.3
55
1
tf1
1
Duty Cycle
Skew
dt1
1
VT = 1.5 V
35
500
120
ps
ps
tsk1
1
Jitter,cycle to cyc
tjcyc-cyc
VT = 1.5 V (Additive) (Fig. 8)
60
1Guaranteed by design, not 100% tested in production.
0542G—08/21/03
14
ICS950812
Electrical Characteristics - PCICLK Un-Buffered Mode
TA = 0 - 90°C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified)
PARAMETER
Output Impedance
Average Period
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
CONDITIONS
VO = VDD*(0.5)
MIN
12
TYP MAX UNITS
1
33
65
Ω
ns
V
RDSP1
TPERIOD
Fig. 8
30.00 30.01
2.05
1
IOH = -1 mA
VOH
1
IOL = 1 mA
0.65
-28
38
V
VOL
1
VOH@MIN = 1.0V, VOH@MAX = 3.135V
VOL @MIN = 1.95 V, VOL @MAX = 0.4 V
VOL = 0.4 V, VOH = 2.4 V (Fig. 7)
VOH = 2.4 V, VOL = 0.4 V (Fig. 7)
VT = 1.5 V (Fig. 8)
-33
26
mA
mA
ns
ns
%
IOH
1
IOL
1
0.5
0.5
45
1.4
1.2
50
2.3
2.3
55
tr1
1
Fall Time
tf1
1
Duty Cycle
dt1
1
Skew
VT = 1.5 V
65
500
290
ps
ps
tsk1
1
Jitter,cycle to cyc
tjcyc-cyc
VT = 1.5 V (Fig. 8)
101
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics- 3V66 - Buffered Mode: 3V66 [1:0] 66MHz_OUT [2:0]
TA = 0 - 90°C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified)
PARAMETER
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
CONDITIONS
VO = VDD*(0.5)
MIN
12
TYP MAX UNITS
1
33
65
Ω
V
RDSP1
1
IOH = -1 mA
2.05
VOH
1
IOL = 1 mA
0.65
-28
38
V
VOL
1
V
OH@MIN = 1.0 V, V OH@MAX = 3.135 V
-33
26
mA
mA
ns
ns
%
IOH
1
VOL @MIN = 1.95 V, VOL @MAX = 0.4 V
VOL = 0.4 V, VOH = 2.4 V (Fig. 7)
VOH = 2.4 V, VOL = 0.4 V (Fig. 7)
VT = 1.5 V (Fig. 8)
IOL
1
0.5
0.5
45
1.6
1
2.3
2.3
55
tr1
1
Fall Time
tf1
1
Duty Cycle
Skew
dt1
52
10
1
tsk1
VT = 1.5 V 3V66 [1:0]
250
ps
1
Jitter
VT = 1.5 V 3V66 [1:0] (Additive) (Fig. 8)
VT = 1.5 V 66MHz_OUT [2:0]
83
120
250
ps
ps
tjcyc-cyc
1
Skew
169
tsk1
VT = 1.5V 66MHz_OUT [2:0]
(Fig. 8)
1
Jitter
83
290
ps
tjcyc-cyc
1Guaranteed by design, not 100% tested in production.
0542G—08/21/03
15
ICS950812
Electrical Characteristics - 3V66 -Un-Buffered Mode: 3V66 [5:0]
TA = 0 - 90°C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified)
PARAMETER
Output Impedance
Average Period
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
CONDITIONS
VO = VDD*(0.5)
MIN
12
TYP MAX UNITS
1
33
65
Ω
ns
V
RDSP1
TPERIOD
Fig. 8
15.00 15.01 15.30
1
IOH = -1 mA
2.05
VOH
1
IOL = 1 mA
0.65
V
VOL
1
V OH@MIN = 1.0 V, V OH@MAX = 3.135 V
VOL @MIN = 1.95 V, VOL @MAX = 0.4 V
VOL = 0.4 V, VOH = 2.4 V (Fig. 7)
VOH = 2.4 V, VOL = 0.4 V (Fig. 7)
-33
26
-28
38
mA
mA
ns
ns
%
IOH
1
IOL
1
0.5
0.5
45
1.6
1.2
48
2.3
2.3
55
tr1
1
Fall Time
tf1
1
Duty Cycle
Skew
dt1
VT = 1.5 V (Fig. 8)
VT = 1.5 V
1
tsk1
40
250
290
ps
ps
1
Jitter
tjcyc-cyc
VT = 1.5 V (Fig. 8)
133
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - VCH, 48MHz DOT, 48MHz, USB
TA = 0 - 90°C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
Output Frequency
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
48DOT Rise Time
48DOT Fall Time
SYMBOL
CONDITIONS
Fig. 8
MIN
TYP MAX UNITS
FO1
48
48
MHz
Ω
1
VO = VDD*(0.5)
20
70
RDSP1
1
IOH = -1 mA
2.05
V
VOH
1
IOL = 1 mA
0.5
-20
27
V
VOL
1
V OH@MIN = 1.0 V, V OH@MAX = 3.135 V
VOL @MIN = 1.95 V, VOL @MAX = 0.4 V
VOL = 0.4 V, VOH = 2.4 V (Fig. 7)
VOH = 2.4 V, VOL = 0.4 V (Fig. 7)
VOL = 0.4 V, VOH = 2.4 V (Fig. 7)
VOH = 2.4 V, VOL = 0.4 V (Fig. 7)
VT = 1.5 V (Fig. 8)
-29
25
0.5
0.5
1
mA
mA
ns
ns
ns
ns
IOH
1
IOL
1
0.7
0.8
1.2
1.4
53
1.15
1.15
2.3
2.3
55
tr1
1
tf1
1
VCH 48 USB Rise Time
VCH 48 USB Fall Time
48 DOT Duty Cycle
VCH 48 USB Duty Cycle
48 DOT Jitter
tr1
1
1
tf1
1
dt1
45
45
%
%
1
VT = 1.5 V (Fig. 8)
53
55
dt1
1
VT = 1.5 V (Fig. 8)
183
0.43
157
410
1
ps
ns
ps
tjcyc-cyc
1
USB to DOT Skew
VT = 1.5 V (0 OR 180 degrees)
tsk1
1
VCH Jitter
tjcyc-cyc
VT = 1.5 V (Fig. 8)
410
1Guaranteed by design, not 100% tested in production.
0542G—08/21/03
16
ICS950812
Electrical Characteristics - REF (1X select)
TA = 0 - 90°C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
Output Frequency
Output Impedance
Output High Voltage
Output Low Voltage
SYMBOL
FO1
CONDITIONS
Fig. 8
MIN
TYP MAX UNITS
14.32
48
MHz
Ω
1
VO = VDD*(0.5)
IOH = -1 mA
IOL = 1 mA
20
70
RDSP1
1
2.05
V
VOH
1
0.45
-25
V
VOL
1
Output High Current
V OH@MIN = 1.0 V, V OH@MAX = 3.135 V -29
mA
IOH
1
Output Low Current
Rise Time
Fall Time
VOL @MIN = 1.95 V, VOL @MAX = 0.4 V
VOL = 0.4 V, VOH = 2.4 V (Fig. 7)
VOH = 2.4 V, VOL = 0.4 V (Fig. 7)
VT = 1.5 V
25
1
27
2.3
2.3
55
mA
ns
ns
%
IOL
1
1.1
1.4
53
tr1
1
1
tf1
1
Duty Cycle
Jitter
dt1
45
1
tjcyc-cyc
VT = 1.5 V (Fig. 8)
180
1200
ps
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - REF (2X select)
TA = 0 - 90°C; VDD=3.3V +/-5%; CL = 20-40 pF (unless otherwise specified)
PARAMETER
Output Frequency
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
FO1
CONDITIONS
Fig. 8
MIN
TYP MAX UNITS
14.32
MHz
Ω
1
VO = VDD*(0.5)
RDSP1
1
IOH = -1 mA
V
VOH
1
IOL = 1 mA
V
VOL
1
V OH@MIN = 1.0 V, V OH@MAX = 3.135 V
VOL @MIN = 1.95 V, VOL @MAX = 0.4 V
VOL = 0.4 V, VOH = 2.4 V (Fig. 7)
VOH = 2.4 V, VOL = 0.4 V (Fig. 7)
mA
mA
ns
IOH
1
IOL
1
1
1
1.1
0.9
53
2.3
2.3
tr1
1
Fall Time
ns
tf1
1
Duty Cycle
dt1
VT = 1.5 V
45
55
%
1
Jitter
tjcyc-cyc
VT = 1.5 V (Fig. 8)
180
1200
ps
1Guaranteed by design, not 100% tested in production.
0542G—08/21/03
17
ICS950812
Figure 1 - Differential (CPUCLK - CPUCLK#) Measurement Points (Tperiod, Duty Cycle, Jitter)
TPERIOD
High Duty Cycle %
Low Duty Cycle %
0.000 V
Figure 2 - 0.7V Differential TRise and TFall Measurement Points
CPUCLK#
+0.35V
0.0V
-0.35V
TRISE
TFALL
CPUCLK
0542G—08/21/03
18
ICS950812
Figure 3 - 0.7V Single Ended Measurement Points for TRise, TFall
TRISE (CPUCLK)
V
= 0.525
OH
V
CROSS
V
= 0.175V
OL
TFALL (CPUCLK#)
Figure 4 - 0.7V VCross Range Measurement Clarification
VCROSS(REL) max
Total VCROSS Variation
(140mV max)
VCROSS(REL) min
0542G—08/21/03
19
ICS950812
Figure 5 - 1.0V Single Ended VCross, VOH and VOL Measurement Points
V
OH Max 1.45V
CPUCLK#
VOH Min 0.92V
VCROSS Max 0.76V
VCROSS Min 0.51V
VOL Max 0.35V
CPUCLK
VOL Min -0.20V
Figure 6 - 1.0V Single Ended Measurement Points for TRise, TFall
TRISE (CPUCLK)
V
= 0.86V
OH
V
CROSS
V
= 0.41V
OL
TFALL (CPUCLK#)
0542G—08/21/03
20
ICS950812
Figure 7 - Measurement Points for TRise, TFall with Lumped Load
2.4V
1.5V
0.4V
Figure 8 - Measurement Points for TPeriod, Duty Cycle and Jitter
TPERIOD
High Duty Cycle %
Low Duty Cycle %
1.5V
0542G—08/21/03
21
ICS950812
General I2C serial interface information
How to Read:
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2 (H)
• ICS clock will acknowledge
• Controller (host) will send start bit.
• Controller (host) sends the write address D2 (H)
• ICS clock will acknowledge
• Controller (host) sends the begining byte location = N
• ICS clock will acknowledge
• Controller (host) sends the begining byte
location = N
• Controller (host) sends the data byte count = X
• ICS clock will acknowledge
• Controller (host) starts sending Byte N through
Byte N + X -1
• ICS clock will acknowledge
• Controller (host) will send a separate start bit.
• Controller (host) sends the read address D3 (H)
• ICS clock will acknowledge
(see Note 2)
• ICS clock will send the data byte count = X
• ICS clock sends Byte N + X -1
• ICS clock sends Byte 0 through byte X (if X(H)
was written to byte 8).
• ICS clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
• Controller (host) will need to acknowledge each
byte
• Controllor (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
Index Block Read Operation
Index Block Write Operation
Controller (Host)
ICS (Slave/Receiver)
Controller (Host)
ICS (Slave/Receiver)
T
starT bit
starT bit
T
Slave Address D2(H)
Slave Address D2(H)
WR
WRite
WR
WRite
ACK
ACK
ACK
ACK
ACK
ACK
Beginning Byte = N
Beginning Byte = N
Data Byte Count = X
Beginning Byte N
RT
Repeat starT
Slave Address D3(H)
RD
ReaD
ACK
Data Byte Count = X
Beginning Byte N
ACK
ACK
Byte N + X - 1
ACK
P
stoP bit
Byte N + X - 1
N
P
Not acknowledge
stoP bit
0542G—08/21/03
22
ICS950812
Buffered Mode - 3V66[0:1], 66MHz_IN, 66MHz_OUT[0:2] and PCI Phase Relationship
All 3V66 clocks are to be in phase with each other. All 66MHz_OUT clocks are to be in phase with each other. There is
NO phase relationship between the 3V66 clocks and the 66MHz_OUT and PCI clocks. In the case where 3V66_1 is
configured as 48MHz VCH clock, there is no defined phase relationship between 3V66_1_VCH and other 3V66 clocks.
The PCI group should lag 3V66 by the standard skew described below as Tpci.
The 66MHz_IN to 66MHz_OUT delay is shown in the figure below and is specified to be within a min and max propagation
value.
66MHz_IN
Tpd
66MHz_OUT
3V66
No Relationship
Tpci
PCICLK_F (2:0) PCICLK (6:0)
E_PCICLK (3,1)
Tepci
Group to Group Skews at Common Transition Edges: Buffered Mode
GROUP
SYMBOL
CONDITIONS
Propogation delay from
66MHz_IN to 66MHz_OUT (2:0)
66MHz_OUT (2:0) leads 33 MHz
PCICLK
MIN
TYP MAX
UNITS
ns
66MHz_IN 66MHz_OUT1,2
Tpd
2.5
2.9
4.5
3.5
66MHz_OUT to PCI1,2
Tpci
1.5
ns
1Guaranteed by design, not 100% tested in production.
2500ps Tolerance
E_PCICLK to PCICLK Skews
GROUP
SYMBOL
CONDITIONS
MIN
0.3
TYP MAX
UNITS
ns
E_PCICLK1 (pin 11)=0
E_PCICLK3 (pin 13)=1
E_PCICLK1 (pin 11)=1
E_PCICLK3 (pin 13)=0
E_PCICLK1 (pin 11)=1
E_PCICLK3 (pin 13)=1
TE_PCI-PCI1
0.5
1.0
1.5
0.7
1.2
1.7
E_PCICLK to PCICLK1
TE_PCI-PCI2
TE_PCI-PCI3
0.8
1.3
ns
ns
1Guaranteed by design, not 100% tested in production.
0542G—08/21/03
23
ICS950812
Un-Buffered Mode 3V66 & PCI Phase Relationship
All 3V66 clocks are to be in pphase with each other. In the case where 3V66_1 is configured as 48MHz VCH clock, there
is no defined phase relationship between 3V66_1_VCH and other 3V66 clocks. The PCI group should lag 3V66 by the
standard skew described below as Tpci.
3V66 (1:0)
3V66 (4:2)
3V66_5
Tpci
PCICLK_F (2:0) PCICLK (6:0)
E_PCICLK (3,1)
Tepci
Group to Group Skews at Common Transition Edges: Unbuffered Mode
GROUP
3V66 to PCI1,2
SYMBOL
CONDITIONS
MIN
TYP MAX
UNITS
ns
S3V66-PCI
3V66 (5:0) leads 33MHz PCI
1.5
2.55 3.5
1Guarenteed by design, not 100% tested in production.
2500ps Tolerance
E_PCICLK to PCICLK Skews
GROUP
SYMBOL
CONDITIONS
MIN
0.3
TYP MAX
UNITS
ns
E_PCICLK1 (pin 11)=0
E_PCICLK3 (pin 13)=1
E_PCICLK1 (pin 11)=1
E_PCICLK3 (pin 13)=0
E_PCICLK1 (pin 11)=1
E_PCICLK3 (pin 13)=1
TE_PCI-PCI1
0.5
1.0
1.5
0.7
1.2
1.7
E_PCICLK to PCICLK1
TE_PCI-PCI2
TE_PCI-PCI3
0.8
1.3
ns
ns
1Guaranteed by design, not 100% tested in production.
0542G—08/21/03
24
ICS950812
PCI_STOP# - Assertion (transition from logic "1" to logic "0")
The impact of asserting the PCI_STOP# signal will be the following.All PCI[6:0] and stoppable PCI_F[2,0] clocks will latch
low in their next high to low transition.The PCI_STOP# setup time tsu is 10 ns, for transitions to be recognized by the next
rising edge.
Assertion of PCI_STOP# Waveforms
PCI_STOP#
PCI_F[2:0] 33MHz
PCI[6:0] 33MHz
tsu
CPU_STOP# - Assertion (transition from logic "1" to logic "0")
The impact of asserting the CPU_STOP# pin is all CPU outputs that are set in the I2C configuration to be stoppable via
assertion of CPU_STOP# are to be stopped after their next transition. When the I2C Bit 6 of Byte 1 is programmed to '0'
the final state of the stopped CPU signals is CPU = High and CPU# = Low. There is to be no change to the output drive
current values.The CPU will be driven high with a current value equal to (Mult 0 'select') x (Iref), the CPU# signal will not
be driven .When the I2C Bit 6 of Byte 1 is programmed to '1' then final state of the stopped CPU signals is Low, both CPU
and CPU# outputs will not be driven.
Assertion of CPU_STOP# Waveforms
CPU_STOP#
CPUCLKT
CPUCLKC
CPU_STOP# Functionality
CPU_STOP#
CPUT
CPUC
1
0
Normal
Normal
Float
iref * Mult
0542G—08/21/03
25
ICS950812
CPU_STOP# - De-assertion (transition from logic "0" to logic "1")
All CPU outputs that were stopped are to resume normal operation in a glitch free manner.The maximum latency from the
de-assertion to active outputs is to be defined to be between 2 - 6 CPU clock periods (2 clocks are shown). If the I2C
Bit 6 of Byte 1 is programmed to "1" then the stopped CPU outputs will be driven High within 10 nS of CPU_Stop# de-
assertion.
De-assertion of CPU_STOP# Waveforms
CPU_STOP#
CPUCLKT(2:0)
Tdrive_CPU_STOP# <10ns @ 200mV
*CPUCLKT(2:0)TS
CPUCLKC(2:0)
*Signal TS is CPUCLKT in Tri-State mode
PD# - Assertion (transition from logic "1" to logic "0")
When PWRDWN# is sampled low by two consecutive rising edges of CPU clock, then all clock outputs except CPU clocks
must be held low on their next high to low transitions. When the I2C Bit 6 of Byte 0 is programmed to '0' CPU clocks must
be held with the CPU clock pin driven high with a value of 2 x Iref, and CPU# undriven. If Bit 6 of Byte 0 is '1' then both
CPU and CPU# are undriven. Note the example below shows CPU = 133 MHz and Bit 6 of Byte 0 = '0', this diagram and
description is applicable for all valid CPU frequencies 66, 100, 133, 200 MHz.
Due to the state if the internal logic, stopping and holding the REF clock outputs in the LOW state may require more than
one clock cycle to complete.
Power Down Assertion of Waveforms
0ns
25ns
50ns
PD#
CPUCLKT 100MHz
CPUCLKC 100MHz
3V66MHz
66MHz_IN
66MHz_OUT
PCICLK 33MHz
USB 48MHz
REF 14.318MHz
PD# Functionality
PD#
PCICLK_F
PCICLK
USB/DOT
48MHz
CPUCLKT CPUCLKC
3V66
66MHz_OUT
PCICLK
66MHz_IN/2 66MHz_IN/2
Low Low
1
0
Normal
Normal
Float
66MHz
Low
66MHz_IN
Low
48MHz
Low
iref * Mult
0542G—08/21/03
26
ICS950812
Power Down De-Assertion Mode
The power-up latency needs to be less than 1.8mS. this is the time from the de-asseration of the powerdown of the ramping
of the power supply until the time that stable clocks are output from the clock chip. If the I2C Bit 6 of Byte 0 is programmed
to "1" then the stopped CPU outputs will be driven high within 3 nS of PD# de-asseration.
Test Configuration Diagrams
Rs=33 Ohms
1%
TLA
Rdif=475 Ohms
CPUCLKT test
point
1%
CLK408
Rs=33 Ohms
1%
TLB
CPUCLKC test
point
Rp=63.4 Ohms
1%
Rp=63.4 Ohms
1%
2pF
5%
2pF
5%
R
REF=221 Ohms
1%
MULTSEL Pin must be Low
CPU 1.0V Configuration test load board termination
Rs=33 Ohms
5%
TLA
CLK408
CPUCLKT test
point
Rs=33 Ohms
5%
TLB
CPUCLKC test
point
Rp=49.9 Ohms
1%
Rp=49.9 Ohms
1%
Rset=475 Ohms
1%
2pF
5%
2pF
5%
MULTSEL Pin must be High
CPU 0.7V Configuration test load board termination
0542G—08/21/03
27
ICS950812
c
N
In Millimeters
In Inches
SYMBOL
COMMON DIMENSIONS COMMON DIMENSIONS
L
MIN
2.41
0.20
0.20
0.13
MAX
2.80
0.40
0.34
0.25
MIN
.095
.008
.008
.005
MAX
.110
.016
.0135
.010
A
A1
b
E1
E
INDEX
AREA
c
D
E
E1
e
SEE VARIATIONS
SEE VARIATIONS
1
2
10.03
7.40
10.68
7.60
.395
.291
.420
.299
a
hh xx 4455°°
D
0.635 BASIC
0.025 BASIC
h
L
0.38
0.50
0.64
1.02
.015
.020
.025
.040
A
N
α
SEE VARIATIONS
SEE VARIATIONS
0°
8°
0°
8°
A1
- CC --
VARIATIONS
e
SEATING
PLANE
D mm.
D (inch)
b
N
MIN
18.31
MAX
18.55
MIN
.720
MAX
.730
.10 (.004)
C
56
Reference Doc.: JEDEC Publication 95, M O-118
300 mil SSOP Package
10-0034
Ordering Information
ICS950812yFLFT
Example:
ICS XXXX y F LF T
Designation for tape and reel packaging
Lead Free (optional)
Package Type
F = SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
0542G—08/21/03
28
ICS950812
c
N
In Millimeters
In Inches
SYMBOL
COMMON DIMENSIONS COMMON DIMENSIONS
L
MIN
--
0.05
0.80
0.17
0.09
MAX
1.20
0.15
1.05
0.27
0.20
MIN
--
.002
.032
.007
.0035
MAX
.047
.006
.041
.011
.008
A
A1
A2
b
E1
E
INDEX
AREA
c
1
22
D
E
E1
e
SEE VARIATIONS
8.10 BASIC
SEE VARIATIONS
0.319 BASIC
a
D
6.00
6.20
.236
.244
0.50 BASIC
0.020 BASIC
L
0.45
0.75
.018
.030
N
SEE VARIATIONS
SEE VARIATIONS
A
A2
0°
--
8°
0.10
0°
--
8°
.004
α
aaa
A1
- CC --
VARIATIONS
e
SEATING
PLANE
D mm.
D (inch)
b
N
MIN
13.90
MAX
14.10
MIN
.547
MAX
.555
aaa
C
56
Reference Doc.: JEDEC Publication 95, M O-153
10-0039
6.10 mm. Body, 0.50 mm. pitch TSSOP
(20 mil)
(240 mil)
Ordering Information
ICS950812yGLFT
Example:
ICS XXXX y G LF T
Designation for tape and reel packaging
Lead Free (optional)
Package Type
G = TSSOP
Revision Designator (will not correlate with datasheet revision)
DeviceType (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
0542G—08/21/03
29
相关型号：
SI9130DB
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