ICS950813 [ICSI]
Frequency Generator with 200MHz Differential CPU Clocks; 频率发生器，差分200MHz的CPU时钟
| 型号： | ICS950813 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Frequency Generator with 200MHz Differential CPU Clocks |
| 文件： | 总22页 (文件大小：253K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS950813
Advance Information
Integrated
Circuit
Systems,Inc.
Frequency Generator with 200MHz Differential CPU Clocks
Recommended Application:
Pin Configuration
CK-408 clock for Brookdale/Odem/Montara-GM for P4/Banias
processor.
VDDREF
X1
X2
GND
PCICLK_F0
PCICLK_F1
1
2
3
4
5
56 REF
55 FS1
54 FS0
53 CPU_STOP#*
52 CPUCLKT0
Output Features:
•
•
•
•
•
•
•
3 Differential CPU Clock Pairs @ 3.3V
7 PCI (3.3V) @ 33.3MHz including 2 early PCI clocks
3 PCI_F (3.3V) @ 33.3MHz
CPUCLKC0
51
6
7
8
9
*ASEL/PCICLK_F2
VDDPCI
50 VDDCPU
49 CPUCLKT1
48 CPUCLKC1
47 GND
1 USB (3.3V) @ 48MHz, 1 DOT (3.3V) @ 48MHz
1 REF (3.3V) @ 14.318MHz
GND
PCICLK0 10
**E_PCICLK1/PCICLK1 11
PCICLK2 12
**E_PCICLK3/PCICLK3 13
VDDPCI 14
46 VDDCPU
45 CPUCLKT2
44 CPUCLKC2
43 MULTSEL*
42 IREF
5 3V66 (3.3V) @ 66.6MHz
1 VCH/3V66 (3.3V) @ 48MHz or 66.6MHz
Features:
GND 15
•
Provides standard frequencies and additional 3%, 5%
and 10% over-clocked frequencies
PCICLK4 16
PCICLK5 17
PCICLK6 18
VDD3V66 19
GND 20
41 GND
40 PWRSAVE#*
39 48MHz_USB/FS2**
38 48MHz_DOT
37 VDD48
•
Supports spread spectrum modulation:
No spread, Center Spread (±0.3%, ±0.55%), or Down
Spread (-0.5%, -0.75%)
3V66_2 21
3V66_3 22
3V66_4 23
3V66_5 24
36 GND
•
•
•
•
•
Offers adjustable PCI early clock via latch inputs
Selectable 1X or 2X strength for REF via I2C interface
Programmable group to group skew
35 3V66_1/VCH_CLK/FS3**
34 PCI_STOP#*
33 3V66_0/FS4**
32 VDD3V66
31 GND
*PD# 25
VDDA 26
GND 27
Vtt_PWRGD# 28
Linear programmable frequency and spreading %
Efficient power management scheme through PD#,
CPU_STOP# and PCI_STOP#.
30 SCLK
29 SDATA
•
•
Uses external 14.318MHz crystal
56-Pin 300mil SSOP
56-Pin 240mil TSSOP
Stop clocks and functional control available through
I2C interface.
Key Specifications:
*These inputs have 120K internal pull-up resistors to VDD.
**Internal pull-down resistors to ground.
•
•
•
CPU Output Jitter <150ps
3V66 Output Jitter <250ps
CPU Output Skew <100ps
Block Diagram
Functionality Table
CPU
AGP
PCI
48MHz_USB
48MHz_DOT
PLL2
FS1
FS0
MHz
MHz
66.67
66.67
MHz
33.33
33.33
0
0
1
0
1
0
100.00
133.33
X1
X2
XTAL
OSC
3V66 (5:2)
REF
200.00
166.66
66.67
66.66
33.33
33.33
1
1
PLL1
Spread
Spectrum
CPUCLKT (2:0)
CPUCLKC (2:0)
CPU
DIVDER
3
3
Stop
Stop
Asynchronous AGP/PCI Frequency Selection Table
Byte7 Bit5 Byte7 Bit4 AGP Frequency
PWRSAVE#
Vtt_PWRGD#
PD#
PCI
DIVDER
PCICLK (6:0)
PCI Frequency
7
3
Control
Logic
PCICLK_F (2:0)
0
0
1
1
0
1
0
1
66.00
75.43
88.00
--
33.00
37.72
44.00
--
3V66
DIVDER
CPU_STOP#
PCI_STOP#
MULTSEL
FS (4:0)
3V66_0
3V66_1/VCH_CLK
Config.
Reg.
SDATA
I REF
SCLK
0708—10/10/02
ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals.
ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.
ICS950813
Advance Information
Pin Description
PIN # PIN NAME
PIN TYPE DESCRIPTION
1
2
3
4
5
6
VDDREF
X1
PWR
IN
Ref, XTAL power supply, nominal 3.3V
Crystal input,nominally 14.318MHz.
Crystal output, Nominally 14.318MHz
Ground pin.
X2
OUT
PWR
OUT
OUT
GND
PCICLK_F0
PCICLK_F1
Free running PCI clock not affected by PCI_STOP# .
Free running PCI clock not affected by PCI_STOP# .
Asynchronous AGP/PCI frequency latch input pin / 3.3V PCI free running
clock put. Pull-Up = Main PLL / Pull-Down = Async Fix PLL
Power supply for PCI clocks, nominal 3.3V
7
*ASEL/PCICLK_F2
I/O
8
9
VDDPCI
GND
PWR
PWR
OUT
I/O
Ground pin.
10 PCICLK0
11 **E_PCICLK1/PCICLK1
12 PCICLK2
13 **E_PCICLK3/PCICLK3
14 VDDPCI
PCI clock output.
Early/Normal PCI clock output latched at power up.
PCI clock output.
OUT
I/O
Early/Normal PCI clock output latched at power up.
Power supply for PCI clocks, nominal 3.3V
Ground pin.
PWR
PWR
OUT
OUT
OUT
PWR
PWR
OUT
OUT
OUT
OUT
15 GND
16 PCICLK4
17 PCICLK5
18 PCICLK6
19 VDD3V66
20 GND
PCI clock output.
PCI clock output.
PCI clock output.
Power pin for the 3V66 clocks.
Ground pin.
21 3V66_2
3.3V 66.66MHz clock output
3.3V 66.66MHz clock output
3.3V 66.66MHz clock output
3.3V 66.66MHz clock output
22 3V66_3
23 3V66_4
24 3V66_5
Asynchronous active low input pin used to power down the device into a low
power state. The internal clocks are disabled and the VCO and the crystal
are stopped. The latency of the power down will not be greater than 3ms.
25 *PD#
IN
26 VDDA
27 GND
PWR
PWR
3.3V power for the PLL core.
Ground pin.
This 3.3V LVTTL input is a level sensitive strobe used to determine when
latch inputs are valid and are ready to be sampled. This is an active low
input.
28 Vtt_PWRGD#
IN
0708—10/10/02
2
ICS950813
Advance Information
Pin Description (Continued)
PIN # PIN NAME
29 SDATA
PIN TYPE DESCRIPTION
I/O
IN
Data pin for I2C circuitry 5V tolerant
Clock pin of I2C circuitry 5V tolerant
Ground pin.
30 SCLK
31 GND
PWR
PWR
I/O
32 VDD3V66
33 3V66_0/FS4**
Power pin for the 3V66 clocks.
Frequency select latch input pin / 3.3V 66.66MHz clock output.
Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level, when input
low
34 PCI_STOP#*
IN
Frequency select latch input pin / 3.3V 66.66MHz clock output / 48MHz
VCH clock output.
Ground pin.
35 3V66_1/VCH_CLK/FS3**
I/O
36 GND
PWR
PWR
OUT
I/O
37 VDD48
Power for 24 & 48MHz output buffers and fixed PLL core.
48MHz clock output.
38 48MHz_DOT
39 48MHz_USB/FS2**
Frequency select latch input pin / 3.3V 48MHz clock output.
Real Time input pin to change frequency to under-clock entries located in
FS 4:2 = '100'. Clock groups gear ratio will not be change during this
operation.
40 PWRSAVE#*
41 GND
IN
PWR
OUT
Ground pin.
This pin establishes the reference current for the CPUCLK pairs. This pin
requires a fixed precision resistor tied to ground in order to establish the
appropriate current.
42 IREF
43 MULTSEL*
44 CPUCLKC2
IN
3.3V LVTTL input for selection the current multiplier for CPU outputs
"Complementary" clocks of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
"True" clocks of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
Supply for CPU clocks, 3.3V nominal
OUT
45 CPUCLKT2
OUT
46 VDDCPU
47 GND
PWR
PWR
Ground pin.
"Complementary" clocks of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
"True" clocks of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
Supply for CPU clocks, 3.3V nominal
"Complementary" clocks of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
"True" clocks of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
Stops all CPUCLK besides the free running clocks
48 CPUCLKC1
OUT
49 CPUCLKT1
50 VDDCPU
OUT
PWR
OUT
51 CPUCLKC0
52 CPUCLKT0
OUT
53 CPU_STOP#*
54 FS0
IN
IN
Frequency select pin.
55 FS1
IN
Frequency select pin.
56 REF
OUT
14.318 MHz reference clock.
Power Supply
Pin Number
Description
VDD
1
GND
4
Xtal, Ref, CPU PLL, digital
48MHz, Fix Digital, Fix Analog
Master clock, CPU Analog
37
36
46
47
0708—10/10/02
3
ICS950813
Advance Information
Frequency Select Table 1
Bit4 Bit3 Bit2 Bit1 Bit0 CPU
AGP
PCI
Spread
FS4 FS3 FS2 FS1 FS0 MHz
MHz
MHz
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
%
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
100.00 66.67
133.33 66.67
200.00 66.67
166.66 66.66
100.00 66.67
133.33 66.67
200.00 66.67
166.66 66.66
100.00 66.67
133.33 66.67
0.3% Center
0.3% Center
0.3% Center
0.3% Center
0 - 0.5% down
0 - 0.5% down
0 - 0.5% down
0 - 0.5% down
0.55% Center
0.55% Center
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
0
0
0
1
1
1
1
1
1
0
0
1
0
1
0
200.00 66.67
33.33
33.33
0.55% Center
0.55% Center
0
1
1
1
1
166.66 66.66
100.00 66.67
133.33 66.67
200.00 66.67
166.66 66.66
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
33.33 0 - 0.75% down
33.33 0 - 0.75% down
33.33 0 - 0.75% down
33.33 0 - 0.75% down
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
80.00
53.33
26.67
26.67
26.67
26.67
34.33
34.33
34.33
34.33
35.00
35.00
Spread Off
Spread Off
Spread Off
Spread Off
0.3% Center
0.3% Center
0.3% Center
0.3% Center
0.3% Center
0.3% Center
N/A
106.66 53.33
160.00 53.33
133.33 53.33
103.00 68.67
137.33 68.66
206.00 68.67
171.66 68.66
105.00 70.00
140.00 70.00
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
Tristate Tristate Tristate
174.99 70.00
110.00 73.33
146.66 73.33
35.00
36.67
36.67
0.3% Center
0.3% Center
0.3% Center
N/A
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
Test/2 Test/4 Test/8
183.33 73.33 36.67
0.3% Center
0708—10/10/02
4
ICS950813
Advance Information
Host Swing Select Functions
Voh @ Z
MULTSEL
Board Target
Reference R,
Output
Rr = 221 1%,
Iref = 5.00mA
50 ohms
Ioh = 4 * I REF
1.0V @ 50 ohm
0
Rr = 475 1%,
Iref = 2.32mA
50 ohms
Ioh = 6 * I REF
0.7V @ 50 ohm
1
PCI Select Functions
E_PCICLK(3,1)*
E_PCICLK1
E_PCICLK3
0
0
0
1
0ns
0.5ns
1
1
0
1
1.0ns
1.5ns
Note:
E_PCICLK1 = 10Kohm resistor.
E_PCICLK3 = 10Kohm resistor.
0 = No resistor
1 = 10Kohm pull-up to VDD
.
* Approximate values
Frequency Select Table 2
Freqency Select
CPU, 3V66, PCI
Clocking Mode
0.3% Center Spread
FS4
0
FS3
0
FS2
0
Standard Clocking
0
0
1
Standard Clocking 0 to -0.5%, Down Spread
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
Standard Clocking
Standard Clocking
Pwr Save Clocking
3% Overclocking
5% Overclocking
10% Overclocking
0.3% Center Spread
0 to - 0.75%, Down
Spread Off
0.3% Center Spread
0.3% Center Spread
0.3% Center Spread
PWRSAVE# Usage Illustration
Bit4
FS4
X
Bit3
FS3
X
Bit2 Bit1 Bit0
CPU
MHz
XXX
XXX
XXX
XXX
AGP
MHz
XXX
XXX
XXX
XXX
PCI
MHz
XXX
XXX
XXX
XXX
PWRSAVE# = '1'. as
PWRSAVE# = '0'. as
FS2
X
FS1
0
FS0
0
PWRSAVE# is driven back to
high '1'. The output frequencies
will be driven back to the
original programmed
frequencies smoothly. Notice
that this operation will only
happen after the PWRSAVE#
has been driven to '0'. This will
not affect power up or I2C
programmed frequencies if the
PWRSAFE# has been tied to a
'1'.
PWRSAVE# is driven to low '0'.
The output frequencies of the
CPU, AGP and PCI clock will
smoothly switch to frequencies
indicated by FS (4:2) = 100. The
frequencies gear ratio will be kept
the same. Notice that the 48MHz
& REF frequencies will not be
changed. This function can be
used with asynchronous
X
X
X
0
1
X
X
X
1
0
X
X
X
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
80.00
53.33
26.67
26.67
26.67
26.67
106.66 53.33
160.00 53.33
133.33 53.33
AGP/PCI frequencies.
0708—10/10/02
5
ICS950813
Advance Information
BYTE
0
Affected Pin
Name
Bit Control
Control Function
Type
Pin #
0
1
PWD
Bit 7
-
Spread Enabled
Spread Spectrum Control
Power down mode output level
0= CPU driven in power down
1= undriven
RW
OFF
ON
0
Bit 6
-
CPUCLKT(2:0)
RW
HIGH
LOW
0
Bit 5
Bit 4
35
53
3V66_1/VCH_CLK/FS3**
CPU_STOP#*
VCH/66.66 Select
Reflects value of pin
RW
R
66.66
Stop
48.00
Active
0
X
Reflects value of pin at power up.
Also can be set.
Bit 3
34
PCI_STOP#*
RW
Stop
Active
X
Bit 2
Bit 1
Bit 0
39
55
54
FS3
FS1
FS0
Frequency Selection
Frequency Selection
Frequency Selection
RW
R
R
-
-
-
-
-
-
X
X
X
Note: For PCI_STOP# function, refer to table 3.
BYTE
1
Affected Pin
Name
Bit Control
Control Function
Type
Pin #
0
1
PWD
Bit 7
43
MULTSEL*
Reflects value of pin
CPU_Stop mode output level
0= CPU driven when stopped
1 = undriven
R
-
-
x
Bit 6
-
CPUCLKT(2:0)
RW
HIGH
LOW
0
CPUCLKT2, CPUCLKC2
(see note)
CPUCLKT1, CPUCLKC1
(see note)
CPUCLKT0, CPUCLKC0
(see note)
CPUCLKT2, CPUCLKC2
CPUCLKT1, CPUCLKC1
CPUCLKT0, CPUCLKC0
Allow control of output with
assertion of CPU_STOP#.
Allow control of output with
assertion of CPU_STOP#.
Allow control of output with
assertion of CPU_STOP#.
Output control
Not
Freerun
Not
Freerun
Not
Freerun
Disable
Disable
Disable
Bit 5
Bit 4
Bit 3
45, 44
49, 48
52, 51
RW
RW
RW
Freerun
Freerun
Freerun
0
0
0
Bit 2
Bit 1
Bit 0
45, 44
49, 48
52, 51
RW
RW
RW
Enable
Enable
Enable
1
1
1
Output control
Output control
Note: CPUCLK(2:0) can be turned on/off by CPU_STOP#. Refer to table 4.
BYTE
2
Affected Pin
Name
Bit Control
Control Function
Type
Pin #
56
18
17
16
13
12
11
10
0
1
PWD
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
REF
PCICLK6
PCICLK5
1X or 2X Strength control
Output control
Output control
Output control
Output control
Output control
Output control
Output control
RW
RW
RW
RW
RW
RW
RW
RW
1X
2X
0
1
1
1
1
1
1
1
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
PCICLK4
**E_PCICLK3/PCICLK3
PCICLK2
**E_PCICLK1/PCICLK1
PCICLK0
Note: PCICLK(6:0) can be turned on/off by PCI_STOP#. Refer to table 3.
0708—10/10/02
6
ICS950813
Advance Information
BYTE
3
Affected Pin
Name
48MHz_DOT
48MHz_USB/FS2**
Bit Control
Control Function
Type
Pin #
38
39
0
1
PWD
1
1
Bit 7
Bit 6
Output control
Output control
RW
RW
Disable
Disable
Enable
Enable
Not
Freerun
Not
Freerun
Not
Freerun
Enable
Enable
Enable
Allow control of output with
assertion of PCI_STOP#.
Allow control of output with
assertion of PCI_STOP#.
Allow control of output with
assertion of PCI_STOP#.
Output control
Bit 5
Bit 4
Bit 3
7
6
5
*ASEL/PCICLK_F2 (see note)
PCICLK_F1 (see note)
RW
RW
RW
Freerun
Freerun
Freerun
0
0
0
PCICLK_F0 (see note)
Bit 2
Bit 1
Bit 0
7
6
5
*ASEL/PCICLK_F2
PCICLK_F1
RW
RW
RW
Disable
Disable
Disable
1
1
1
Output control
Output control
PCICLK_F0
Note: PCICLK_F(2:0) can be turned on/off by PCI_STOP#. Refer to table 5.
BYTE
Affected Pin
Name
Bit Control
Control Function
Type
4
Pin #
35
33
33
35
24
23
22
21
0
1
PWD
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
FS3
FS4
Frequency Selection
Frequency Selection
Output control
RW
RW
RW
RW
RW
RW
RW
RW
-
-
X
X
1
1
1
1
1
1
-
-
3V66_0/FS4**
3V66_1/VCH_CLK/FS3**
3V66_5
Disable
Disable
Disable
Disable
Disable
Disable
Enable
Enable
Enable
Enable
Enable
Enable
Output control
Output control
Output control
Output control
3V66_4
3V66_3
3V66_2
Output control
BYTE
5
Affected Pin
Name
Bit Control
Control Function
Type
Pin #
0
OFF
-
1
PWD
Allow Iref Mirror to be ON during
Power Down Mode
Bit 7
Bit 6
Bit 5
X
X
X
PD Mode Iref Mirror Enable
Reserved
RW
X
ON
0
0
0
Reserved
-
Allow control of output with
assertion of CPU_STOP#.
Allow control of output with
assertion of CPU_STOP#.
00 = Medium (default), 01 = Low,
11,10 =High
Not
Freerun
3V66(5:2) (See table 6)
X
Freerun
Not
Freerun
Bit 4
X
3V66(1:0) (See table 7)
X
Freerun
0
Bit 3
Bit 2
Bit 1
RW
RW
RW
-
-
-
-
-
-
0
0
0
38
48MHz_DOT Slew Control
00 = Medium (default), 01 = Low,
11,10 =High
39
48MHz_USB Slew Control
Bit 0
RW
-
-
0
Functions in Byte 5 of CK408 were intended as a test and debug byte only.
Note:
BYTE
6
Affected Pin
Bit Control
Control Function
Type
Pin #
X
Name
0
-
-
-
-
-
-
-
-
1
-
-
-
-
-
-
-
-
PWD
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Revision ID Bit 3
Revision ID Bit 2
Revision ID Bit 1
Revision ID Bit 0
Vendor ID Bit 3
Vendor ID Bit 2
Vendor ID Bit 1
Vendor ID Bit 0
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
1
X
Revision ID Value Based on
Device Revision
X
X
X
X
X
X
(Reserved)
(Reserved)
(Reserved)
(Reserved)
0708—10/10/02
7
ICS950813
Advance Information
BYTE
7
Bit 7
Affected Pin
Name
Bit Control
Control Function
(Reserved)
Type
RW
Pin #
X
0
1
PWD
1
(Reserved)
-
-
Fix_PLL CPU_PLL
Async Sync
Bit 6
X
AEN
3V66/PCI Freq Source Select
RW
1
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
X
X
X
X
X
AFS1
AFS0
Async Freq select bit 1
Async Freq select bit 0
(Reserved)
RW
RW
RW
RW
See Async Freq
Selection Table
0
0
1
1
(Reserved)
(Reserved)
-
-
-
-
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
RW
RW
-
-
-
-
1
1
BYTE
8
Affected Pin
Bit Control
Control Function
Type
Pin #
Name
0
1
PWD
Bit 7
X
-
(Reserved)
X
-
-
0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
X
X
X
X
X
-
-
-
-
-
(Reserved)
(Reserved)
(Reserved)
X
X
X
R
R
-
-
-
-
-
-
-
-
-
-
0
0
0
1
1
Readback Byte Count
Bit 1
Bit 0
X
X
-
-
R
R
-
-
-
-
1
1
Note: Byte 8 is for ICS test only. Do not write as system damage may occur. Bit(2:0) contain the readback Byte count.
BYTE
9
Affected Pin
Name
Bit Control
Control Function
Type
Pin #
0
-
1
-
PWD
Bit 7
Bit 6
Bit 5
00 = High(default), 01 = Low,
11,10 = Medium
RW
RW
RW
0
0
0
35
VCHCLK Slew Control
-
-
00 (default), 11 = Medium
01 = Low, 10 =High
-
-
7, 6, 5
PCICLK_F (2:0) Slew Contol
PCICLK (3:0) Slew Contol
PCICLK (6:4) Slew Contol
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RW
RW
RW
RW
RW
-
-
-
-
-
-
-
-
-
-
0
0
0
0
0
13, 12,
11, 10
00 (default), 11 = Medium
10 = Low, 01 =High
00 (default), 11 = Medium
10 = Low, 01 =High
18 , 17 , 16
BYTE
10
Affected Pin
Name
Bit Control
Control Function
Type
Pin #
0
1
PWD
M/N Enable (Enable access to
Byte 11 - 14)
Byte
(11-14)
Bit 7
X
-
RW
HW/B0
0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
X
X
X
X
X
X
-
Unused
-
-
-
-
-
-
-
-
-
-
-
-
-
0
0
0
1
0
1
RW
RW
-
-
-
3V66 (5:2) Skew
Approx 250ps per bit (Ref to PCI)
-
-
-
Unused
Unused
Unused
Bit 0
X
-
Unused
-
-
-
0
Note: See table 8 for Byte 11-14 default information
0708—10/10/02
8
ICS950813
Advance Information
BYTE
11
Affected Pin
Name
Bit Control
Control Function
Type
Pin #
0
1
PWD
Bit 7
X
-
VCO Divider Bit8
RW
-
-
X
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
X
X
X
X
X
X
-
-
-
-
-
-
-
REF Divider Bit6
REF Divider Bit5
REF Divider Bit4
REF Divider Bit3
REF Divider Bit2
REF Divider Bit1
REF Divider Bit0
RW
RW
RW
RW
RW
RW
RW
-
-
-
-
-
-
-
-
-
-
-
-
-
-
X
X
X
X
X
X
X
Note: The decimal representation of these 7 bits (Byte 11 bit[6:0]) + 2 is equal to the REF divider value.
BYTE
12
Affected Pin
Name
Bit Control
Control Function
Type
Pin #
0
1
PWD
Bit 7
X
-
VCO Divider Bit7
RW
-
-
X
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
X
X
X
X
X
X
-
-
-
-
-
-
-
VCO Divider Bit6
VCO Divider Bit5
VCO Divider Bit4
VCO Divider Bit3
VCO Divider Bit2
VCO Divider Bit1
VCO Divider Bit0
RW
RW
RW
RW
RW
RW
RW
-
-
-
-
-
-
-
-
-
-
-
-
-
-
X
X
X
X
X
X
X
Note: The decimal representation of these 9 bits (Byte 12 bit[7:0]) and Byte 11 bit [7]) + 8 is equal to the VCO divider value.
BYTE
13
Affected Pin
Name
Bit Control
Control Function
Type
Pin #
0
1
PWD
Bit 7
X
-
Spread Spectrum Bit7
RW
-
-
X
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
X
X
X
X
X
X
-
-
-
-
-
-
-
Spread Spectrum Bit6
Spread Spectrum Bit5
Spread Spectrum Bit4
Spread Spectrum Bit3
Spread Spectrum Bit2
Spread Spectrum Bit1
Spread Spectrum Bit0
RW
RW
RW
RW
RW
RW
RW
-
-
-
-
-
-
-
-
-
-
-
-
-
-
X
X
X
X
X
X
X
Note: Please utilize software utility provided by ICS Application Engineering to configure spread spectrum. Incorrect spread
percentage may cause system failure.
BYTE
14
Affected Pin
Name
Bit Control
Control Function
Type
Pin #
0
1
PWD
Bit 7
X
-
(Reserved)
RW
-
-
X
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
X
X
X
X
X
X
-
-
-
-
-
-
-
(Reserved)
RW
RW
RW
RW
RW
RW
RW
-
-
-
-
-
-
-
-
-
-
-
-
-
-
X
X
X
X
X
X
X
Spread Spectrum Bit13
Spread Spectrum Bit12
Spread Spectrum Bit11
Spread Spectrum Bit10
Spread Spectrum Bit9
Spread Spectrum Bit8
Note: Please utilize software utility provided by ICS Application Engineering to configure spread spectrum. Incorrect spread
percentage may cause system failure.
0708—10/10/02
9
ICS950813
Advance Information
Table 3
PCI_STOP# I2C Control Table
PCI_STOP#
(Pin 34)
Byte 0 Bit 3
Write Bit
Byte 0, Bit 3 Read Bit
(Internal Status)
0
0
1
1
0
1
0
1
0
0
0
1`
When this Byte 0, Bit 3 is low (0), all PCI clocks are stopped.
Note:
Table 4
CPUCLKT/C (2:0) Outputs I2C Control Table
CPU_STOP#
Byte 1
CPUCLKT/C (2:0) Outputs
(Pin 53)
Bit 3, 4, 5
0
0
1
1
0
1
0
1
Stop
Running
Running
Running
Individual CPUCLK outputs are controlled by Byte 1, Bit 3, 4, and 5.
Note:
Table 5
PCICLK_F (2:0) Outputs I2C Control Table
PCI_STOP#
(Pin 34)
Byte 3
Bit 3, 4, 5
PCICLK (2:0) Outputs
0
0
1
1
0
1
0
1
Stop
Running
Running
Running
Individual PCICLK outputs are controlled by Byte 3, Bit 3, 4, and 5.
Note:
Table 6
3V66 (5:2) I2C Control Table
CPU_STOP#
(Pin 53)
Byte 5
Bit 5
3V66 (5:2)
0
0
1
1
0
1
0
1
Running
Stopped
Running
Running
Activating Byte 5, Bit 5 will allow CPU_STOP# to control stop of pins 21, 22, 23, and 24.
Note:
Table 7
3V66 (1:0) I2C Control Table
CPU_STOP#
(Pin 53)
Byte 5
Bit 4
3V66 (1:0)
0
0
1
1
0
1
0
1
Running
Stopped
Running
Running
Activating Byte 5, Bit 4 will allow CPU_STOP# to control stop of pins 33 and 35.
Note:
0708—10/10/02
10
ICS950813
Advance Information
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD + 0.5 V
Ambient Operating Temperature . . . . . . . . . . 0°C to +90°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . 115°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device.These ratings
are stress specifications only and functional operation of the device at these or any other conditions above those listed
in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
SYMBOL
VIH
CONDITIONS
MIN
TYP
MAX
VDD + 0.3
0.8
UNITS
V
2
VSS - 0.3
-5
VIL
V
IIH
VIN = VDD
5
mA
mA
IIL1
VIN = 0 V; Inputs with no pull-up resistors
-5
Input Low Current
IIL2
VIN = 0 V; Inputs with pull-up resistors
CL = Full load; Select @ 100 MHz
CL =Full load; Select @ 133 MHz
-200
229
220
Operating Supply
Current
IDD3.3OP
mA
mA
280
IDD3.3OP
280
45
Powerdown Current
Input Frequency
Pin Inductance
IDD3.3PD IREF=5 mA
mA
MHz
nH
Fi
VDD = 3.3 V
Lpin
7
5
CIN
Logic Inputs
pF
Input Capacitance1
COUT
CINX
Output pin capacitance
X1 & X2 pins
6
pF
27
30
33
pF
PWRSAVE
From Assertion of PWRSAVE# to 1st
clock.
TPWRSV
TSTAB
1.8
1.8
ms
ms
Stabilization1,2
From PowerUp or deassertion of
PowerDown to 1st clock.
Clk Stabilization1,2
t
t
PZH,tPZL Output enable delay (all outputs)
PHZ,tPLZ
1
1
10
10
ns
ns
Delay1
Output disable delay (all outputs)
1Guaranteed by design, not 100% tested in production.
2See timing diagrams for buffered and un-buffered timing requirements.
0708—10/10/02
11
ICS950813
Advance Information
Electrical Characteristics - CPUCLKT/C
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
Current Source Output
Impedance
SYMBOL
Zo1
CONDITIONS
MIN
3000
2.4
TYP
MAX
UNITS
VO = Vx
Ω
Output High Voltage
Output Low Voltage
Voltage High
Voltage Low
Max Voltage
Min Voltage
Crossing Voltage (abs) Vcross(abs)
Crossing Voltage (var) d-Vcross
VOH3
VOL3
IOH = -1 mA
V
IOL = 1 mA
0.4
850
150
VHigh
VLow
Vovs
Vuds
Statistical measurement on single ended
signal using oscilloscope math function.
Measurement on single ended signal
using absolute value.
660
-150
mV
mV
1150
-450
250
550
140
700
mV
mV
ps
Variation of crossing over all edges
VOL = 0.175V, VOH = 0.525V
VOH = 0.525V VOL = 0.175V
Rise Time
Fall Time
tr
tf
175
175
700
125
125
ps
ps
ps
Rise Time Variation
Fall Time Variation
d-tr
d-tf
Duty Cycle
dt3
Measurement from differential wavefrom
45
55
%
Skew
tsk3
VT = 50%
VT = 50%
100
150
ps
ps
1
Jitter, Cycle to cycle
tjcyc-cyc
1Guaranteed by design, not 100% tested in production.
2 IOWT can be varied and is selectable thru the MULTSEL pin.
Electrical Characteristics - 3V66
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise specified)
PARAMETER
Output Frequency
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
FO1
CONDITIONS
MIN
TYP
MAX
55
UNITS
MHz
Ω
1
RDSP1
VO = VDD*(0.5)
12
1
VOH
IOH = -1 mA
2.4
V
1
VOL
IOL = 1 mA
0.55
-33
38
2
V
1
V OH@MIN = 1.0 V, V OH@MAX = 3.135 V
VOL @MIN = 1.95 V, VOL @MAX = 0.4 V
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
-33
30
mA
mA
ns
IOH
1
IOL
1
tr1
0.5
0.5
45
1
Fall Time
tf1
2
ns
1
Duty Cycle
dt1
%
VT = 1.5 V
55
1
Skew
Jitter
tsk1
VT = 1.5 V
250
250
ps
ps
1
tjcyc-cyc
VT = 1.5 V 3V66
1Guaranteed by design, not 100% tested in production.
0708—10/10/02
12
ICS950813
Advance Information
Electrical Characteristics - PCICLK
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise specified)
PARAMETER
Output Frequency
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
FO1
CONDITIONS
MIN
TYP
MAX
55
UNITS
MHz
Ω
1
RDSP1
VO = VDD*(0.5)
12
1
VOH
IOH = -1 mA
IOL = 1 mA
2.4
V
1
VOL
0.55
-33
38
2
V
1
V
OH@MIN = 1.0 V, V OH@MAX = 3.135 V
-33
30
mA
mA
ns
IOH
1
VOL @MIN = 1.95 V, VOL @MAX = 0.4 V
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
IOL
1
tr1
0.5
0.5
45
1
Fall Time
tf1
2
ns
1
Duty Cycle
dt1
%
55
1
Skew
tsk1
VT = 1.5 V
500
250
ps
ps
1
tjcyc-cyc
VT = 1.5 V
Jitter,cycle to cyc
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - VCH, 48MHz DOT, 48MHz, USB
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
Output Frequency
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
48DOT Rise Time
SYMBOL
FO1
CONDITIONS
MIN
TYP
MAX
60
UNITS
MHz
Ω
1
VO = VDD*(0.5)
IOH = -1 mA
20
RDSP1
1
2.4
V
VOH
1
IOL = 1 mA
0.4
-23
27
1
V
VOL
1
V OH@MIN = 1.0 V, V OH@MAX = 3.135 V
VOL @MIN = 1.95 V, VOL @MAX = 0.4 V
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
-29
29
mA
mA
ns
IOH
1
IOL
1
0.5
0.5
tr1
1
48DOT Fall Time
VCH 48 USB Rise
Time
1
ns
tf1
1
VOL = 0.4 V, VOH = 2.4 V
1
2
ns
tr1
1
VCH 48 USB Fall Time
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1
2
ns
%
tf1
1
48 DOT Duty Cycle
dt1
45
55
VCH 48 USB Duty
Cycle
1
VT = 1.5 V
45
55
%
dt1
1
48 DOT Jitter
VT = 1.5 V
VT = 1.5 V (0 OR 180 degrees)
VT = 1.5 V
350
1
ps
ns
ps
tjcyc-cyc
1
USB to DOT Skew
tsk1
1
VCH Jitter
tjcyc-cyc
350
1Guaranteed by design, not 100% tested in production.
0708—10/10/02
13
ICS950813
Advance Information
Electrical Characteristics - REF
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
Output Frequency
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
FO1
CONDITIONS
MIN
TYP
MAX UNITS
MHz
1
RDSP1
VO = VDD*(0.5)
20
60
Ω
V
1
VOH
IOH = -1 mA
2.4
1
VOL
IOL = 1 mA
0.4
-23
27
V
1
V OH@MIN = 1.0 V, V OH@MAX = 3.135 V
VOL @MIN = 1.95 V, VOL @MAX = 0.4 V
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
-29
29
1
mA
mA
ns
ns
%
IOH
1
IOL
1
tr1
2
1
Fall Time
tf1
1
2
1
Duty Cycle
dt1
45
55
1
tjcyc-cyc
VT = 1.5 V
Jitter
1000
ps
1Guaranteed by design, not 100% tested in production.
0708—10/10/02
14
ICS950813
Advance Information
General I2C serial interface information
How to Write:
How to Read:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2 (H)
• ICS clock will acknowledge
• Controller (host) will send start bit.
• Controller (host) sends the write address D2 (H)
• ICS clock will acknowledge
• Controller (host) sends the begining byte location = N
• ICS clock will acknowledge
• Controller (host) sends the begining byte
location = N
• Controller (host) sends the data byte count = X
• ICS clock will acknowledge
• Controller (host) starts sending Byte N through
Byte N + X -1
• ICS clock will acknowledge
• Controller (host) will send a separate start bit.
• Controller (host) sends the read address D3 (H)
• ICS clock will acknowledge
(see Note 2)
• ICS clock will send the data byte count = X
• ICS clock sends Byte N + X -1
• ICS clock sends Byte 0 through byte X (if X(H)
was written to byte 8).
• ICS clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
• Controller (host) will need to acknowledge each
byte
• Controllor (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
Index Block Read Operation
Index Block Write Operation
Controller (Host)
ICS (Slave/Receiver)
Controller (Host)
ICS (Slave/Receiver)
T
starT bit
starT bit
T
Slave Address D2(H)
Slave Address D2(H)
WR
WRite
WR
WRite
ACK
ACK
ACK
ACK
ACK
ACK
Beginning Byte = N
Beginning Byte = N
Data Byte Count = X
Beginning Byte N
RT
Repeat starT
Slave Address D3(H)
RD
ReaD
ACK
Data Byte Count = X
Beginning Byte N
ACK
ACK
Byte N + X - 1
ACK
P
stoP bit
Byte N + X - 1
N
P
Not acknowledge
stoP bit
0708—10/10/02
15
ICS950813
Advance Information
Un-Buffered Mode 3V66 & PCI Phase Relationship
All 3V66 clocks are to be in pphase with each other. In the case where 3V66_1 is configured as 48MHz VCH clock,
there is no defined phase relationship between 3V66_1_VCH and other 3V66 clocks. The PCI group should lag 3V66
by the standard skew described below as Tpci.
3V66 (1:0)
3V66 (4:2)
3V66_5
Tpci
PCICLK_F (2:0) PCICLK (6:0)
E_PCICLK (3,1)
Tepci
Group to Group Skews at Common Transition Edges: Unbuffered Mode
GROUP
3V66 to PCI1,2
SYMBOL
CONDITIONS
MIN
TYP MAX
UNITS
ns
S3V66-PCI
3V66 (5:0) leads 33MHz PCI
1.5
2.55 3.5
1Guarenteed by design, not 100% tested in production.
2500ps Tolerance
E_PCICLK to PCICLK Skews
GROUP
SYMBOL
CONDITIONS
MIN
0.3
TYP MAX
UNITS
ns
E_PCICLK1 (pin 11)=0
E_PCICLK3 (pin 13)=1
E_PCICLK1 (pin 11)=1
E_PCICLK3 (pin 13)=0
E_PCICLK1 (pin 11)=1
E_PCICLK3 (pin 13)=1
TE_PCI-PCI1
0.5
1.0
1.5
0.7
1.2
1.7
E_PCICLK to PCICLK1
TE_PCI-PCI2
TE_PCI-PCI3
0.8
1.3
ns
ns
1Guaranteed by design, not 100% tested in production.
0708—10/10/02
16
ICS950813
Advance Information
PCI_STOP# - Assertion (transition from logic "1" to logic "0")
The impact of asserting the PCI_STOP# signal will be the following.All PCI[6:0] and stoppable PCI_F[2,0] clocks will latch
low in their next high to low transition.The PCI_STOP# setup time tsu is 10 ns, for transitions to be recognized by the next
rising edge.
Assertion of PCI_STOP# Waveforms
PCI_STOP#
PCI_F[2:0] 33MHz
PCI[6:0] 33MHz
tsu
CPU_STOP# - Assertion (transition from logic "1" to logic "0")
The impact of asserting the CPU_STOP# pin is all CPU outputs that are set in the I2C configuration to be stoppable via
assertion of CPU_STOP# are to be stopped after their next transition. When the I2C Bit 6 of Byte 1 is programmed to '0'
the final state of the stopped CPU signals is CPU = High and CPU# = Low. There is to be no change to the output drive
current values.The CPU will be driven high with a current value equal to (Mult 0 'select') x (Iref), the CPU# signal will not
be driven .When the I2C Bit 6 of Byte 1 is programmed to '1' then final state of the stopped CPU signals is Low, both CPU
and CPU# outputs will not be driven.
Assertion of CPU_STOP# Waveforms
CPU_STOP#
CPUCLKT
CPUCLKC
CPU_STOP# Functionality
CPU_STOP#
CPUT
CPUC
1
0
Normal
Normal
Float
iref * Mult
0708—10/10/02
17
ICS950813
Advance Information
CPU_STOP# - De-assertion (transition from logic "0" to logic "1")
All CPU outputs that were stopped are to resume normal operation in a glitch free manner.The maximum latency from the
de-assertion to active outputs is to be defined to be between 2 - 6 CPU clock periods (2 clocks are shown). If the I2C
Bit 6 of Byte 1 is programmed to "1" then the stopped CPU outputs will be driven High within 10 nS of CPU_Stop# de-
assertion.
De-assertion of CPU_STOP# Waveforms
CPU_STOP#
CPUCLKT(2:0)
Tdrive_CPU_STOP# <10ns @ 200mV
*CPUCLKT(2:0)TS
CPUCLKC(2:0)
*Signal TS is CPUCLKT in Tri-State mode
PD# - Assertion (transition from logic "1" to logic "0")
When PWRDWN# is sampled low by two consecutive rising edges of CPU clock, then all clock outputs except CPU clocks
must be held low on their next high to low transitions. When the I2C Bit 6 of Byte 0 is programmed to '0' CPU clocks must
be held with the CPU clock pin driven high with a value of 2 x Iref, and CPU# undriven. If Bit 6 of Byte 0 is '1' then both
CPU and CPU# are undriven. Note the example below shows CPU = 133 MHz and Bit 6 of Byte 0 = '0', this diagram and
description is applicable for all valid CPU frequencies 66, 100, 133, 200 MHz.
Due to the state if the internal logic, stopping and holding the REF clock outputs in the LOW state may require more than
one clock cycle to complete.
Power Down Assertion of Waveforms
0ns
25ns
50ns
PD#
CPUCLKT 100MHz
CPUCLKC 100MHz
3V66MHz
PCICLK 33MHz
USB 48MHz
REF 14.318MHz
PD# Functionality
PD#
PCICLK_F USB/DOT
CPUCLKT CPUCLKC
3V66
PCICLK
48MHz
33MHz
Low
1
0
Normal
Normal
Float
66MHz
Low
48MHz
iref * Mult
Low
0708—10/10/02
18
ICS950813
Advance Information
Power Down De-Assertion Mode
The power-up latency needs to be less than 1.8mS. this is the time from the de-asseration of the powerdown of the ramping
of the power supply until the time that stable clocks are output from the clock chip. If the I2C Bit 6 of Byte 0 is programmed
to "1" then the stopped CPU outputs will be driven high within 3 nS of PD# de-asseration.
Test Configuration Diagram
Rs=33 Ohms
5%
TLA
CLK408
CPUCLKT test
point
Rs=33 Ohms
5%
TLB
CPUCLKC test
point
Rp=49.9 Ohms
1%
Rp=49.9 Ohms
1%
Rset=475 Ohms
1%
2pF
5%
2pF
5%
MULTSEL Pin must be High
CPU 0.7V Configuration test load board termination
0708—10/10/02
19
ICS950813
Advance Information
Shared Pin Operation -
Input/Output Pins
Figure 1 shows a means of implementing this function
when a switch or 2 pin header is used. With no jumper is
installed the pin will be pulled high. With the jumper in
place the pin will be pulled low. If programmability is not
necessary, than only a single resistor is necessary. The
programming resistors should be located close to the
series termination resistor to minimize the current loop
area. It is more important to locate the series termination
resistor close to the driver than the programming resistor.
The I/O pins designated by (input/output) serve as dual
signal functions to the device. During initial power-up,
they act as input pins. The logic level (voltage) that is
present on these pins at this time is read and stored into
a 5-bit internal data latch. At the end of Power-On reset,
(see AC characteristics for timing values), the device
changes the mode of operations for these pins to an
output function. In this mode the pins produce the
specified buffered clocks to external loads.
To program (load) the internal configuration register for
these pins, a resistor is connected to either the VDD
(logic 1) power supply or the GND (logic 0) voltage
potential. A 10 Kilohm (10K) resistor is used to provide
both the solid CMOS programming voltage needed during
the power-up programming period and to provide an
insignificant load on the output clock during the subsequent
operating period.
Via to
VDD
Programming
Header
2K W
Via to Gnd
Device
Pad
8.2K W
Clock trace to load
Series Term. Res.
Fig. 1
0708—10/10/02
20
ICS950813
Advance Information
c
In Millimeters
In Inches
N
SYMBOL
COMMON DIMENSIONS COMMON DIMENSIONS
MIN
2.41
0.20
0.20
0.13
MAX
2.80
0.40
0.34
0.25
MIN
.095
.008
.008
.005
MAX
.110
.016
.0135
.010
L
A
A1
b
E1
E
INDEX
AREA
c
D
E
E1
e
SEE VARIATIONS
SEE VARIATIONS
10.03
7.40
10.68
7.60
.395
.291
.420
.299
1
2
a
hh xx 4455°°
0.635 BASIC
0.025 BASIC
D
h
L
0.38
0.50
0.64
1.02
.015
.020
.025
.040
N
α
SEE VARIATIONS
SEE VARIATIONS
A
0°
8°
0°
8°
A1
VARIATIONS
- CC --
D mm.
D (inch)
N
e
SEATING
PLANE
MIN
18.31
MAX
18.55
MIN
.720
MAX
.730
b
56
.10 (.004)
C
Reference Doc.: JEDEC Publication 95, MO-118
10-0034
300 mil SSOP Package
Ordering Information
ICS950813yFT
Example:
ICS95 XXXX y F - T
Designation for tape and reel packaging
Package Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
DeviceType (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
0708—10/10/02
21
ICS950813
Advance Information
In Millimeters
COMMON DIMENSIONS COMMON DIMENSIONS
In Inches
c
N
SYMBOL
MIN
--
0.05
0.80
0.17
0.09
MAX
1.20
0.15
1.05
0.27
0.20
MIN
--
.002
.032
.007
.0035
MAX
.047
.006
.041
.011
.008
A
A1
A2
b
L
E1
E
INDEX
AREA
c
D
E
SEE VARIATIONS
8.10 BASIC
SEE VARIATIONS
0.319 BASIC
1
22
E1
e
L
6.00
0.50 BASIC
0.45
6.20
.236
0.020 BASIC
.018
.244
a
D
0.75
.030
N
SEE VARIATIONS
SEE VARIATIONS
a
aaa
0°
--
8°
0.10
0°
--
8°
.004
A
A2
VARIATIONS
A1
D mm.
D (inch)
- CC --
N
MIN
MAX
14.10
MIN
.547
MAX
.555
e
SEATING
PLANE
56
13.90
b
Reference Doc.: JEDEC Publication 95, M O-153
aaa
C
10-0039
6.10 mm. Body, 0.50 mm. pitch TSSOP
(20 mil)
(240 mil)
Ordering Information
ICS950813yGT
Example:
ICS95 XXXX y G - T
Designation for tape and reel packaging
Package Type
G=TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS, AV = Standard Device
0708—10/10/02
22
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