ICS951403YFLF-T [ICSI]
AMD-K7 System Clock Chip; AMD- K7系统时钟芯片
| 型号： | ICS951403YFLF-T |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | AMD-K7 System Clock Chip |
| 文件： | 总18页 (文件大小：638K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS951403
Integrated
Circuit
Systems, Inc.
AMD-K7TM System Clock Chip
Recommended Application:
ATI chipset with K7 systems
Output Features:
Pin Configuration
•
3 differential pair open drain CPU clocks (1.5V
external
pull-up; up to 150MHz achieviable through I2C)
•
•
•
•
•
2 - AGPCLK @ 3.3V
8 - PCI @3.3V, including 1 free running
1 - 48MHz @ 3.3V
1 - 24/48MHz @ 3.3V
2- REF @3.3V, 14.318MHz.
Features:
•
•
•
•
•
Programmable ouput frequency
Programmable ouput rise/fall time
Programmable group skew
Real time system reset output
Spread spectrum for EMI control typically
by 7dB to 8dB,
with programmable spread percentage
Watchdog timer technology to reset system
if over-clocking causes malfunction
Uses external 14.318MHz crystal
Asyncronous CPU and SDRAM clocks
CPU and PCI outputs are aligned
CPU - AGP skew <500ps
48-Pin SSOP & TSSOP
* Internal 120K pullup resistor on indicated inputs
** Internal 240K pullup resistor on indicated inputs
•
•
•
•
•
Block Diagram
Functionality
AGP SEL = AGP SEL =
Bit 7 FS2 FS1 FS0
CPU
SDRAM
PCICLK
PLL2
48MHz
0
1
24_48MHz
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
100.00
100.00
100.00
100.00
100.00
133.33
150.00
66.67
33.33
33.33
30.00
33.33
66.67
66.67
60.00
66.67
50.00
50.00
50.00
50.00
/ 2
X1
X2
XTAL
OSC
REF (1:0)
PLL1
Spread
Spectrum
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
133.33
125.00
124.00
133.33
133.33
100.00
124.00
100.00
33.33
31.25
31.00
33.33
66.67
62.50
62.00
66.67
50.00
50.00
46.50
50.00
CPUCLKT (2:0)
CPUCLKC (2:0)
CPU
DIVDER
Stop
3
3
SDRAM
DIVDER
SDRAM_OUT
SEL24_48#
SDATA
1
1
0
0
0
0
0
1
112.00
150.00
112.00
150.00
33.60
30.00
67.20
60.00
56.00
50.00
PCI
DIVDER
Stop
PCICLK (6:0)
PCICLK_F
AGP (1:0)
7
Control
Logic
1
1
1
1
1
1
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
111.11
110.00
166.67
90.00
166.67
165.00
166.67
90.00
33.33
33.00
33.33
30.00
32.00
30.00
66.67
66.00
66.67
60.00
64.00
60.00
55.56
55.00
55.56
45.00
48.00
45.00
SCLK
AGP
DIVDER
FS (2:0)
2
PD#
Config.
Reg.
48.00
48.00
PCI_STOP#
CPU_STOP#
SPREAD#
45.00
60.00
Power Groups
VDD48, GND48 = 48MHz, PLL2
VDDREF, GNDREF= REF, X1, X2
VDD, GND = PLL Core
0486B—02/23/04
ICS951403
General Description
The ICS951403 is a main clock synthesizer chip for AMD-K7 based systems with ATI chipset. This provides all clocks
required for such a system.
The ICS951403 belongs to ICS new generation of programmable system clock generators. It employs serial
programming I2C interface as a vehicle for changing output functions, changing output frequency, configuring output
strength, configuring output to output skew, changing spread spectrum amount, changing group divider ratio and dis/
enabling individual clocks. This device also has ICS propriety 'Watchdog Timer' technology which will reset the
frequency to a safe setting if the system become unstable from over clocking.
Pin Descriptions
PIN NUMBER
PIN NAME
FS (1:0)
TYPE
IN
OUT
DESCRIPTION
Frequency Select pins, has pull-up to VDD
14.318MHz clock output
2,1
REF (1:0)
3, 6, 21, 25,
33, 38, 41, 47
GND
PWR
Ground
XTAL_IN 14.318MHz Crystal input, has internal 33pF
load cap and feed back resistor from X2
4
5
7
X1
X2
IN
OUT
OUT
XTAL_OUT Crystal output, has internal load cap 33pF
Free Running PCI output. Not affected by the
PCI_STOP# input.
PCICLK_F
17, 16, 14, 13, 11, 10,
8
PCICLK (6:0)
OUT
PCI clock outputs. TTL compatible 3.3V
9, 15
18
VDDPCI
VDDAGP
PWR
PWR
Power for PCICLK outputs, nominally 3.3V
Power for AGP outputs, nominally 3.3V
AGP outputs defined as 2X PCI. These may not be
stopped.
20, 19
AGP (1:0)
OUT
34
22
23
VDD
VDD48
48MHz
PWR
PWR
OUT
Isolated power for core, nominally 3.3V
Power for 48MHz and 24MHz outputs nominally 3.3V
48MHz output
Selects 24 or 48MHz output for pin 24
Low = 48MHz High = 24MHz
SEL24-48#
IN
24
24-48MHz
SCLK
SDATA
FS2
OUT
IN
I/O
IN
Fixed clock out selectable through SEL24-48#
Clock pin of I2C circuitry 5V tolerant
26
27
28
Data pin for I2C circuitry 5V tolerant
Frequency Select pin, has pull-up to VDD
Enables Spread Spectrum feature when LOW. Down
Spread 0.5% modulation frequency =50KHz
Powers down chip, active low. Internal PLL & all outputs
are disabled.
29
30
SPREAD#
PD#
IN
IN
Halts CPUCLKs. CPUCLKT is driven LOW wheras
CPUCLKC is driven HIGH when this pin is asserted
(Active LOW).
31
CPU_STOP#
IN
Halts PCI Bus at logic "0" level when driven low.
PCICLK_F is not affected by this pin
Real time system reset signal for watchdog tmer
timeout. This signal is active low.
Reference clock for SDRAM zero delay buffer
Future CPU power rail
32
35
PCI_STOP#
RESET#
IN
OUT
46
44
SDRAM_OUT
RESERVED
OUT
N/C
"True" clocks of differential pair CPU outputs. These open
drain outputs need an external 1.5V pull-up.
"Complementary" clocks of differental pair CPU output.
These open drain outputs need an external 1.5V pull_up.
42, 39, 36
43, 40, 37
CPUCLKT (2:0)
CPUCLKC (2:0)
OUT
OUT
45
48
VDDSD
VDDREF
PWR
PWR
Power for SDRAM_OUT pin. Norminally 3.3V
Power for REF, X1, X2, nominally 3.3V
0486B—02/23/04
2
ICS951403
Bit
Description
AGP
PWD
Bit 6 Bit 5 Bit 4
FS2 FS1 FS0
AGP
Bit 2 Bit 7
CPU
SDRAM
PCI
Spread Precentage
SEL = 0 SEL = 1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
100.00 100.00 33.33
100.00 133.33 33.33
100.00 150.00 30.00
66.67
66.67
60.00
66.67
67.67
62.50
62.00
66.67
67.20
60.00
66.67
66.00
66.67
60.00
64.00
60.00
66.87
66.87
63.00
66.87
66.00
68.67
68.67
66.87
66.87
70.00
68.67
68.67
70.00
69.17
66.67
69.50
50.00
50.00
50.00
50.00
50.00
50.00
46.50
50.00
56.00
50.00
55.56
55.00
55.56
45.00
48.00
45.00
50.15
50.15
52.50
50.15
55.00
51.50
51.50
50.15
50.15
52.50
51.50
51.50
52.50
51.88
50.00
52.13
0 to -0.5% Down Spread
0 to -0.5% Down Spread
+/- 0.25% Center Spread
0 to -0.5% Down Spread
0 to -0.5% Down Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
0 to -0.5% Down Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
100.00
66.67
33.33
133.33 133.33 33.33
125.00 100.00 31.25
124.00 124.00 31.00
133.33 100.00 33.33
112.00 112.00 33.60
150.00 150.00 30.00
111.11 166.67 33.33
110.00 165.00 33.00
166.67 166.67 33.33
0000-
0
Note1
90.00
48.00
45.00
90.00
48.00
60.00
30.00
32.00
30.00
Bit 2
Bit 7:4
100.30 100.30 33.43
100.30 133.73 33.43
105.00 157.50 31.50
100.30 66.87
33.43
110.00 110.00 33.00
103.00 103.00 34.33
103.00 137.33 34.33
133.73 100.30 33.43
133.73 133.73 33.43
140.00 140.00 35.00
137.33 103.00 34.33
137.33 137.33 34.33
105.00 105.00 35.00
138.33 138.33 34.58
200.00 200.00 33.33
104.25 139.00 34.75
0 - Frequency is selected by hardware select, Latched Inputs
Bit 3
Bit 1
Bit 0
0
0
0
1 - Frequency is selected by Bit , 2 7:4
0 - Normal
1 - Spread Spectrum Enabled
0 - Running
1- Tristate all outputs
Note1:
Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
Note: PWD = Power-Up Default
0486B—02/23/04
3
ICS951403
Byte 1: Output Control Register
(1= enable, 0 = disable)
Byte 2: PCI Stop Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
SEL 24/48
0 = 24MHz 1= 48MHz
BIT PIN# PWD
DESCRIPTION
PCICLK_F
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
7
1
1
1
1
1
1
1
1
Bit 7
24
1
17
16
14
13
11
10
8
PCICLK6
PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
37
36
40
39
43
42
46
1
1
1
1
1
1
1
CPUCLKC0
CPUCLKT0
CPUCLKC1
CPUCLKT1
CPUCLKC2
CPUCLKT2
SDRAM_OUT
Byte 3: CPU Free Running Control Register
(1= enable, 0 = disable)
Byte 4: 24/48MHz Control Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
Reserved
BIT PIN# PWD
DESCRIPTION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
X
X
X
X
0
7
6
5
4
3
2
-
24
-
1
1
1
1
1
1
Reserved
24-48MHz
48MHz
Reserved
-
Reserved
-
-
-
-
-
Reserved
-
Reserved
Reserved
Reserved
Reserved
-
0
CPU T/C 0
CPU T/C 1
CPU T/C 2
-
AGP frequency select
0 = 66.6MHz 1 = 50.0MHz
0
1
0
-
-
0
1
0
Reserved
Byte 5: Clock Enable Control Register
(1= enable, 0 = disable)
Byte 6: Control Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
BIT PIN# PWD
DESCRIPTION
7
-
0
REF strength 0 = 1X 1 = 2X
7
6
5
4
3
2
1
0
-
X
X
X
X
1
Reserved
FS2 Read-back
FS1 Read-back
FS0 Read-back
REF1
0 = CPU C1:2, T1:2 stop
1 = CPU C1:2, T1:2 free running
6
-
0
5
-
-
-
-
-
-
0
X
X
X
X
0
Reserved
4
SPREAD# read-back
CPU_STOP# read-back
PCI_STOP# read-back
Reserved
1
2
3
1
REF0
2
20
19
1
AGP1
1
0
1
AGP0
AGP speed toggle
Notes:
Notes:
1. Inactive means outputs are held LOW and are disabled
3. Bytes 7:14 not defined.
from switching.
2. Latched Frequency Selects (FS#) will be inverted logic
load of the input frequency select pin conditions.
0486B—02/23/04
4
ICS951403
Byte 15: CPU_SDRAM Skew Register
Byte 16: Slew Rate Control Register
Bit
PWD
Description
Bit
PWD
Description
SDRAM (pdel canned)
-
-
-
-
-
-
-
-
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
0
0
1
1
1
1
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
CPUC0 & T0 (pdel canned)
CPUC 1:2 & T 1:2 (pdel canned)
Byte 17: Slew Rate Control Register
Byte 18: Slew Rate Control Register
Bit
PWD
Description
PCI (3:0) Slew Control
Bit
PWD
Description
PCI (4:7) Slew Control
1
0
1
0
1
0
1
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
0
1
0
1
0
1
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PCI_F Slew Control
AGP1 Slew Control
AGP0 Slew Control
Reserved
CPUCLKC0 Slew Control
CPUCLKT0 Slew Control
Byte 20: Slew Rate Control Register
Byte 19: Slew Rate Control Register
Bit
PWD
Description
Bit
PWD
Description
48MHz Slew Control
1
0
1
0
1
0
1
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
0
1
0
1
0
1
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CPUCLKC1 Slew Control
CPUCLKT1 Slew Control
CPUCLKC2 Slew Control
CPUCLKT2 Slew Control
24, 48MHz Slew Control
REF0 Slew Control
REF1 Slew Control
SDRAM Slew Control
Notes:
1. PWD = Power on Default
0486B—02/23/04
5
ICS951403
VCO Programming Constrains
VCO Frequency ...................... 150MHz to 500MHz
VCO Divider Range ................ 8 to 519
REF Divider Range ................. 2 to 129
Phase Detector Stability .......... 0.3536 to 1.4142
Useful Formula
VCO Frequency = 14.31818 x VCO/REF divider value
Phase Detector Stabiliy = 14.038 x (VCO divider value)-0.5
To program theVCO frequency for over-clocking.
0. Before trying to program our clock manually, consider using ICS provided software utilities for easy
programming.
1. Select the frequency you want to over-clock from with the desire gear ratio (i.e. CPU:SDRAM:3V66:PCI ratio) by
writing to byte 0, or using initial hardware power up frequency.
2.Write 0001, 1001 (19H) to byte 8 for readback of 21 bytes (byte 0-20).
3. Read back byte 11-20 and copy values in these registers.
4. Re-initialize the write sequence.
5. Write a '1' to byte 9 bit 7 and write to byte 11 & 12 with the desired VCO & REF divider values.
6. Write to byte 13 to 20 with the values you copy from step 3. This maintains the output spread, skew and slew
rate.
7.The above procedure is only needed when changing the VCO for the 1st pass. If VCO frequency needed to be
changed again, user only needs to write to byte 11 and 12 unless the system is to reboot.
Note:
1. User needs to ensure step 3 & 7 is carried out. Systems with wrong spread percentage and/or group to group skew
relation programmedintobytes13-16couldbeunstable. Step3&7assurethecorrectspreadandskewrelationship.
2. If VCO, REF divider values or phase detector stability are out of range, the device may fail to function correctly.
3.Follow min and maxVCO frequency range provided. Internal PLL could be unstable ifVCO frequency is too fast or
too slow. Use 14.31818MHz x VCO/REF divider values to calculate the VCO frequency (MHz).
4.ICS recommends users, to utilize the software utility provided by ICS Application Engineering to program theVCO
frequency.
5.Spread percent needs to be calculated based onVCO frequency, spread modulation frequency and spreadamount
desired. See Application note for software support.
0486B—02/23/04
6
ICS951403
Absolute Maximum Ratings
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of the device at these or any other conditions above those
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Volt age VDD = 3.3 V +/-5% (unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input Low Current
SYMBOL
VIH
CONDITIONS
MIN
2
VSS - 0.3
TYP
MAX
VDD + 0.3
0.8
UNITS
V
V
A
uA
uA
VIL
IIH
IIL1
IIL2
IDD3.3OP
PD
Fi
CIN
VIN = VDD
5
VIN=0 V; Inputs with no pull-up resistors
VIN=0 V; Inputs with pull-up resistors
CL = Full load
-5
-200
Supply Current
Power Down
Input frequency
213
0.07
14.318
240
0.6
16
5
5
45
3
mA
mA
MHz
VDD = 3.3 V;
12
27
Logic Inputs
Logic Inputs
X1 & X2 pins
pF
pF
pF
ms
ps
ps
ps
Input Capacitance1
CIN
CINX
Clk Stabilization1
Skew1
TSTAB
tCPU-SDRAM
tCPU-PCI
From VDD= 3.3 V to 1% target Freq.
CPU Xover to SDRAM 1.5V
CPU Xover to PCI 1.5V
CPU Xover to AGP 1.5V
68
250
250
500
Skew1
186
138
Skew1
tCPU-AGP
1 Guaranteed by design, not 100% tested in production.
0486B—02/23/04
7
ICS951403
Electrical Characteristics - REF
TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified)
PARAMETER
Output High
Voltage
SYMBOL
CONDITIONS
MIN
2.4
TYP
MAX
UNITS
V
VOH5
IOH = -18mA
VOL5
IOH5
IOL5
IOL = 18mA
V OH = 2.0 V,
VOL = 0.8V
Output Low Voltage
Output High Current
Output Low Current
0.4
-19
V
mA
mA
19
45
tr5
tf5
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 50%
Rise Time
Fall Time
Duty Cycle
Jitter
0.85
1.03
54
4
4
ns
ns
%
1
55
dt1
tjcyc-cyc5
VT = 1.5 V
521
1000
ps
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - CPU (Open Drain)
TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 2pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
MIN
1
TYP
MAX
UNITS
VO = Vx
Output Impedance
Zo
Ω
Output High
Voltage
Output Low
VOH2B
VOL2B
Termination to Vpull_up (external)
Termination to Vpull_up (external)
1.2
0.4
V
Voltage
Output Low
Current
Fall Time
IOL2B
tf2B
VOL = 0.3V
18
mA
ps
VOH = 1.2V VOL = 0.3V
0.8
0.9
Vtpullup
Differential
voltage_AC
VDIF
(external)+0
Note 2
ps
.6
Vtpullup
(external)+0
.6
Differential
voltage_DC
VDIF
VX
Note 2
ps
V
Differential
Crossover Voltage
Duty Cycle
True rise to compl. Fall
1.37
1.5
dt2B
tsk2B
VT = 50%
VT = 50%
45
49.3
48
55
200
%
ps
Skew
1
VT = Vx
Jitter, Cycle to cycle
130
250
ps
tjcyc-cyc
1Guaranteed by design, not 100% tested in production.
2 VDIF specifies the minimum input differential voltages (VTR-VCP) required for switching, where VTR is the "true"
input level and VCP is the "complement" input level.
0486B—02/23/04
8
ICS951403
Electrical Characteristics - PCICLK
TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified)
PARAMETER
Output High
Voltage
SYMBOL
CONDITIONS
MIN
2.6
TYP
MAX
UNITS
V
1
IOH = -11mA
VOH
1
IOL = 9.4mA
V OH = 2.0 V,
VOL = 0.8V
Output Low Voltage
Output High Current
Output Low Current
0.4
-19
V
VOL
1
mA
mA
IOH
1
19
45
IOL
1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 50%
Rise Time
Fall Time
Duty Cycle
Skew
1.29
1.02
51.5
54
2
2
ns
ns
%
tr1
1
tf1
1
55
dt1
1
VT = 50%
200
250
ps
ps
tsk1
1
VT = 1.5 V
Jitter
104
tjcyc-cyc
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - 24MHz,48MHz
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
SYMBOL
VOH5
VOL5
IOH5
CONDITIONS
IOH = -18mA
IOL = 18mA
VOH = 2.0 V
VOL = 0.8 V
MIN
2.4
TYP
MAX
UNITS
V
0.4
-22
V
mA
mA
ns
IOL5
16
45
tr5
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
1.2
1.3
4
4
Fall Time1
tf5
ns
Duty Cycle1
dt5
tjcyc_cyc2B
VT = 1.5V
VT = 1.5V
50.5
130
55
500
%
ps
Jitter, Cycle to cycle
1Guaranteed by design, not 100% tested in production.
0486B—02/23/04
9
ICS951403
Electrical Characteristics - AGP [1:0]
TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified)
PARAMETER
Output High
Voltage
SYMBOL
CONDITIONS
MIN
2.4
TYP
MAX
UNITS
V
1
IOH = -18mA
VOH
1
IOL = 18mA
V OH = 2.0 V,
VOL = 0.8V
Output Low Voltage
Output High Current
Output Low Current
0.4
-19
V
VOL
1
mA
mA
IOH
1
19
45
IOL
1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 50%
Rise Time
Fall Time
Duty Cycle
Skew
0.98
0.85
48.5
4
1.6
1.6
55
ns
ns
%
tr1
1
tf1
1
dt1
1
VT = 50%
250
500
ps
ps
tsk1
1
VT = 1.5 V
Jitter
235
tjcyc-cyc
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - SDRAM_OUT
TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified)
PARAMETER
Output High
Voltage
SYMBOL
CONDITIONS
MIN
2
TYP
MAX
UNITS
V
VOH3
IOH = -11mA
VOL3
IOH3
IOL3
IOL = 11mA
V OH = 2.0 V,
VOL = 0.8V
Output Low Voltage
Output High Current
Output Low Current
0.4
-12
V
mA
mA
12
45
3
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 50%
Rise Time
Fall Time
Duty Cycle
Jitter
0.96
0.75
49.5
235
1.6
1.6
55
ns
ns
%
tr3
3
tf3
3
dt3
3
VT = 1.5 V
250
ps
tjcyc-cyc
1Guaranteed by design, not 100% tested in production.
0486B—02/23/04
10
ICS951403
General I2C serial interface information for the ICS951403
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2 (H)
• ICS clock will acknowledge
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the read address D3 (H)
• ICS clock will acknowledge
• Controller (host) sends a dummy command code
• ICS clock will acknowledge
• ICS clock will send the byte count
• Controller (host) acknowledges
• Controller (host) sends a dummy byte count
• ICS clock will acknowledge
• Controller (host) starts sending Byte 0 through Byte 20
(see Note)
• ICS clock sends Byte 0 through byte 8 (default)
• ICS clock sends Byte 0 through byte X (if X(H) was
written to byte 8).
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a stop bit
• ICS clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
How to Write:
How to Read:
Controller (Host)
Start Bit
ICS (Slave/Receiver)
Controller (Host)
Start Bit
ICS (Slave/Receiver)
Address D2(H)
Address D3(H)
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Byte Count
Dummy Command Code
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Dummy Byte Count
Byte 0
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
ACK
Byte 6
If 7H has been written to B6
Byte 7
ACK
Byte 18
Byte 19
Byte 20
Stop Bit
ACK
ACK
ACK
If 12H has been written to B6
Byte18
Byte 19
Byte 20
ACK
If 13H has been written to B6
ACK
If 14H has been written to B6
ACK
Stop Bit
*See notes on the following page.
0486B—02/23/04
11
ICS951403
Brief I2C registers description for ICS951403
Programmable System Frequency Generator
Register Name
Byte
Description
PWD Default
Output frequency, hardware / I2C
frequency select, spread spectrum &
output enable control register.
Functionality &
Frequency Select
Register
See individual
byte
description
See individual
byte
0
Active / inactive output control
registers/latch inputs read back.
Output Control Registers
1-6
7
description
Byte 11 bit[7:4] is ICS vendor id -
1001. Other bits in this register
designate device revision ID of this
part.
See individual
byte
description
Vendor ID & Revision ID
Registers
Writing to this register will configure
byte count and how many byte will
be read back. Do not write 00H to
this byte.
Writing to this register will configure
the number of seconds for the
watchdog timer to reset.
Byte Count
Read Back Register
8
9
08H
10H
Watchdog Timer
Count Register
Watchdog enable, watchdog status
10 Bit [6:0] and programmable 'safe' frequency'
can be configured in this register.
Watchdog Control
Registers
000,0000
This bit select whether the output
VCO Control Selection
Bit
frequency is control by
hardware/byte 0 configurations or
10 Bit [7]
0
byte 11&12 programming.
These registers control the dividers
ratio into the phase detector and
thus control the VCO output
frequency.
Depended on
hardware/byte
0 configuration
VCO Frequency Control
Registers
11-12
Depended on
hardware/byte
0 configuration
Spread Spectrum
Control Registers
These registers control the spread
percentage amount.
13-14
Increment or decrement the group
skew amount as compared to the
initial skew.
See individual
byte
description
See individual
byte
Group Skews Control
Registers
15-16
17-20
Output Rise/Fall Time
Select Registers
These registers will control the
output rise and fall time.
description
Notes:
1.
The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches
for verification. Readback will support standard SMBUS controller protocol. The number of bytes to
readback is defined by writing to byte 8.
2.
When writing to byte 11 - 12, and byte 13 - 14, they must be written as a set. If for example, only byte
14 is written but not 15, neither byte 14 or 15 will load into the receiver.
3.
4.
5.
6.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I2C interface, the protocol is set to use only Block-Writes from the
controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to
stop after any complete byte has been transferred. The Command code and Byte count shown above must
be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued.
At power-on, all registers are set to a default condition, as shown.
7.
0486B—02/23/04
12
ICS951403
Shared Pin Operation -
Input/Output Pins
Figure 1 shows a means of implementing this function
when a switch or 2 pin header is used. With no jumper is
installed the pin will be pulled high. With the jumper in
place the pin will be pulled low. If programmability is not
necessary, than only a single resistor is necessary. The
programming resistors should be located close to the
series termination resistor to minimize the current loop
area. It is more important to locate the series termination
resistor close to the driver than the programming resistor.
The I/O pins designated by (input/output) serve as dual
signal functions to the device. During initial power-up,
they act as input pins. The logic level (voltage) that is
present on these pins at this time is read and stored into
a 5-bit internal data latch. At the end of Power-On reset,
(see AC characteristics for timing values), the device
changes the mode of operations for these pins to an
output function. In this mode the pins produce the
specified buffered clocks to external loads.
To program (load) the internal configuration register for
these pins, a resistor is connected to either the VDD
(logic 1) power supply or the GND (logic 0) voltage
potential. A 10 Kilohm (10K) resistor is used to provide
both the solid CMOS programming voltage needed during
the power-up programming period and to provide an
insignificant load on the output clock during the subsequent
operating period.
Fig. 1
0486B—02/23/04
13
ICS951403
CPU_STOP# Timing Diagram
CPU_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPUCLKs for low power
operation. CPU_STOP# is synchronized by the ICS951403. All other clocks will continue to run while the CPUCLKs
clocks are disabled. The CPUCLKs will always be stopped in a low state and start in such a manner that guarantees
the high pulse width is a full pulse. CPUCLK on latency is less than 4 CPUCLKs and CPUCLK off latency is less than
4 CPUCLKs.
INTERNAL
CPUCLK
PCICLK
CPU_STOP#
PD# (High)
CPUCLKT
CPUCLKC
Notes:
1. All timing is referenced to the internal CPUCLK.
2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is
synchronized to the CPUCLKs inside the ICS951403.
3. All other clocks continue to run undisturbed.
4. PD# and PCI_STOP# are shown in a high (true) state.
0486B—02/23/04
14
ICS951403
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS951403. It is used to turn off the PCICLK clocks for low power operation.
PCI_STOP# is synchronized by the ICS951403 internally. PCICLK clocks are stopped in a low state and started with
a full high pulse width guaranteed. PCICLK clock on latency cycles are only one rising PCICLK clock off latency is one
PCICLK clock.
CPUCLK
(Internal)
PCICLK
(Internal)
PCICLK
(Free-runningl)
CPU_STOP#
PCI_STOP#
PWR_DWN#
PCICLK
(External)
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS951403 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS951403.
3. All other clocks continue to run undisturbed.
4. PD# and CPU_STOP# are shown in a high (true) state.
0486B—02/23/04
15
ICS951403
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part.
PD# is an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering
down the clock synthesizer.
Internal clocks are not running after the device is put in power down.When PD# is active low all clocks need to be driven
to a low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than 3 mS.
The power down latency should be as short as possible but conforming to the sequence requirements shown below.
PCI_STOP# and CPU_STOP# are considered to be don't cares during the power down operations.The REF and 48MHz
clocks are expected to be stopped in the LOW state as soon as possible. Due to the state of the internal logic, stopping
and holding the REF clock outputs in the LOW state may require more than one clock cycle to complete.
PD#
CPUCLKT
CPUCLKC
PCICLK
VCO
Crystal
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS951403 device).
2. As shown, the outputs Stop Low on the next falling edge after PD# goes low.
3. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part.
4. The shaded sections on the VCO and the Crystal signals indicate an active clock.
5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz.
0486B—02/23/04
16
ICS951403
c
N
In Millimeters
In Inches
SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS
L
MIN
2.41
0.20
0.20
0.13
MAX
2.80
0.40
0.34
0.25
MIN
.095
.008
.008
.005
MAX
.110
.016
.0135
.010
A
A1
b
E1
E
INDEX
AREA
c
D
E
E1
e
SEE VARIATIONS
SEE VARIATIONS
1
2
10.03
7.40
10.68
7.60
.395
.291
.420
.299
a
hh xx 4455°°
D
0.635 BASIC
0.025 BASIC
h
L
0.38
0.50
0.64
1.02
.015
.020
.025
.040
N
α
SEE VARIATIONS
SEE VARIATIONS
A
0°
8°
0°
8°
A1
VARIATIONS
- CC --
D mm.
D (inch)
N
e
SEATING
PLANE
MIN
15.75
MAX
16.00
MIN
.620
MAX
b
48
.630
.10 (.004)
C
Reference Doc.: JEDEC Publication 95, MO-118
10-0034
300 mil SSOP Package
Ordering Information
ICS951403yFLF-T
Example:
ICS XXXX y F LF- T
Designation for tape and reel packaging
Lead Free (Optional)
Package Type
F = SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
0486B—02/23/04
17
ICS951403
c
6.10 mm. Body, 0.50 mm. Pitch TSSOP
N
(240 mil)
In Millimeters
(20 mil)
In Inches
L
SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS
MIN
--
0.05
0.80
0.17
0.09
MAX
1.20
0.15
1.05
0.27
0.20
MIN
--
.002
.032
.007
.0035
MAX
.047
.006
.041
.011
.008
A
A1
A2
b
E1
E
INDEX
AREA
c
D
E
E1
e
SEE VARIATIONS
8.10 BASIC
SEE VARIATIONS
0.319 BASIC
1
22
a
6.00
6.20
.236
.244
D
0.50 BASIC
0.020 BASIC
L
0.45
0.75
.018
.030
N
SEE VARIATIONS
SEE VARIATIONS
a
aaa
0°
--
8°
0.10
0°
--
8°
.004
A
A2
A1
VARIATIONS
- CC --
D mm.
D (inch)
N
e
SEATING
PLANE
MIN
12.40
MAX
12.60
MIN
.488
MAX
.496
b
48
aaa
C
Reference Doc.: JEDEC Publication 95, MO-153
10-0039
Ordering Information
ICS951403yGLF-T
Example:
ICS XXXX y G LF- T
Designation for tape and reel packaging
Lead Free (Optional)
Package Type
G = TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
0486B—02/23/04
18
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