ICS951901YFLF-T [ICSI]
Programmable Frequency Generator & Integrated Buffers for Pentium III Processor; 可编程频率发生器和缓冲器集成的奔腾III处理器
| 型号： | ICS951901YFLF-T |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Programmable Frequency Generator & Integrated Buffers for Pentium III Processor |
| 文件： | 总19页 (文件大小：180K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS951901
Integrated
Circuit
Systems, Inc.
Programmable Frequency Generator & Integrated Buffers for Pentium III Processor
Recommended Application:
Pin Configuration
Single chip clock solution for IA platform.
VDDA
(AGPSEL)REF0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDDL
1
Output Features:
*
CPUCLK0
CPUCLK1
CPUCLK2
GND
VDDSDR
SDRAM0
SDRAM1
SDRAM2
GND
SDRAM3
SDRAM4
SDRAM5
VDDSDR
SDRAM6
SDRAM7
GND
SDRAM8/PD#
SDRAM9/SDRAM_STOP#
GND
SDRAM10/PCI_STOP#
SDRAM11/CPU_STOP#
SDRAM12
VDDSDR
1
*(FS3)REF1
•
•
•
•
•
•
3 - CPU @ 2.5V
GND
X1
X2
13 - SDRAM @ 3.3V
6 - PCI @3.3V,
VDDPCI
*(FS1)PCICLK_F
*(FS2)PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4
GND
2 - AGP @ 3.3V
1 - 48MHz, @3.3V fixed.
1 - 24/48MHz, @3.3V selectable by I2C
(Default is 24MHz)
•
2 - REF @3.3V, 14.318MHz.
VDDAGP
AGPCLK0
AGPCLK1
GND
Features:
•
Programmable ouput frequency.
•
•
•
Programmable ouput rise/fall time.
Programmable SDRAM and CPU skew.
Spread spectrum for EMI control typically
by 7dB to 8dB,
GND
*(FS0)48MHz
*(MODE)24_48MHz
VDD48
SDATA
SCLK
with programmable spread percentage.
Watchdog timer technology to reset system
if over-clocking causes malfunction.
Uses external 14.318MHz crystal.
FS pins for frequency select
•
48-Pin 300mil SSOP
•
•
* These inputs have a 120K pull down to GND.
1 These are double strength.
Skew Specifications:
•
•
•
•
CPU - CPU: < 175ps
SDRAM - SDRAM < 250ps (except SDRAM12)
PCI - PCI: < 500ps
CPU (early) - PCI: 1-4ns (typ. 2ns)
Block Diagram
Functionality
SDRAM
MHz
FS3
Bit7
FS2
Bit6
FS1
Bit5
FS0
Bit4 MHz
CPU
PCI
MHz
AGP1
SEL=1
AGP0
SEL=0
PLL2
48MHz
Bit2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
66.67
66.67
66.67
75.00
83.31
90.00
95.00
100.00
66.67
100.00
133.34
75.00
83.31
90.00
95.00
66.67
33.33
33.33
33.33
37.50
33.32
30.00
31.67
33.33
33.33
33.33
35.00
33.60
35.40
31.02
33.33
33.33
66.67
66.67
66.67
75.00
66.64
60.00
63.33
66.67
66.67
66.67
70.00
67.20
70.80
62.05
66.67
66.67
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
24_48MHz
/ 2
X1
X2
XTAL
OSC
REF(1:0)
2
3
PLL1
Spread
Spectrum
CPU
DIVDER
Stop
CPUCLK (2:0)
SDRAM (12:0)
SDRAM
DIVDER
100.00 100.00
100.00 133.34
105.00 105.00
112.00 112.00
117.99 117.99
124.09 124.09
133.34 100.00
133.34 133.34
Stop
Stop
13
5
SDATA
SCLK
Control
Logic
PCI
DIVDER
PCICLK (4:0)
PCICLK_F
AGP (1:0)
FS(3:0)
PD#
AGP
DIVDER
PCI_STOP#
CPU_STOP#
SDRAM_STOP#
MODE
2
Config.
Reg.
AGP_SEL
0670B—07/15/04
ICS951901
Power Groups
Analog
VDDA = X1, X2, Core, PLL
VDD48 = 48MHz, 24MHz, fixed PLL
Digital
General Description
The ICS951901 is a single chip clock solution for desktop
designs using 630S chipsets. It provides all necessary
clock signals for such a system.
VDDPCI = PCICLK_F, PCICLK
VDDSDR = SDRAM
VDDAGP=AGP, REF
The ICS951901 belongs to ICS new generation of
programmable system clock generators. It employs serial
programming I2C interface as a vehicle for changing
output functions, changing output frequency, configuring
output strength, configuring output to output skew, changing
spread spectrum amount, changing group divider ratio and
dis/enabling individual clocks. This device also has ICS
propriety 'Watchdog Timer' technology which will reset the
frequency to a safe setting if the system becomes
unstable from over clocking.
MODE Pin Power Management Control Input
MODE
Pin 21
Pin 27
Pin 28
Pin 30
Pin 31
SDRAM8
PD#
0
SDRAM11
SDRAM10
SDRAM9
1
CPU_STOP# PCI_STOP# SDRAM_STOP#
Pin Configuration
PIN NUMBER
1, 7, 15, 22, 25,
35, 43
PIN NAME
TYPE
DESCRIPTION
3.3V Power supply for SDRAM output buffers, PCI output buffers,
reference output buffers and 48MHz output
AGP frequency select pin.
VDD
PWR
AGPSEL
REF0
FS3
IN
2
3
OUT
IN
14.318 MHz reference clock.
Frequency select pin.
REF1
OUT
14.318 MHz reference clock.
4, 14, 18, 19, 29,
GND
PWR
Ground pin for 3V outputs.
32, 39, 44
5
6
X1
X2
IN
Crystal input,nominally 14.318MHz.
Crystal output, nominally 14.318MHz.
Frequency select pin.
OUT
IN
FS1
8
9
PCICLK_F
FS2
OUT
IN
PCI clock output, not affected by PCI_STOP#
Frequency select pin.
PCICLK0
PCICLK (4:1)
AGP (1:0)
FS0
OUT
OUT
OUT
IN
PCI clock output.
13, 12, 11, 10
17, 16,
PCI clock outputs.
AGP outputs defined as 2X PCI. These may not be stopped.
Frequency select pin.
20
48MHz
OUT
48MHz output clock
Pin 27, 28, 30, & 31 function select pin
0=Desktop 1=Mobile mode
MODE
IN
21
24_48MHz
SDATA
OUT
I/O
Clock output for super I/O/USB default is 24MHz
Data pin for I2C circuitry 5V tolerant
Clock pin of I2C circuitry 5V tolerant
23
24
SCLK
IN
Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level,
when input is low and MODE pin is in Mobile mode
SDRAM clock output
CPU_STOP#
SDRAM11
IN
OUT
IN
27
28
30
Stops all CPUCLKs clocks at logic 0 level, when input is low and
MODE pin is in Mobile mode
SDRAM clock output
PCI_STOP#
SDRAM10
SDRAM9
OUT
OUT
SDRAM clock output
Stops all SDRAM clocks at logic 0 level, when input is low and
SDRAM_STOP#
IN
MODE pin is in Mobile mode
Asynchronous active low input pin used to power down the device
into a low power state. The internal clocks are disabled and the
VCO and the crystal are stopped. The latency of the power down will
PD#
IN
31
SDRAM clock output
SDRAM8
OUT
OUT
26 33, 34, 36,
37, 38, 40, 41,
42
SDRAM (12,
7:0)
SDRAM clock outputs
45, 46, 47
CPUCLK (2:0)
VDDL
OUT
PWR
CPU clock outputs.
48
Power pin for the CPUCLKs. 2.5V
0670B—07/15/04
2
ICS951901
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default = 0)
Description
FS3
Bit7
FS2
Bit6
FS1
Bit5
FS0
Bit4
CPU
MHz
SDRAM
MHz
PCI
MHz
AGP1
SEL=1
AGP0
SEL=0
Spread %
PWD
Bit2
0
0
0
0
0
0
0
0
Bit
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
66.67
66.67
66.67
75.00
83.31
90.00
95.00
100.00
100.00 100.00
100.00 133.34
105.00 105.00
112.00 112.00
117.99 117.99
124.09 124.09
133.34 100.00
133.34 133.34
75.00
75.00
75.00
83.31
83.32
90.00
90.00
95.00
95.00
105.00
66.67
100.00
133.34
75.00
83.31
90.00
95.00
66.67
33.33
33.33
33.33
37.50
33.32
30.00
31.67
33.33
33.33
33.33
35.00
33.60
35.40
31.02
33.33
33.33
37.50
32.14
32.14
33.32
31.25
30.00
30.00
31.67
31.67
35.00
35.00
33.60
35.40
31.02
32.50
35.00
66.67
66.67
66.67
75.00
66.64
60.00
63.33
66.67
66.67
66.67
70.00
67.20
70.80
62.05
66.67
66.67
75.00
64.29
64.29
66.64
62.49
60.00
60.00
63.33
63.33
70.00
70.00
67.20
70.80
62.05
64.99
70.00
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
± 0.35% center spread
± 0.35% center spread
± 0.35% center spread
± 0.35% center spread
± 0.35% center spread
± 0.35% center spread
± 0.35% center spread
± 0.35% center spread
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
± 0.35% center spread
± 0.35% center spread
± 0.35% center spread
± 0.35% center spread
± 0.35% center spread
± 0.35% center spread
± 0.35% center spread
± 0.35% center spread
Bit 2
Bit 7:4
00000
Note1
100.00
112.50
150.00
111.07
166.65
60.00
120.00
63.33
126.66
70.00
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
± 0.35% center spread
± 0.35% center spread
± 0.35% center spread
± 0.35% center spread
± 0.35% center spread
± 0.35% center spread
± 0.35% center spread
± 0.35% center spread
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
± 0.35% center spread
± 0.35% center spread
± 0.35% center spread
± 0.35% center spread
± 0.35% center spread
± 0.35% center spread
± 0.35% center spread
± 0.35% center spread
105.00 140.00
112.00
117.99
124.09
129.99
84.00
88.49
93.07
97.49
140.00 105.00
Bit 3
Bit 1
Bit 0
0 - Frequency is selected by hardware select, Latched inputs
1 - Frequency is selected by Bit, 2 7:4
0 - Normal
1 - Spread Spectrum Enabled
0 - Running
0
1
0
1 - Tristate all outputs
Note1:
Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
Note: PWD = Power-Up Default
I2C is a trademark of Philips Corporation
0670B—07/15/04
3
ICS951901
Byte 2: PCI, Active/Inactive Register
(1= enable, 0 = disable)
Byte 1: CPU, Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
BIT
PIN# PWD
DESCRIPTION
Sel24_48
(1:24MHz, 0:48MHz)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
1
1
1
1
1
1
1
1
Reserved
Reserved
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0
PCICLK_F
Bit 7
-
1
-
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
1
1
1
1
1
1
1
Reserved
13
12
11
10
9
Reserved
-
Reserved
47
46
45
-
CPUCLK0
CPUCLK1
CPUCLK2
Reserved
8
Byte 3: SDRAM, Active/Inactive Register
(1= enable, 0 = disable)
Byte 4: SDRAM , Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
Reserved
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN# PWD
DESCRIPTION
SDRAM7
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
1
1
1
1
1
1
1
1
33
34
36
37
38
40
41
42
1
1
1
1
1
1
1
1
21
20
26
27
28
30
31
24_48MHz
48MHz
SDRAM6
SDRAM5
SDRAM4
SDRAM3
SDRAM2
SDRAM1
SDRAM0
SDRAM12
SDRAM11
SDRAM10
SDRAM9
SDRAM8
Byte 5: AGP, Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
X
X
X
X
1
FS3 (Readback)
FS2 (Readback)
FS1 (Readback)
FS0 (Readback)
REF0
-
-
3
2
1
REF1
17
16
1
AGPCLK1
AGPCLK0
1
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
2. Latched Frequency Selects (FS#) will be inverted logic
load of the input frequency select pin conditions.
0670B—07/15/04
4
ICS951901
Byte 6: Control , Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
REF strength 0=1X, 1=2X
Bit7
2,3
0
CPUCLK2 - Stop - Control
0=CPU_STOP# will control CPUCLK2,
1=CPUCLK2 is free running even if CPU_STOP# is low
Bit6
45
0
Bit5
Bit4
Bit3
Bit2
Bit1
-
-
-
-
-
X
X
X
X
X
AGPSEL (Readback)
MODE (Readback)
CPU_STOP# (Readback)
PCI_STOP# (Readback)
SDRAM_STOP# (Readback)
AGP Speed Toggle
0=AGPSEL (pin2) will be determined by latch input setting,
1=AGPSEL will be opposite of latch input setting
Bit0
-
0
Byte 8: Byte Count and Read Back Register
(1= enable, 0 = disable)
Byte 7: Vendor ID Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
Reserved
BIT PIN# PWD
DESCRIPTION
Reserved
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
0
0
1
0
1
0
0
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
0
0
0
0
0
1
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Byte 10: VCO Control Selection Bit &
Watchdog Timer Control Register
Byte 9: Watchdog Timer Count Register
Bit
PWD
Description
Bit
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
0=Hw/B0 freq / 1=B11 & 12 freq
WD Enable 0=disable / 1=enable
WD Status 0=normal / 1=alarm
WD Safe Frequency, Byte 0 bit 2
WD Safe Frequency, FS3
WD Safe Frequency, FS2
WD Safe Frequency, FS1
WD Safe Frequency, FS0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
1
0
0
0
0
The decimal representation of these
8 bits correspond to 290ms or 1ms
the watchdog timer will wait before
it goes to alarm mode and reset the
frequency to the safe setting. Default
at power up is 16X 290ms = 4.6
seconds.
Note: FS values in bit [0:4] will correspond to Byte 0 FS
values. Default safe frequency is same as 00000
entry in byte0.
0670B—07/15/04
5
ICS951901
Byte 12: VCO Frequency Control Register
Byte 11: VCO Frequency Control Register
Bit
PWD
X
X
X
X
X
X
X
X
Description
VCO Divider Bit8
Bit
PWD
X
X
X
X
X
X
X
X
Description
VCO Divider Bit0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
VCO Divider Bit7
VCO Divider Bit6
VCO Divider Bit5
VCO Divider Bit4
VCO Divider Bit3
VCO Divider Bit2
VCO Divider Bit1
REF Divider Bit6
REF Divider Bit5
REF Divider Bit4
REF Divider Bit3
REF Divider Bit2
REF Divider Bit1
REF Divider Bit0
Note: The decimal representation of these 9 bits (Byte
12 bit [7:0] & Byte 11 bit [7] ) + 8 is equal to the VCO
divider value. For example if VCO divider value of 36
is desired, user need to program 36 - 8 = 28, namely, 0,
00011100 into byte 12 bit & byte 11 bit 7.
Note: The decimal representation of these 7 bits (Byte 11
[6:0]) + 2 is equal to the REF divider value .
Notes:
1. PWD = Power on Default
Byte 13: Spread Sectrum Control Register
Byte 14: Spread Sectrum Control Register
Bit
PWD
X
X
X
X
X
X
X
X
Description
Spread Spectrum Bit7
Spread Spectrum Bit6
Spread Spectrum Bit5
Spread Spectrum Bit4
Spread Spectrum Bit3
Spread Spectrum Bit2
Spread Spectrum Bit1
Spread Spectrum Bit0
Bit
PWD
X
X
X
X
X
X
X
X
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Reserved
Reserved
Spread Spectrum Bit12
Spread Spectrum Bit11
Spread Spectrum Bit10
Spread Spectrum Bi 9
Spread Spectrum Bit8
Note: Please utilize software utility provided by ICS
Application Engineering to configure spread
spectrum. Incorrect spread percentage may cause
system failure.
Note: Please utilize software utility provided by ICS
Application Engineering to configure spread
spectrum. Incorrect spread percentage may cause
system failure.
Byte 15: Output Skew Control
Byte 16: Output Skew Control
Bit
PWD
Description
Bit
PWD
X
X
X
X
X
X
X
X
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
0
0
1
1
1
1
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SDRAM 12 Skew Control
SDRAM (11:0) Skew Control
CPUCLK2 Skew Control
CPUCLK (1:0) Skew Control
0670B—07/15/04
6
ICS951901
Byte 17:Output Rise/FallTime Select Register
Byte 18: Output Rise/Fall Time Select Register
Bit
PWD
Description
Bit
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
0
1
0
1
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
0
1
0
1
0
1
0
PCI (3:0) Slew Rate Control
SDRAM12: Slew Rate Control
PCI_F Slew Rate Control
AGPCLK1: Slew Rate Control
AGPCLK0: Slew Rate Control
PCICLK4: Slew Rate Control
CPUCLK2 Slew Rate Control
CPUCLK1 Slew rate Control
0
Byte 19:Output Rise/FallTime Select Register
Byte 20: Output Rise/Fall Time Select Register
Bit
PWD
Description
Bit
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
0
1
0
1
0
1
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
48MHz: Slew Rate Control
24_48MHz: Slew Rate Control
REF1: Slew Rate Control
REF0: Slew Rate Control
SDRAM (11:0): Slew Rate Control
0
CPUCLK0 Slew Rate Control
VCO Programming Constrains
VCO Frequency ...................... 150MHz to 500MHz
VCO Divider Range ................ 8 to 519
REF Divider Range ................. 2 to 129
Phase Detector Stability .......... 0.3536 to 1.4142
Useful Formula
VCO Frequency = 14.31818 x VCO/REF divider value
Phase Detector Stabiliy = 14.038 x (VCO divider value)-0.5
To program theVCO frequency for over-clocking.
0. Before trying to program our clock manually, consider using ICS provided software utilities for easy
programming.
1. Select the frequency you want to over-clock from with the desire gear ratio (i.e. CPU:SDRAM:3V66:PCI ratio) by
writing to byte 0, or using initial hardware power up frequency.
2.Write 0001, 1001 (19H) to byte 8 for readback of 21 bytes (byte 0-20).
3. Read back byte 11-20 and copy values in these registers.
4. Re-initialize the write sequence.
5. Write a '1' to byte 9 bit 7 and write to byte 11 & 12 with the desired VCO & REF divider values.
6. Write to byte 13 to 20 with the values you copy from step 3. This maintains the output spread, skew and slew
rate.
7.The above procedure is only needed when changing the VCO for the 1st pass. If VCO frequency needed to be
changed again, user only needs to write to byte 11 and 12 unless the system is to reboot.
0670B—07/15/04
7
ICS951901
Absolute Maximum Ratings
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . 0°C to +70°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . 115°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of the device at these or any other conditions above those
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Volt age VDD = 3.3 V +/-5%VDDL = 2.5 V +/-5% (unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
Supply Current
Power Down
SYMBOL
CONDITIONS
MIN
2
TYP
MAX UNITS
VIH
VIL
IDD
PD
Fi
VDD + 0.3
0.8
V
V
VSS - 0.3
CL=30 pF, CPU @ 66, 100 MHz
390
300
400
mA
mA
600
Input frequency
Input Capacitance1
VDD = 3.3 V;
Logic Inputs
12
27
14.32
16
MHz
CIN
CINX
5
45
3
pF
pF
X1 & X2 pins
Transition Time
Settling Time
Clk Stabilization1
Ttrans
TS
To 1st crossing of target Freq.
From 1st crossing to 1% target Freq.
From VDD= 3.3 V to 1% target Freq.
CPUVT= 1.5 V PCI VT=1.25V
TSTAB
TCPU-PCI
3
4
0
ms
ns
ps
Skew
Skew
1
1.9
TCPU-SDRAM CPUVT= 1.5 V SDRAM VT=1.25
-500
-300
1 Guaranteed by design, not 100% tested in production.
0670B—07/15/04
8
ICS951901
Electrical Characteristics - CPU
TA = 0 - 70°C; VDDL = 2.5 V +/-5%; VDDL = 2.5 V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
Output Impedance1
Output Impedance1
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
SYMBOL
RDSP2B
RDSN2B
VOH2B
VOL2B
IOH2B
CONDITIONS
VO = VDD*(0.5)
MIN
10
10
2
TYP
MAX UNITS
20
20
V
VO = VDD*(0.5)
IOH = -12.0 mA
IOL = 12 mA
0.4
-19
V
VOH = 1.7 V
mA
mA
ns
IOL2B
VOL = 0.7 V
19
0.4
0.4
45
tr2B
VOL = 0.4 V, VOH = 2.0 V
VOH = 2.0 V, VOL = 0.4 V
VT = 1.25 V
1.2
1.1
1.6
1.6
55
Fall Time1
tf2B
ns
Duty Cycle1
dt2B
46.9
%
Skew window0:1
Skew window0:2
Jitter, Cycle-to-cycle1
tsk2B
tsk2B
VT = 1.25 V
43
175
375
250
ps
ps
ps
VT = 1.25 V
142
177
tjcyc-cyc
VT = 1.25 V, CPU=66 MHz
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - 24-48MHz
TA = 0 - 70°C; VDD = 3.3 V +/-5%;VDDL = 2.5 V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
SYMBOL
CONDITIONS
VO = VDD*(0.5)
MIN
20
TYP
MAX UNITS
1
RDSP5B
60
60
V
1
RDSN5B
VO = VDD*(0.5)
IOH = -14 mA
20
VOH15
VOL5
IOH5
IOL5
tr5
2.4
IOL = 6.0 mA
0.4
-20
V
VOH = 2.0 V
mA
mA
ns
VOL = 0.8 V
10
0.4
0.4
45
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.45
1.5
4
4
Fall Time1
Duty Cycle1
tf5
ns
dt5
52.5
210
55
500
%
tcycle to cycle VT = 1.5 V
Jitter
ps
1Guaranteed by design, not 100% tested in production.
0670B—07/15/04
9
ICS951901
Electrical Characteristics - PCI
TA = 0 - 70°C; VDD = 3.3 V +/-5%; VDDL = 2.5 V +/-5%; CL = 10-30 pF (unless otherwise specified)
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
SYMBOL
CONDITIONS
VO = VDD*(0.5)
MIN
12
TYP
MAX UNITS
1
RDSP1B
55
55
V
1
RDSN1B
VO = VDD*(0.5)
IOH = -1 mA
12
VOH1
VOL1
IOH1
IOL1
tr1
2.4
IOL = 1 mA
0.55
-29
V
mA
mA
ns
ns
%
VOH @ MIN = 1.0 V
VOL @ MIN = 1.95 V
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
29
0.5
0.5
45
2.3
2.3
2.5
2.5
55
Fall Time1
Duty Cycle1
Skew window1
tf1
dt1
51.2
108
353
tsk1
VT = 1.5 V
500
500
ps
ps
Jitter, Cycle-to-cycle1
tjcyc-cyc1 VT = 1.5 V
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - SDRAM
TA = 0 - 70°C; VDD = 3.3 V +/-5%;VDDL = 2.5 V +/-5%; CL = 20-30 pF (unless otherwise specified)
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
SYMBOL
CONDITIONS
VO = VDD*(0.5)
MIN
10
TYP
MAX UNITS
1
RDSP3B
24
24
V
1
RDSN3B
VO = VDD*(0.5)
IOH = -18 mA
10
VOH3
VOL3
IOH3
IOL3
tr3
2.4
IOL = 9.4 mA
0.4
-46
V
mA
mA
ns
VOH = 2.0 V
VOL = 0.8V
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
0.8
0.8
1.6
1.6
55
Fall Time1
Duty Cycle1
Skew window1(0:11)
tf3
ns
dt3
45
48.5
192
290
%
tsk3
tsk3
VT = 1.5 V
250
500
ps
Skew window1( 0:12)
VT = 1.5 V
ps
Jitter, Cycle-to-cycle1
173
250
tjcyc-cyc3 VT = 1.5 V, CPU=66,100,133 MHz
ps
1Guaranteed by design, not 100% tested in production.
0670B—07/15/04
10
ICS951901
Electrical Characteristics - AGP
TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 20 pF (unless otherwise specified)
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
SYMBOL
CONDITIONS
MIN
12
12
2
TYP
MAX UNITS
1
RDSP4B
VO=VDD*(0.5)
VO=VDD*(0.5)
IOH = -18 mA
IOL = 18 mA
VOH = 2.0 V
VOL = 0.8 V
55
55
V
1
RDSN4B
VOH4B
VOL4B
IOH4B
IOL4B
0.4
-19
V
mA
mA
ns
ns
%
19
0.5
0.5
45
tr4B
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.5
1.6
2
2
Fall Time1
tf4B
Duty Cycle1
Skew window1
Jitter Cyc-Cyc
dt4B
tsk1
tjcyc-cyc1
52.3
55.5
239
55
175
500
VT = 1.5 V
ps
ps
VT = 1.5 V
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - REF
TA = 0 - 70°C; VDD = 3.3 V +/-5%;VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
SYMBOL
VOH5
VOL5
IOH5
IOL5
CONDITIONS
IOH = -12 mA
MIN
2.4
TYP
MAX UNITS
V
IOL = 9 mA
0.4
-22
V
VOH = 2.0 V
mA
mA
ns
VOL = 0.8 V
16
45
tr5
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 50%
1.8
1.9
4
4
Fall Time1
Duty Cycle1
tf5
ns
dt5
54.5
55
%
1Guaranteed by design, not 100% tested in production.
0670B—07/15/04
11
ICS951901
General I2C serial interface information for the ICS951901
How to Write:
How to Read:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2 (H)
• ICS clock will acknowledge
• Controller (host) will send start bit.
• Controller (host) sends the read address D3 (H)
• ICS clock will acknowledge
• Controller (host) sends a dummy command code
• ICS clock will acknowledge
• ICS clock will send the byte count
• Controller (host) acknowledges
• Controller (host) sends a dummy byte count
• ICS clock will acknowledge
• Controller (host) starts sending Byte 0 through Byte 28
(see Note 2)
• ICS clock sends Byte 0 through byte 6 (default)
• ICS clock sends Byte 0 through byte X (if X(H) was
written to byte 6).
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a stop bit
• ICS clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
How to Write:
How to Read:
Controller (Host)
Controller (Host)
ICS (Slave/Receiver)
ICS (Slave/Receiver)
Start Bit
Start Bit
Address D2(H)
Address D3(H)
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Byte Count
Dummy Command Code
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Dummy Byte Count
Byte 0
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte 7
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
ACK
If 7H has been written to B6
ACK
Byte 6
Byte 18
Byte 19
Byte 20
Stop Bit
ACK
ACK
ACK
If 1AH has been written to B6
ACK
Byte18
Byte 19
Byte 20
If 1BH has been written to B6
ACK
If 1CH has been written to B6
ACK
Stop Bit
*See notes on the following page.
0670B—07/15/04
12
ICS951901
Brief I2C registers description for ICS951901
Programmable System Frequency Generator
Register Name
Byte
Description
PWD Default
Output frequency, hardware / I2C
frequency select, spread spectrum &
output enable control register.
Functionality &
Frequency Select
Register
See individual
byte
description
0
See individual
byte
description
Active / inactive output control
registers/latch inputs read back.
Output Control Registers
1-6
7
Byte 11 bit[7:4] is ICS vendor id -
1001. Other bits in this register
designate device revision ID of this
part.
See individual
byte
description
Vendor ID & Revision ID
Registers
Writing to this register will configure
byte count and how many byte will
be read back. Do not write 00H to
this byte.
Byte Count
Read Back Register
8
9
08H
10H
Writing to this register will configure
the number of seconds for the
watchdog timer to reset.
Watchdog Timer
Count Register
Watchdog enable, watchdog status
10 Bit [6:0] and programmable 'safe' frequency'
can be configured in this register.
Watchdog Control
Registers
000,0000
This bit select whether the output
VCO Control Selection
Bit
frequency is control by
hardware/byte 0 configurations or
10 Bit [7]
0
byte 11&12 programming.
These registers control the dividers
ratio into the phase detector and
thus control the VCO output
frequency.
Depended on
hardware/byte
0 configuration
VCO Frequency Control
Registers
11-12
Depended on
hardware/byte
0 configuration
See individual
byte
description
See individual
byte
Spread Spectrum
Control Registers
These registers control the spread
percentage amount.
13-14
Increment or decrement the group
skew amount as compared to the
initial skew.
Group Skews Control
Registers
15-16
17-20
Output Rise/Fall Time
Select Registers
These registers will control the
output rise and fall time.
description
Notes:
1.
The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches
for verification. Readback will support standard SMBUS controller protocol. The number of bytes to
readback is defined by writing to byte 8.
2.
When writing to byte 11 - 12, and byte 13 - 14, they must be written as a set. If for example, only byte
14 is written but not 15, neither byte 14 or 15 will load into the receiver.
3.
4.
5.
6.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I2C interface, the protocol is set to use only Block-Writes from the
controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to
stop after any complete byte has been transferred. The Command code and Byte count shown above must
be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued.
At power-on, all registers are set to a default condition, as shown.
7.
0670B—07/15/04
13
ICS951901
Shared Pin Operation -
Input/Output Pins
Figure 1 shows a means of implementing this function
when a switch or 2 pin header is used. With no jumper is
installed the pin will be pulled high. With the jumper in
place the pin will be pulled low. If programmability is not
necessary, than only a single resistor is necessary. The
programming resistors should be located close to the
series termination resistor to minimize the current loop
area. It is more important to locate the series termination
resistor close to the driver than the programming resistor.
TheI/Opinsdesignatedby(input/output)ontheICS951901
serve as dual signal functions to the device. During initial
power-up, they act as input pins. The logic level (voltage)
that is present on these pins at this time is read and
stored into a 5-bit internal data latch. At the end of Power-
On reset, (see AC characteristics for timing values), the
device changes the mode of operations for these pins to
an output function. In this mode the pins produce the
specified buffered clocks to external loads.
To program (load) the internal configuration register for
these pins, a resistor is connected to either the VDD
(logic 1) power supply or the GND (logic 0) voltage
potential. A 10 Kilohm (10K) resistor is used to provide
both the solid CMOS programming voltage needed during
the power-up programming period and to provide an
insignificant load on the output clock during the subsequent
operating period.
Via to
VDD
Programming
Header
2K
Via to Gnd
Device
Pad
8.2K
Clock trace to load
Series Term. Res.
Fig. 1
0670B—07/15/04
14
ICS951901
CPU_STOP# Timing Diagram
CPU_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power
operation. CPU_STOP# is synchronized by the ICS94209. The minimum that the CPU clock is enabled (CPU_STOP#
high pulse) is 100 CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks
will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse.
CPU clock on latency is less than 4 CPU clocks and CPU clock off latency is less than 4 CPU clocks.
Notes:
1. All timing is referenced to the internal CPU clock.
2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is
synchronized to the CPU clocks inside the ICS94209.
3. All other clocks continue to run undisturbed. (including SDRAM outputs).
0670B—07/15/04
15
ICS951901
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS94209. It is used to turn off the PCICLK clocks for low power operation.
PCI_STOP# is synchronized by the ICS94209 internally. The minimum that the PCICLK clocks are enabled
(PCI_STOP# high pulse) is at least 10 PCICLK clocks. PCICLK clocks are stopped in a low state and started with a
full high pulse width guaranteed. PCICLK clock on latency cycles are only one rising PCICLK clock off latency is one
PCICLK clock.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS94209 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS94209.
3. All other clocks continue to run undisturbed.
4. CPU_STOP# is shown in a high (true) state.
0670B—07/15/04
16
ICS951901
SDRAM_STOP# Timing Diagram
SDRAM_STOP# is an asychronous input to the clock synthesizer. It is used to stop SDRAM clocks for low power
operation. SDRAM_STOP# is synchronized to complete it's current cycle, by the ICS94209. All other clocks will
continue to run while the SDRAM clocks are disabled. The SDRAM clocks will always be stopped in a low state and
start in such a manner that guarantees the high pulse width is a full pulse.
Notes:
1. All timing is referenced to the internal CPU clock.
2. SDRAM is an asynchronous input and metastable conditions may exist. This signal is
synchronized to the SDRAM clocks inside the ICS94209.
3. All other clocks continue to run undisturbed.
0670B—07/15/04
17
ICS951901
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part.
PD# is an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering
down the clock synthesizer.
Internal clocks are not running after the device is put in power down.When PD# is active low all clocks need to be driven
to a low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than 3 mS.
The power down latency should be as short as possible but conforming to the sequence requirements shown below.
PCI_STOP# and CPU_STOP# are considered to be don't cares during the power down operations.The REF and 48MHz
clocks are expected to be stopped in the LOW state as soon as possible. Due to the state of the internal logic, stopping
and holding the REF clock outputs in the LOW state may require more than one clock cycle to complete.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS94209 device).
2. As shown, the outputs Stop Low on the next falling edge after PD# goes low.
3. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part.
4. The shaded sections on the VCO and the Crystal signals indicate an active clock.
5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz.
0670B—07/15/04
18
ICS951901
c
N
In Millimeters
In Inches
SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS
L
MIN
2.41
0.20
0.20
0.13
MAX
2.80
0.40
0.34
0.25
MIN
.095
.008
.008
.005
MAX
.110
.016
.0135
.010
A
A1
b
E1
E
INDEX
AREA
c
D
E
E1
e
SEE VARIATIONS
SEE VARIATIONS
10.03
7.40
10.68
7.60
.395
.291
.420
.299
1
2
0.635 BASIC
0.025 BASIC
hh xx 4455°°
h
L
0.38
0.50
0.64
1.02
.015
.020
.025
.040
D
N
α
SEE VARIATIONS
SEE VARIATIONS
0°
8°
0°
8°
A
VARIATIONS
D mm.
D (inch)
A1
N
MIN
15.75
MAX
16.00
MIN
.620
MAX
- C -
48
.630
e
SEATING
PLANE
Reference Doc.: JEDEC Publication 95, MO-118
b
10-0034
.10 (.004) C
300 mil SSOP Package
Ordering Information
ICS951901yFLF-T
Example:
ICS XXXXXX y F LF- T
Designation for tape and reel packaging
Lead Free (Optional)
Package Type
F = SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
0670B—07/15/04
19
相关型号：
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