ICS952301YG-T [ICSI]
Frequency Timing Generator for Transmeta Systems; 频率时序发生器全美达系统
| 型号： | ICS952301YG-T |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Frequency Timing Generator for Transmeta Systems |
| 文件： | 总12页 (文件大小：588K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS952301
Integrated
Circuit
Systems, Inc.
Advance Information
Frequency Timing Generator for Transmeta Systems
RecommendedApplication:
Transmeta
OutputFeatures:
Pin Configuration
•
1CPU up to 66.6MHz &
overclocking of 66MHz.
GNDREF 1
28 VDDREF
*
2
27
X1
REF/ 1X or 2X Programmable
•
7 PCI (3.3V) @ 33.3MHz (all are free running
selectable) w/ 2 selectable 1X/2X.
X2 3
PD# 4
26 CPU_STOP#
25 VDDCPU/CORE
24 GNDCPU/CORE
23 CPUCLK0
22 PCI_STOP#
21 SCLK
PCICLK0 5
PCICLK1 6
GNDPCI 7
VDDPCI 8
•
•
1 REF (3.3V) at 14.318MHz.
1 48MHz (3.3V).
•
1 24_48MHz selectable output.
PCICLK21
VDD48
9
20
Features:
PCICLK3 10
19 GND48
PCICLK41
48MHz
11
18
•
•
•
•
Supports Spread Spectrum modulation for CPU and
*
12
17
PCI clocks, default -2.0% downspread.
GNDPCI
24-48MHz/Sel 48_24#
VDDPCI 13
PCICLK5 14
16 SDATA
15 PCICLK6
Efficient Power management scheme through stop
clocks and power down modes.
Uses external 14.318MHz crystal, no external load
cap required for CL=18pF crystal.
28-Pin 173milTSSOP
28-pin TSSOP package, 4.40mm (173mil).
Note: ^ Internal Pulldown Resistor
* Internal Pullup Resistor
SkewCharacteristics:
1 1X/2X Programmable
•
PCI – PCI < 500ps
•
CPU(early) – PCI = 1.5ns – 4ns.
Block Diagram
X1
XTA L
REF
OSC
X2
STOP
STOP
CPU
CPU
PLL
PCI(6:0)
PCI DIV
SCLOCK
SDATA
PD#
Control
Logic
PCI_STOP#
SEL48_24#
CPU_STOP#
48MHz
PLL
48MHz
STOP
Power Groups
VDD_Core, GND_Core = PLL core
VDDREF, GNDREF = REF, X1, X2
VDDPCI, GNDPCI = PCICLK (6:0)
VDD48, GND48 = 48MHz (1:0)
STOP
24/48MHz
24/48
0673—07/09/02
Pentium is a trademark on Intel Corporation.
ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals.
ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.
ICS952301
Advance Information
Pin Descriptions
PIN
PIN # PIN
DESCRIPTION
TYPE
PWR
IN
1
2
3
GNDREF
X1
X2
Ground pin.
Crystal input, nominally 14.318MHz.
Crystal output, nominally 14.318MHz.
Asynchronous active low input pin used to power down the
device into a low power state. The internal clocks are
disabled and the VCO and the crystal are stopped. The
latency of the power down will not be greater than 3ms.
PCI clock outputs.
PCI clock outputs.
Ground pin.
Supply for PCI, nominal 3.3V.
PCI clock outputs.
PCI clock outputs.
PCI clock outputs.
Ground pin.
Supply for PCI, nominal 3.3V.
PCI clock outputs.
PCI clock outputs.
Data pin for I2C circuitry 5V tolerant
OUT
4
PD#
IN
5
6
7
8
PCICLK0
PCICLK1
GNDPCI
VDDPCI
PCICLK21
PCICLK3
PCICLK41
GNDPCI
VDDPCI
PCICLK5
PCICLK6
SDATA
OUT
OUT
PWR
PWR
OUT
OUT
OUT
PWR
PWR
OUT
OUT
I/O
9
10
11
12
13
14
15
16
24-48MHz/Sel
48_24#*
48MHz
GND48
VDD48
17
I/O
Selectable 48 or 24MHz output
18
19
20
21
OUT
PWR
PWR
IN
48MHz output clock
Ground pin.
Power for 24 & 48MHz output buffers and fixed PLL core.
Clock pin of I2C circuitry 5V tolerant
Stops all PCICLKs besides the PCICLK_F clocks at logic 0
level, when input low
SCLK
22
PCI_STOP#
IN
23
24
25
CPUCLK0
GNDCPU/CORE
VDDCPU/CORE
OUT
PWR
PWR
CPU clock outputs.
Ground pin.
3.3V power for the PLL core.
Stops all CPUCLKs besides the CPUCLK_F clocks at logic 0
level, when input low
26
CPU_STOP#
IN
REF/ 1X or 2X
Programmable*
VDDREF
14.318 MHz reference clock. Latched input select for strength
of PCICLK(4,2). Default 1X with internal pullup.
3.3V power for the REF.
27
28
OUT
PWR
0673—07/09/02
2
ICS952301
Advance Information
ICS952301PowerManagementRequirements
CPU
PCI
Byte 0
PCICLK PCICLK
24
48
REF
VCO
STOP#
STOP#
Bit 0
Not Free Free-Run
Run
MHz
MHZ
PD#
CPUCLK
0
0
1
1
1
X
0
1
1
X
1
0
1
X
0
0
1
STOP
RUN
RUN
RUN
LOW
LOW
RUN
LOW
RUN
RUN
LOW
RUN
RUN
LOW
RUN
RUN
LOW
RUN
RUN
STOP
RUN
STOP
Tri-State Tri-State Tri-State Tri-State Tri-State Tri-State
Note: If Byte 3 bit [7:2]=0 Not Free-Run, can be controlled by PCI_STOP#
If Byte 3 bit [7:2]=1 Free-Run, cannot controlled by PCI_STOP#
0673—07/09/02
3
ICS952301
Advance Information
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
For more information, contact ICS for an I2C programming application note.
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2(H)
• ICS clock will acknowledge
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the read address D3 (H)
• ICS clock will acknowledge
• Controller (host) sends a dummy command code
• ICS clock will acknowledge
• ICS clock will send the byte count
• Controller (host) acknowledges
• Controller (host) sends a dummy byte count
• ICS clock will acknowledge
• Controller (host) starts sending first byte (Byte 0)
through byte 6
• ICS clock sends first byte (Byte 0) through byte 6
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a stop bit
• ICS clock will acknowledge each byte one at a time.
• Controller (host) sends a Stop bit
How to Write:
Controller (Host)
Start Bit
ICS (Slave/Receiver)
How to Read:
Controller (Host)
Start Bit
ICS (Slave/Receiver)
Address
D2(H)
Address
D3(H)
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Dummy Command Code
ACK
Byte Count
Dummy Byte Count
Byte 0
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
ACK
Stop Bit
Stop Bit
Notes:
1.
The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for
verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.
2.
3.
4.
5.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller.
The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any
complete byte has been transferred. The Command code and Byte count shown above must be sent, but the
data is ignored for those two bytes. The data is loaded until a Stop sequence is issued.
At power-on, all registers are set to a default condition, as shown.
6.
0673—07/09/02
4
ICS952301
Advance Information
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default = 0)
Bit2
Bit7
Bit6
Bit5
FS1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
Bit4
FS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Bit
CPU
PCI
FS4 FS3 FS2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
60
60
60
30
30
30
60
30
66.6
66.6
66.6
66.6
67.32
68.64
69.96
72.6
61.5
63
64
65
60
66.6
50
33.3
33.3
33.3
33.3
33.66
34.32
34.98
36.3
30.75
31.5
32
32.5
30
33.3
25
Bit
2,7:4
48
24
58.8
57.6
56.4
54
60
60
60
60
66.6
66.6
66.6
66.6
29.4
28.8
28.2
27
30
30
30
30
33.3
33.3
33.3
33.3
1
1
Reserved
Bit3
Bit1
Bit0
0-Normal 1-Spread spectrun Enabled
0-Running 1-Tristate all outputs
Note: PWD = Power-Up Default
0673—07/09/02
5
ICS952301
Advance Information
BYTE
Affected Pin
Bit Control
0
BYTE
Affected Pin
Bit Control
Pin #
Name
Control Function
1
PWD
1
0
Pin #
Name
Control Function
0
1
PWD
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
15
14
11
10
9
6
5
-
PCICLK6
PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0
-
Output disable
Output disable
Output disable
Output disable
Output disable
Output disable
Output disable
(Reserved)
RW
RW
RW
RW
RW
RW
RW
-
Disable
Disable
Disable
Disable
Disable
Disable
Disable
-
Enable
Enable
Enable
Enable
Enable
Enable
Enable
-
1
1
1
1
1
1
1
0
-
-
-
-
-
-
Frequency select by bit 7
Frequency select by bit 6
Frequency select by bit 5
RW
RW
RW
1
1
1
Bit 7
Bit 6
Bit 5
See Frequency table
Frequency select by bit 4
Reserved
RW
R
1
1
1
Bit 4
Bit 3
Bit 2
-
-
-
-
-
-
See Frequency table
Frequency select by bit 2
RW
-
-
-
-
Spread Enable
Output Control
RW
RW
Normal
Enable
0
0
Bit 1
Bit 0
Affected Pin
Bit Control
Running
Tri-state
BYTE
Pin #
Name
Control Function
0
1
PWD
3
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
15
14
11
10
9
6
5
-
PCICLK6
PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0
-
Free Run Status
Free Run Status
Free Run Status
Free Run Status
Free Run Status
Free Run Status
Free Run Status
(Reserved)
RW
RW
RW
RW
RW
RW
RW
-
Disable
Disable
Disable
Disable
Disable
Disable
Disable
-
Enable
Enable
Enable
Enable
Enable
Enable
Enable
-
1
1
1
1
1
1
1
X
BYTE
Affected Pin
Bit Control
0
Pin #
Name
Control Function
1
PWD
2
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
18
48MHz
Output Disable
Output Disable
Output disable
Output disable
1X or 2X
1X or 2X
PCI HW SEL Status
(Reserved)
RW
RW
RW
RW
RW
RW
R
Disable
Disable
Disable
Disable
2X
Enable
Enable
Enable
Enable
1X
1
1
1
1
1
1
1
X
17 24_48MHz
23
27
9
CPUCLK0
REF
PCICLK2
11
-
-
PCICLK4
2X
1X
-
-
2X
1X
-
-
-
BYTE
Affected Pin
Bit Control
Pin #
Name
Control Function
0
1
PWD
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
X
X
X
X
X
X
X
X
(Reserved)
-
-
-
Bit 7
Affected Pin
Bit Control
BYTE
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
Name
Control Function
0
1
PWD
4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
X
X
X
X
X
X
X
X
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(Reserved)
(Reserved)
(Reserved)
-
-
-
-
-
-
-
-
-
BYTE
Affected Pin
Bit Control
6
Pin #
Name
Control Function
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
0
-
-
-
-
-
-
1
-
-
-
-
-
-
PWD
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
0
0
0
0
1
1
0
-
-
-
-
-
-
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
-
-
-
-
-
-
Bit 1
Bit 0
0673—07/09/02
6
ICS952301
Advance Information
CPU_STOP#Timing Diagram
CPUSTOP#isanasychronousinputtotheclocksynthesizer.ItisusedtoturnofftheCPUCLKsforlowpoweroperation.
CPU_STOP#issynchronizedbytheICS952301.TheminimumthattheCPUCLKisenabled(CPU_STOP#highpulse)
is 100 CPUCLKs.All other clocks will continue to run while the CPUCLKs are disabled.The CPUCLKs will always be
stoppedinalowstateandstartinsuchamannerthatguaranteesthehighpulsewidthisafullpulse.CPUCLKonlatency
is less than 4 CPUCLKs and CPUCLK off latency is less than 4 CPUCLKs.
INTERNAL
CPUCLK
PCICLK
CPU_STOP#
PCI_STOP# (High)
PD# (High)
CPUCLK
Notes:
1. All timing is referenced to the internal CPUCLK.
2. CPU_STOP# is an asynchronous input and metastable conditions may
exist. This signal is synchronized to the CPUCLKs inside the ICS9248-192.
3. All other clocks continue to run undisturbed.
4. PD# and PCI_STOP# are shown in a high (true) state.
PCI_STOP#Timing Diagram
PCI_STOP#isanasynchronousinputtotheICS952301.ItisusedtoturnoffthePCICLKclocksforlowpoweroperation.
PCI_STOP# is synchronized by the ICS952301 internally. The minimum that the PCICLK clocks are enabled
(PCI_STOP# high pulse) is at least 10 PCICLK clocks. PCICLK clocks are stopped in a low state and started with a
full high pulse width guaranteed. PCICLK clock on latency cycles are only one rising PCICLK clock off latency is one
PCICLK clock.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS952301 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS952301.
3. All other clocks continue to run undisturbed.
4. PD# and CPU_STOP# are shown in a high (true) state.
0673—07/09/02
7
ICS952301
Advance Information
PD#Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part.
PD# is an asynchronous active low input.This signal is synchronized internally by the ICS952301 prior to its control
action of powering down the clock synthesizer.Internal clocks will not be running after the device is put in power down
state.When PD# is active (low) all clocks are driven to a low state and held prior to turning off theVCOs and the crystal
oscillator.Thepoweronlatencyisguaranteedtobelessthan3ms.ThepowerdownlatencyislessthanthreeCPUCLK
cycles.PCI_STOP# and CPU_STOP# are don’t care signals during the power down operations.
CPUCLK
(Internal)
PCICLK
(Internal)
PD#
CPUCLK
PCICLK_F, PCICLK
REF
INTERNAL
VCOs
INTERNAL
CRYSTAL OSC.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS952301 device).
2. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside the ICS9248.
3. The shaded sections on the VCO and the Crystal signals indicate an active clock is being generated.
0673—07/09/02
8
ICS952301
Advance Information
Absolute Maximum Ratings
SupplyVoltage . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient OperatingTemperature . . . . . . . . . . 0°C to +70°C
StorageTemperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device.These
ratingsarestressspecificationsonlyandfunctionaloperationofthedeviceattheseoranyotherconditionsabovethose
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parame
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5% (unless otherwise stated)
PARAMETER
SYMBOL
VIH
CONDITIONS
MIN
2
TYP
MAX UNITS
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
VDD+0.3
V
V
VIL
VSS-0.3
0.8
5
IIH
VIN = VDD
VIN = 0 V; Inputs with no pull-up resistors -5
0.1
2.0
A
µ
µ
µ
IIL1
A
A
Input Low Current
Operating Supply
Current
IIL2
VIN = 0 V; Inputs with pull-up resistors
-200
-100
IDD(op)
IDDPD
CL = 0 pF; Select @ 66MHz
11
180
600
mA
Power Down
Supply Current
CL = 0 pF; With input address to Vdd or
0
A
µ
GND
Input frequency
Fi
CIN
VDD = 3.3 V;
11
27
14.32
16
5
MHz
pF
Logic Inputs
Input Capacitance1
CINX
X1 & X2 pins
36
2
45
3
pF
Transition Time1
Clk Stabilization1
Skew1
Ttrans
TSTAB
TCPU-PCI
To 1st crossing of target Freq.
From VDD = 3.3 V to 1% target Freq.
VT = 1.5 V
ms
ms
ns
3
1.5
4
1Guaranteed by design, not 100% tested in production.
0673—07/09/02
9
ICS952301
Advance Information
Electrical Characteristics - CPUCLK
Output Type:
1
TA = 0 - 70C; VDD = 3.3 V +/-5% CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
Output Impedence
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
Rdsp
CONDITIONS
VO = Vdd * 0.5
MIN
12
TYP
32
MAX UNITS
60
Ohm
V
VOH2B
VOL2B
IOH2B
IOH = -12.0 mA
IOL = 12 mA
1.8
2.1
0.15
-32
49
0.4
-27
V
VOH = 1.7 V
mA
mA
ns
IOL2B
VOL = 0.7 V
27
0.4
0.4
44
1
tr2B
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.4
1.6
48
2
2
1
Fall Time
tf2B
ns
1
Duty Cycle
dt2B
55
%
1
Skew
tsk2B
VT = 1.5 V
18
175
250
+250
ps
1
tjcyc-cyc2B VT = 1.5 V
122
198
ps
Jitter
1
tjabs2B
VT = 1.5 V
-250
ps
Electrical Characteristics - REF
Output Type:
1
TA = 0 - 70C; VDD = 3.3 V, +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
Rdsp
VOH5
CONDITIONS
VO = Vdd * 0.5
MIN
12
TYP
32
MAX UNITS
Output Impedence
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
60
Ohm
V
IOH = -12 mA
IOL = 9 mA
VOH = 2.0 V
VOL = 0.8 V
2.6
2.9
0.3
-29
51
VOL5
0.4
-22
V
IOH5
mA
mA
IOL5
16
45
Rise Time1
Fall Time1
Duty Cycle1
tr5
tf5
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
1.9
1.9
4
4
ns
ns
dt5
VT = 1.5 V
VT = 1.5 V
52
55
%
tjcyc-cyc5
559
1000
ps
1
0673—07/09/02
10
ICS952301
Advance Information
Electrical Characteristics - 48MHz & 48/24MHz Output Type:
1
TA = 0 - 70C; VDD = 3.3 V, +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
Rdsp VO = Vdd * 0.5
VOH5 IOH = -12 mA
VOL5 IOL = 9 mA
CONDITIONS
MIN
20
TYP
30
MAX UNITS
Output Impedence
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
65
Ohm
V
2.6
2.9
0.3
-29
51
0.4
-22
V
IOH5
IOL5
VOH = 2.0 V
VOL = 0.8 V
mA
mA
16
45
Rise Time1
Fall Time1
Duty Cycle1
tr5
tf5
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
0.7
0.7
1.2
1.2
ns
ns
dt5
52
55
%
ps
ps
tjcyc-cyc5 VT = 1.5 V
164
221
500
800
Jitter1
tjabs5 VT = 1.5 V
Output Type: 5
Electrical Characteristics - PCICLK
PCICLK(6:0)
MAX UNITS
TA = 0 - 70C; VDD = 3.3 V,+/-5%; CL = 30 pF
PARAMETER
SYMBOL
Rdsp
CONDITIONS
VO = Vdd * 0.5
MIN
12
TYP
32
Output Impedence
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
60
Ohm
V
VOH1 IOH = -18 mA
VOL1 IOL = 9.4 mA
IOH1 VOH = 2.0 V
2.1
2.8
0.15
-75
44
0.4
-22
57
V
mA
mA
IOL1
tr1
VOL = 0.8 V
16
45
Rise Time1
Fall Time1
Duty Cycle1
Skew1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.6
1.8
50
2
2
ns
ns
%
tf1
dt1
tsk1
55
VT = 1.5 V
16
500
500
500
ps
ps
ps
1
tjcyc-cyc VT = 1.5 V
100
210
Jitter
tjabs1 VT = 1.5 V
0673—07/09/02
11
ICS952301
Advance Information
c
N
In Millimeters
COMMON DIMENSIONS
SYMBOL
In Inches
COMMON DIMENSIONS
L
MIN
-
MAX
1.20
0.15
1.05
0.30
0.20
MIN
-
MAX
.047
.006
.041
.012
.008
E1
E
A
A1
A2
b
INDEX
AREA
0.05
0.80
0.19
0.09
.002
.032
.007
.0035
1
22
c
α
SEE VARIATIONS
6.40 BASIC
SEE VARIATIONS
0.252 BASIC
D
D
E
E1
e
4.30
4.50
0.65 BASIC
0.75
.169
.177
0.0256 BASIC
L
0.45
.018
.030
A
A2
SEE VARIATIONS
SEE VARIATIONS
N
A1
0°
-
8°
0°
-
8°
α
aaa
- CC --
0.10
.004
e
SEATING
PLANE
b
VARIATIONS
aaa
C
D mm.
D (inch)
N
MIN
9.60
MAX
9.80
MIN
.378
MAX
4.40 mm. Body, 0.65 mm. pitch TSSOP
(0.0256Inch)
28
.386
7/6/00 Rev C
(173 mil)
MO-153 JEDEC
Doc.# 10-0035
Ordering Information
ICS952301yGT
Example:
ICS 95XXXX y G - T
Designation for tape and reel packaging
Package Type
G=TSSOP
Revision Designator (will not correlate with datasheet revision)
DeviceType (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
0673—07/09/02
12
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