ICS954101YFLFT [ICSI]
Programmable Timing Control Hub for Desktop P4 Systems; 可编程定时控制中心的台式机P4系统
| 型号： | ICS954101YFLFT |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Programmable Timing Control Hub for Desktop P4 Systems |
| 文件： | 总16页 (文件大小：133K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated
Circuit
ICS954101
Systems, Inc.
Programmable Timing Control Hub™ for Desktop P4™ Systems
Recommended Application:
Features/Benefits:
CK410 clock, Intel Yellow Cover part
•
Supports tight ppm accuracy clocks for Serial-ATA and
PCI-Express
Output Features:
•
Supports spread spectrum modulation, 0 to -0.5%
down spread
•
•
2 - 0.7V current-mode differential CPU pairs
6 - 0.7V current-mode differential SRC pair for SATA and
PCI-E
•
•
Supports CPU clks up to 400MHz
Uses external 14.318MHz crystal, external crystal load
caps are required for frequency tuning
•
1 - 0.7V current-mode differential CPU/SRC selectable
pair
•
Supports undriven differential CPU, SRC pair in PD#
for power management.
•
•
•
•
•
6 - PCI (33MHz)
3 - PCICLK_F, (33MHz) free-running
1 - USB, 48MHz
1 - DOT, 96MHz, 0.7V current differential pair
1 - REF, 14.318MHz
Key Specifications:
•
•
•
•
CPU outputs cycle-cycle jitter < 85ps
SRC output cycle-cycle jitter <125ps
PCI outputs cycle-cycle jitter < 500ps
+/- 300ppm frequency accuracy on CPU & SRC clocks
Functionality
Pin Configuration
CPU
MHz
SRC
MHz
PCI
MHz
REF
MHz
USB
MHz
DOT
MHz
FS_C1 FS_B2 FS_A2
VDDPCI 1
GND 2
PCICLK3 3
PCICLK4 4
PCICLK5 5
56 PCICLK2
55 PCICLK1
54 PCICLK0
53 FS_C/TEST_SEL
52 REFOUT
51 GND
50 X1
49 X2
48 VDDREF
47 SDATA
46 SCLK
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
266.66
133.33
200.00
166.66
333.33
100.00
400.00
100.00 33.33 14.318
100.00 33.33 14.318
100.00 33.33 14.318
100.00 33.33 14.318
100.00 33.33 14.318
100.00 33.33 14.318
100.00 33.33 14.318
48.00
48.00
48.00
48.00
48.00
48.00
48.00
48.00
96.00
96.00
96.00
96.00
96.00
96.00
96.00
96.00
0
0
0
0
1
1
1
1
GND 6
VDDPCI 7
ITP_EN/PCICLK_F0 8
PCICLK_F1 9
PCICLK_F2 10
VDD48 11
RESERVED
14.318
FS_C is a three-level input. Please see VIL_FS and VIH_FS specifications in
the Input/Supply/Common Output Parameters Table for correct values.
Also refer to the Test Clarification Table.
2. FS_B and FS_A are low-threshold inputs. Please see the VIL_FS and VIH_FS
specifications in the Input/Supply/Common Output Parameters Table for correct values.
1.
USB_48MHz 12
GND 13
45 GND
44 CPUCLKT0
43 CPUCLKC0
42 VDDCPU
41 CPUCLKT1
40 CPUCLKC1
39 IREF
DOTT_96MHz 14
DOTC_96MHz 15
FS_B/TEST_MODE 16
Vtt_PwrGd#/PD 17
FS_A_410 18
SRCCLKT1 19
SRCCLKC1 20
VDDSRC 21
SRCCLKT2 22
SRCCLKC2 23
SRCCLKT3 24
SRCCLKC3 25
SRCCLKT4_SATA 26
SRCCLKC4_SATA 27
VDDSRC 28
38 GNDA
37 VDDA
36 CPUCLKT2_ITP/SRCCLKT_7
35 CPUCLKC2_ITP/SRCCLKC_7
34 VDDSRC
33 SRCCLKT6
32 SRCCLKC6
31 SRCCLKT5
30 SRCCLKC5
29 GND
56-pin SSOP & TSSOP
0815D—06/21/04
Integrated
Circuit
ICS954101
Systems, Inc.
Pin Description
Pin #
PIN NAME
PIN TYPE
PWR
PWR
OUT
OUT
OUT
DESCRIPTION
Power supply for PCI clocks, nominal 3.3V
Ground pin.
PCI clock output.
PCI clock output.
PCI clock output.
Ground pin.
Power supply for PCI clocks, nominal 3.3V
Free running PCI clock not affected by PCI_STOP#.
ITP_EN: latched input to select pin functionality
1 = CPU_ITP pair
1
2
3
4
5
6
7
VDDPCI
GND
PCICLK3
PCICLK4
PCICLK5
GND
PWR
PWR
VDDPCI
8
ITP_EN/PCICLK_F0
I/O
0 = SRC pair
9
PCICLK_F1
PCICLK_F2
VDD48
USB_48MHz
GND
OUT
OUT
PWR
OUT
PWR
OUT
OUT
Free running PCI clock not affected by PCI_STOP# .
Free running PCI clock not affected by PCI_STOP# .
Power pin for the 48MHz output.3.3V
48.00MHz USB clock
10
11
12
13
14
15
Ground pin.
DOTT_96MHz
DOTC_96MHz
True clock of differential pair for 96.00MHz DOT clock.
Complement clock of differential pair for 96.00MHz DOT clock.
3.3V tolerant input for CPU frequency selection. Refer to input electrical
characteristics for Vil_FS and Vih_FS values. TEST_MODE is a real time
input to select between Hi-Z and REF/N divider mode while in test mode.
16
FS_B/TEST_MODE
IN
Refer to Test Clarification Table.
Vtt_PwrGd# is an active low input used to determine when latched inputs
are ready to be sampled. PD is an asynchronous active high input pin
used to put the device into a low power state. The internal clocks, PLLs
and the crystal oscillator are stopped.
3.3V tolerant low threshold input for CPU frequency selection. This pin
requires CK410 FSA. Refer to input electrical characteristics for Vil_FS
and Vih_FS threshold values.
17
18
Vtt_PwrGd#/PD
FS_A_410
IN
IN
19
20
21
22
23
24
25
26
27
28
SRCCLKT1
SRCCLKC1
VDDSRC
SRCCLKT2
SRCCLKC2
SRCCLKT3
SRCCLKC3
SRCCLKT4_SATA
SRCCLKC4_SATA
VDDSRC
OUT
OUT
PWR
OUT
OUT
OUT
OUT
OUT
OUT
PWR
True clock of differential SRC clock pair.
Complement clock of differential SRC clock pair.
Supply for SRC clocks, 3.3V nominal
True clock of differential SRC clock pair.
Complement clock of differential SRC clock pair.
True clock of differential SRC clock pair.
Complement clock of differential SRC clock pair.
True clock of differential SRC/SATA pair.
Complement clock of differential SRC/SATA pair.
Supply for SRC clocks, 3.3V nominal
0815D—06/21/04
2
Integrated
Circuit
ICS954101
Systems, Inc.
Pin Description (Continued)
Pin #
29
30
31
32
PIN NAME
TYPE
PWR
OUT
OUT
OUT
OUT
PWR
DESCRIPTION
GND
Ground pin.
SRCCLKC5
SRCCLKT5
SRCCLKC6
SRCCLKT6
VDDSRC
Complement clock of differential SRC clock pair.
True clock of differential SRC clock pair.
Complement clock of differential SRC clock pair.
True clock of differential SRC clock pair.
Supply for SRC clocks, 3.3V nominal
33
34
Complimentary clock of CPU_ITP/SRC differential pair CPU_ITP/SRC
output. These are current mode outputs. External resistors are required
for voltage bias. Selected by ITP_EN input.
True clock of CPU_ITP/SRC differential pair CPU_ITP/SRC output. These
are current mode outputs. External resistors are required for voltage bias.
Selected by ITP_EN input.
35
36
CPUCLKC2_ITP/SRCCLKC_7
CPUCLKT2_ITP/SRCCLKT_7
OUT
OUT
37
38
VDDA
GNDA
PWR
PWR
3.3V power for the PLL core.
Ground pin for the PLL core.
This pin establishes the reference current for the differential current-mode
output pairs. This pin requires a fixed precision resistor tied to ground in
order to establish the appropriate current. 475 ohms is the standard value.
39
40
IREF
OUT
OUT
Complimentary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
CPUCLKC1
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
Supply for CPU clocks, 3.3V nominal
41
42
CPUCLKT1
VDDCPU
OUT
PWR
Complimentary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
43
CPUCLKC0
OUT
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
Ground pin.
Clock pin of SMBus circuitry, 5V tolerant.
Data pin for SMBus circuitry, 5V tolerant.
Ref, XTAL power supply, nominal 3.3V
Crystal output, Nominally 14.318MHz
Crystal input, Nominally 14.318MHz.
Ground pin.
44
CPUCLKT0
OUT
45
46
47
48
49
50
51
52
GND
PWR
IN
I/O
PWR
OUT
IN
PWR
OUT
SCLK
SDATA
VDDREF
X2
X1
GND
REFOUT
Reference Clock output
3.3V tolerant input for CPU frequency selection. Low voltage threshold
inputs, see input electrical characteristics for Vil_FS and Vih_FS values.
TEST_Sel: 3-level latched input to enable test mode.
Refer to Test Clarification Table
53
FS_C/TEST_SEL
IN
54
55
56
PCICLK0
PCICLK1
PCICLK2
OUT
OUT
OUT
PCI clock output.
PCI clock output.
PCI clock output.
0815D—06/21/04
3
Integrated
Circuit
ICS954101
Systems, Inc.
General Description
ICS954101 follows Intel CK410 Yellow Cover specification. This clock synthesizer provides a single chip solution for next
generation P4 Intel processors and Intel chipsets. ICS954101 is driven with a 14.318MHz crystal. It generates CPU outputs up
to 400MHz. It also provides a tight ppm accuracy output for Serial ATA and PCI-Express support.
Block Diagram
48MHz, USB
Frequency
Dividers
96MHz_DOTT_0
PLL2
96MHz_DOTC_0
REFOUT
X1
X2
XTAL
CPUCLKT (2:0)
CPUCLKC (2:0)
SRCCLKT (7:0)
SRCCLKC (7:0)
PCICLK (5:0)
SCLK
SDATA
Programmable
Spread
Programmable
Frequency
Dividers
STOP
Logic
PLL1
Vtt_PWRGD#/PD
FS_A
Control
Logic
FS_B
FS_C
PCICLKF (2:0)
ITP_EN
TEST_MODE
TEST_SEL
I REF
Power Groups
Pin Number
Description
VDD
48
GND
51
2,6
29
38
13
45
Xtal, Ref
PCICLK outputs
SRCCLK outputs
1,7
21,28,34
37
Master clock, CPU Analog
DOT, USB, PLL_48
CPUCLK clocks
11
42
0815D—06/21/04
4
Integrated
Circuit
ICS954101
Systems, Inc.
General I2C serial interface information for the ICS954101
How to Write:
How to Read:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2(H)
• ICS clock will acknowledge
• Controller (host) will send start bit.
• Controller (host) sends the write address D2(H)
• ICS clock will acknowledge
• Controller (host) sends the begining byte location = N
• ICS clock will acknowledge
• Controller (host) sends the begining byte
location = N
• Controller (host) sends the data byte count = X
• ICS clock will acknowledge
• Controller (host) starts sending Byte N through
Byte N + X -1
• ICS clock will acknowledge
• Controller (host) will send a separate start bit.
• Controller (host) sends the read address D3(H)
• ICS clock will acknowledge
(see Note 2)
• ICS clock will send the data byte count = X
• ICS clock sends Byte N + X -1
• ICS clock will acknowledge each byte one at a time
• ICS clock sends Byte 0 through byte X (if X(H)
was written to byte 8).
• Controller (host) sends a Stop bit
• Controller (host) will need to acknowledge each byte
• Controllor (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
Index Block Write Operation
Index Block Read Operation
Controller (Host)
ICS (Slave/Receiver)
Controller (Host)
ICS (Slave/Receiver)
starT bit
T
T
starT bit
Slave Address D2(H)
Slave Address D2(H)
WR
WR
WRite
WRite
ACK
ACK
ACK
ACK
ACK
ACK
Beginning Byte = N
Data Byte Count = X
Beginning Byte N
Beginning Byte = N
RT
Repeat starT
Slave Address D3(H)
RD
ReaD
ACK
Data Byte Count = X
Beginning Byte N
ACK
ACK
Byte N + X - 1
ACK
P
stoP bit
Byte N + X - 1
N
P
Not acknowledge
stoP bit
0815D—06/21/04
5
Integrated
Circuit
ICS954101
Systems, Inc.
Absolute Max
Symbol
VDD_A
VDD_In
Parameter
Min
Max
Units
3.3V Core Supply Voltage
3.3V Logic Input Supply Voltage
V
DD + 0.5V
DD + 0.5V
V
V
°C
°C
°C
GND - 0.5
V
Ts
Tambient
Tcase
Storage Temperature
Ambient Operating Temp
Case Temperature
Input ESD protection
-65
0
150
70
115
human body model
ESD prot
2000
V
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
3.3 V +/-5%
MIN
TYP
MAX
UNITS NOTES
VIH
VIL
IIH
V
DD + 0.3
Input High Voltage
Input Low Voltage
Input High Current
2
V
V
V
SS - 0.3
3.3 V +/-5%
VIN = VDD
0.8
5
-5
uA
VIN = 0 V; Inputs with no pull-up
IIL1
IIL2
-5
uA
uA
resistors
VIN = 0 V; Inputs with pull-up
Input Low Current
-200
resistors
Low Threshold Input High
Voltage
VIH_FS
VDD + 0.3
3.3 V +/-5%
0.7
V
Low Threshold Input Low
Voltage
VIL_FS
IDD3.3OP
IDD3.3PD
VSS - 0.3
3.3 V +/-5%
0.35
500
V
Operating Supply Current
3.3 V +/-5%, Full Load
350
mA
all diff pairs driven
all differential pairs tri-stated
VDD = 3.3 V
70
12
mA
mA
MHz
nH
pF
Powerdown Current
Input Frequency3
Pin Inductance1
Fi
14.31818
3
1
1
1
1
Lpin
7
5
6
5
CIN
Logic Inputs
Output pin capacitance
X1 & X2 pins
Input Capacitance1
COUT
CINX
pF
pF
From VDD Power-Up or de-
Clk Stabilization1,2
Modulation Frequency
Tdrive_PD#
TSTAB
1.8
33
ms
kHz
us
1,2
1
assertion of PD# to 1st clock
Triangular Modulation
CPU output enable after
PD# de-assertion
30
300
1
Tfall_Pd#
Trise_Pd#
SMBus Voltage
PD# fall time of
PD# rise time of
VDD
VOLSMBUS @ IPULLUP
IPULLUP
5
5
5.5
0.4
ns
ns
V
1
2
1
1
1
2.7
4
Low-level Output Voltage
Current sinking at VOL = 0.4 V
SCLK/SDATA
V
mA
TRI2C
(Max VIL - 0.15) to (Min VIH + 0.15)
1000
300
ns
ns
1
1
Clock/Data Rise Time
SCLK/SDATA
Clock/Data Fall Time
TFI2C
(Min VIH + 0.15) to (Max VIL - 0.15)
1Guaranteed by design and characterization, not 100% tested in production.
2See timing diagrams for timing requirements.
3 Input frequency should be measured at the REF output pin and tuned to ideal 14.31818MHz to meet• ppm accuracy on PLL outputs.
0815D—06/21/04
6
Integrated
Circuit
ICS954101
Systems, Inc.
Electrical Characteristics - CPU 0.7V Current Mode Differential Pair
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2 , RP=49.9 /
/
9,
REF
PARAMETER
SYMBOL
Zo
CONDITIONS
VO = Vx
MIN
TYP
MAX
850
UNITS NOTES
1
Current Source Output
Impedance
3000
Statistical measurement on single
ended signal using oscilloscope
math function.
Voltage High
Voltage Low
VHigh
VLow
660
1
mV
-150
150
1
Measurement on single ended
signal using absolute value.
Max Voltage
Min Voltage
Crossing Voltage (abs)
Vovs
Vuds
Vcross(abs)
1150
1
mV
1
mV
-300
250
550
140
1
Crossing Voltage (var)
Long Accuracy
d-Vcross
ppm
Variation of crossing over all edges
mV
1
see Tperiod min-max values
400MHz nominal
-300
300
ppm
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
1,2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1,2
1,2
1,2
1,2
1,2
1,2
1,2
1
2.4993
2.4993
2.9991
2.9991
3.7489
3.7489
4.9985
4.9985
5.9982
5.9982
7.4978
7.4978
9.9970
9.9970
2.4143
2.9141
3.6639
4.8735
5.8732
7.3728
9.8720
175
2.5008
2.5133
3.0009
3.016
3.7511
3.77
5.0015
5.0266
6.0018
6.0320
7.5023
5.4000
10.0030
10.0533
400MHz spread
333.33MHz nominal
333.33MHz spread
266.66MHz nominal
266.66MHz spread
200MHz nominal
200MHz spread
166.66MHz nominal
166.66MHz spread
133.33MHz nominal
133.33MHz spread
100.00MHz nominal
100.00MHz spread
Average period
Tperiod
400MHz nominal/spread
333.33MHz nominal/spread
266.66MHz nominal/spread
200MHz nominal/spread
166.66MHz nominal/spread
133.33MHz nominal/spread
100.00MHz nominal/spread
VOL = 0.175V, VOH = 0.525V
Tabsmin
Absolute min period
tr
tf
Rise Time
Fall Time
700
700
125
125
VOH = 0.525V VOL = 0.175V
175
ps
ps
ps
1
1
1
d-tr
d-tf
Rise Time Variation
Fall Time Variation
Measurement from differential
wavefrom
dt3
tsk3
tsk4
Duty Cycle
Skew
45
55
%
ps
ps
1
1
1
CPU (1:0) VT = 50%
100
150
CPU (1:0) to CPU_ITP, VT = 50%
Skew
Measurement from differential
wavefrom
tjcyc-cyc
Jitter, Cycle to cycle
85
ps
1
1Guaranteed by design, not 100% tested in production.
2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFoutput is at 14.31818MHz
0815D—06/21/04
7
Integrated
Circuit
ICS954101
Systems, Inc.
Electrical Characteristics - SRC 0.7V Current Mode Differential Pair
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2 , RP=49.9 /
/
9,
REF
PARAMETER
SYMBOL
Zo
CONDITIONS
VO = Vx
MIN TYP MAX UNITS NOTES
Current Source Output
Impedance
3000
1
Statistical measurement on single
ended signal using oscilloscope
Measurement on single ended
signal using absolute value.
Voltage High
Voltage Low
Max Voltage
VHigh
VLow
Vovs
Vuds
660
-150
850
150
1150
1
1
1
1
mV
mV
mV
mV
Min Voltage
-300
Crossing Voltage (abs) Vcross(abs)
250 350
550
140
1
1
Variation of crossing over all
edges
see Tperiod min-max values
100.00MHz nominal
100.00MHz spread
100.00MHz nominal/spread
VOL = 0.175V, VOH = 0.525V
Crossing Voltage (var)
Long Accuracy
d-Vcross
ppm
12
-300
9.9970
9.9970
9.8720
175
300
10.0030
10.0533
ppm
ns
ns
ns
ps
1,2
2
2
1,2
1
Average period
Tperiod
Absolute min period
Rise Time
Tabsmin
tr
700
700
125
125
tf
VOH = 0.525V VOL = 0.175V
Fall Time
175
ps
1
d-tr
d-tf
Rise Time Variation
Fall Time Variation
30
ps
1
30
ps
1
Measurement from differential
wavefrom
SRC(7:0), VT = 50%
Measurement from differential
wavefrom
dt3
tsk3
Duty Cycle
Skew
45
55
%
ps
ps
1
1
1
250
125
tjcyc-cyc
Jitter, Cycle to cycle
1Guaranteed by design, not 100% tested in production.
2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFoutput is at 14.31818MHz
0815D—06/21/04
8
Integrated
Circuit
ICS954101
Systems, Inc.
Electrical Characteristics - PCICLK/PCICLK_F
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 30 pF (unless otherwise specified)
PARAMETER
Long Accuracy
Clock period
SYMBOL
ppm
CONDITIONS
MIN
TYP
MAX
UNITS
Notes
see Tperiod min-max values
33.33MHz output nominal
33.33MHz output spread
33.33MHz output nominal
33.33MHz output spread
-300
29.99100
29.99100
29.49100
29.49100
12
300
ppm
ns
ns
ns
ns
1,2
2
2
2
2
30.00900
30.15980
30.50900
30.65980
N/A
Tperiod
Absolute Min/Max Clock
period
Tabs
th1
tl1
Clk High Time
ns
1
Clock Low Time
Output High Voltage
Output Low Voltage
12
N/A
ns
1
VOH
VOL
IOH = -1 mA
IOL = 1 mA
2.4
V
0.55
-33
38
V
V OH @MIN = 1.0 V
VOH@ MAX = 3.135 V
VOL @ MIN = 1.95 V
VOL @ MAX = 0.4 V
-33
30
mA
mA
mA
mA
IOH
IOL
Output High Current
Output Low Current
Edge Rate
Edge Rate
Rise Time
Fall Time
Duty Cycle
Skew
Rising edge rate
Falling edge rate
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1
4
4
2
V/ns
V/ns
ns
1
1
1
1
1
1
1
1
tr1
tf1
0.5
0.5
45
2
ns
dt1
55
500
500
%
tsk1
VT = 1.5 V
ps
tjcyc-cyc
VT = 1.5 V
Jitter
ps
1Guaranteed by design, not 100% tested in production.
2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFoutput is at 14.31818MHz
Electrical Characteristics - USB_48MHz
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 20 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS Notes
Long Accuracy
Clock period
ppm
Tperiod
see Tperiod min-max values
48.0000MHz output nominal
-100
20.82570
100
20.83400
ppm
ns
1,2
2
Absolute Min/Max Clock
Tabs
Nominal
20.48125
21.18542
ns
2
period
th1
tl1
Clk High Time
8.094
7.694
-33
10.036
9.836
ns
ns
1
1
Clock Low Time
V
OH @ MIN = 1.0 V
mA
mA
mA
mA
V/ns
V/ns
IOH
IOL
Output High Current
V
OH@ MAX = 3.135 V
-33
V
OL @MIN = 1.95 V
OL @ MAX = 0.4 V
Rising edge rate
Falling edge rate
30
Output Low Current
V
38
2
2
Edge Rate
Edge Rate
1
1
1
1
tr1
tf1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
Rise Time
Fall Time
1
1
1.43
1.33
48
2
2
ns
ns
%
1
1
1
1
dt1
Duty Cycle
45
55
350
tjcyc-cyc
VT = 1.5 V
Jitter, Cycle to cycle
ps
1Guaranteed by design, not 100% tested in production.
2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFoutput is at 14.31818MHz
0815D—06/21/04
9
Integrated
Circuit
ICS954101
Systems, Inc.
Electrical Characteristics - DOT, 96MHz 0.7V Current Mode Differential Pair
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2 , RP=49.9 /
/
9,
REF
PARAMETER
SYMBOL
Zo
CONDITIONS
VO = Vx
MIN
TYP
MAX
UNITS NOTES
1
Current Source
Output Impedance
Voltage High
Voltage Low
Max Voltage
Min Voltage
Crossing Voltage
(abs)
3000
Statistical measurement
on single ended signal
Measurement on single
ended signal using
VHigh
VLow
Vovs
Vuds
660
-150
850
150
1150
1
mV
1
1
mV
1
-300
250
Vcross(abs)
d-Vcross
550
140
mV
mV
1
1
Crossing Voltage
Variation of crossing over
all edges
(var)
see Tperiod min-max
values
96.00MHz nominal
Long Accuracy
Average period
ppm
-100
100
ppm
ns
1,2
2
Tperiod
Tabsmin
10.4135
10.1635
10.4198
Absolute min period
96.00MHz nominal
ns
1,2
VOL = 0.175V, VOH
=
tr
tf
Rise Time
Fall Time
175
175
700
700
ps
ps
1
1
0.525V
VOH = 0.525V VOL
=
0.175V
d-tr
d-tf
Rise Time Variation
Fall Time Variation
125
125
ps
ps
1
1
Measurement from
differential wavefrom
Measurement from
dt3
Duty Cycle
45
55
%
1
1
tjcyc-cyc
Jitter, Cycle to cycle
250
ps
differential wavefrom
1Guaranteed by design, not 100% tested in production.
2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFoutput is at 14.31818MHz
0815D—06/21/04
10
Integrated
Circuit
ICS954101
Systems, Inc.
Electrical Characteristics - REF-14.318MHz
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 20 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS NOTES
Long Accuracy
Clock period
ppm
Tperiod
see Tperiod min-max values
14.318MHz output nominal
-300
69.82700
300
69.85500
ppm
ns
1
1
Absolute Min/Max Clock
period
Output High Voltage
Output Low Voltage
Tabs
Nominal
68.82033
2.4
70.86224
ns
2
VOH
VOL
IOH = -1 mA
IOL = 1 mA
V
V
1
1
0.4
-23
V OH @MIN = 1.0 V,
OH@MAX = 3.135 V
V
IOH
IOL
Output High Current
Output Low Current
-29
29
mA
mA
1
1
VOL @MIN = 1.95 V,
@MAX = 0.4 V
VOL
27
tr1
tf1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
Rise Time
Fall Time
Skew
1
1
2
2
ns
ns
ps
%
1
1
1
1
1
tsk1
500
55
dt1
VT = 1.5 V
Duty Cycle
45
tjcyc-cyc
VT = 1.5 V
Jitter
1000
ps
1Guaranteed by design, not 100% tested in production.
0815D—06/21/04
11
Integrated
Circuit
ICS954101
Systems, Inc.
I2C Table: Read-Back Register
Byte 0
Bit 7
Pin #
35,36
Name
Control Function
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Type
RW
RW
RW
RW
RW
RW
RW
0
1
PWD
CPUCLK2/RCCLK7 Enable
SRCCLK6 Enable
SRCCLK5 Enable
SRCCLK4 Enable
SRCCLK3 Enable
SRCCLK2 Enable
SRCCLK1 Enable
DISABLE
DISABLE
DISABLE
DISABLE
DISABLE
DISABLE
DISABLE
ENABLE
ENABLE
ENABLE
ENABLE
ENABLE
ENABLE
ENABLE
1
1
1
1
1
1
1
32,33
30,31
26,27
24,25
22,23
19,20
-
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RESERVED
I2C Table: Spreading and Device Behavior Control Register
Byte 1
Bit 7
Pin #
Name
PCI_F0 Enable
DOT_96MHz
USB_48MHz Enable
REFOUT Enable
Control Function
Type
RW
RW
RW
RW
0
1
PWD
54
Output Enable
Output Enable
Output Enable
Output Enable
RESERVED
Output Enable
Output Enable
Disable
Disable
Disable
Disable
Enable
Enable
Enable
Enable
1
1
1
1
1
1
1
14,15
12
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
52
40,41
43,44
CPUT1/CPUC1
CPUT0/CPUC0
RW
RW
Disable
Disable
Enable
Enable
SPREAD
ON
-
Bit 0
Spread Spectrum Mode
Spread Off
RW
SPREAD OFF
0
I2C Table: Output Control Register
Byte 2
Bit 7
Pin #
Name
PCICLK5
Control Function
Output Enable
Type
RW
0
1
PWD
1
5
Disable
Enable
4
3
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0
PCI_F2 Enable
PCI_F1 Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
RW
RW
RW
RW
RW
RW
RW
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
1
1
1
1
1
1
1
56
55
54
10
9
Bit 0
I2C Table: Output Control Register
Byte 3
Bit 7
Pin #
35,35
Name
CPU_ITP/SRCCLK7
SRCCLK6
Control Function
Type
RW
RW
RW
RW
RW
RW
RW
0
1
PWD
Free-Running
Free-Running
Free-Running
Free-Running
Free-Running
Free-Running
Free-Running
Stoppable
Stoppable
Stoppable
Stoppable
Stoppable
Stoppable
Stoppable
0
0
0
0
0
0
0
0
Free-Running
Control
32,33
30,31
26,27
24,25
22,23
19,20
-
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SRCCLK5
SRCCLK4
SRCCLK3
SRCCLK2
default:
not affected by
PCI/SRC_STOP
(Byte 6, bit 3)
SRCCLK1
RESERVED
0815D—06/21/04
12
Integrated
Circuit
ICS954101
Systems, Inc.
I2C Table: Output Control Register
Byte 4
Bit 7
Pin #
Name
Control Function
RESERVED
Driven in PD
Free-Running
Control
not affected by
RESERVED
RESERVED
RESERVED
Type
0
1
PWD
1
1
1
1
1
1
1
1
14,15
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DOT_96MHz
PCI_F2
PCI_F1
RW
RW
RW
RW
Driven
Hi-Z
10
9
8
Free-Running
Free-Running
Free-Running
Stoppable
Stoppable
Stoppable
PCI_F0
I2C Table: Output Control Register
Byte 5
Pin #
19,20,22,23,
Name
Control Function
Type
0
1
PWD
Drive Mode in
PCI_Stop
24,25,26,27,30,31,
32,33,35,36
Bit 7
SRC Stop Drive Mode
RW
Driven
Hi-Z
0
RESERVED
RESERVED
RESERVED
Bit 6
Bit 5
Bit 4
0
0
0
19,20,22,23,
24,25,26,27,30,31,
32,33,35,36
35,36
Bit 3
SRC PD Drive Mode
Drive Mode in PD
RW
Driven
Hi-Z
0
Bit 2
Bit 1
Bit 0
CPUCLK_ITP
CPUCLK1
CPUCLK0
Drive Mode in PD
Drive mode in PD
Drive mode in PD
RW
RW
RW
Driven
Driven
Driven
Hi-Z
Hi-Z
Hi-Z
0
0
0
40,41
43,44
I2C Table: Output Control Register
Byte 6
Pin #
Name
Control Function
Type
RW
0
1
PWD
-
Bit 7
Test Mode Selection
Test Clock Mode Entry
Test Mode Selection
Hi-Z
REF/N
Enable
0
-
-
52
Bit 6
Bit 5
Bit 4
Test Mode
RESERVED
Strength Prog
RW
Disable
0
0
1
REFOUT Strength
PCI/SRC_STOP
RW
RW
1X
2X
17,18,19,20,22,23,
24,25,26,27,30,31,
32,33,35,36
Enabled, all
stoppable PCI stoppable PCI
and SRC clocks and SRC clocks
Disabled, all
Stop all PCI and
SRC clocks
Bit 3
1
54,55,56,3,4,5,8,9,
are stopped.
are running
10
-
-
Bit 2
Bit 1
Bit 0
FS_C
FS_B
FS_A
readback
readback
readback
R
R
R
-
-
-
-
-
-
LATCHED
LATCHED
LATCHED
-
I2C Table: Vendor & Revision ID Register
Byte 7
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
Name
RID3
RID2
RID1
RID0
VID3
VID2
VID1
VID0
Control Function
Type
R
R
R
R
R
R
R
R
0
-
-
-
-
-
-
-
-
1
-
-
-
-
-
-
-
-
PWD
-
-
-
-
-
-
-
-
0
0
0
0
0
0
0
1
REVISION ID
VENDOR ID
0815D—06/21/04
13
Integrated
Circuit
ICS954101
Systems, Inc.
Test Clarification Table
Comments
HW
SW
TEST
ENTRY REF/N or
FS_C/TEST_ FS_B/TEST_
SEL
MODE
BIT
HI-Z
HW PIN HW PIN
B6b6
B6b7
OUTPUT
NORMAL
HI-Z
REF/N
REF/N
0
1
1
1
X
0
0
1
0
X
X
X
X
0
1
0
· FS_C/TEST_SEL is a 3-level latched input.
o Power-up w/ V >= 2.0V to select TEST
o Power-up w/ V < 2.0V to have pin function as FS_C.
· When pin is FS_C, VIH_FS and VIL_FS levels apply.
· FS_B/TEST_MODE is a low-threshold input
o VIH_FS and VIL_FS levels apply.
o TEST_MODE is a real time input
· TEST_SEL can be invoked after power up through
SMBus B6b6.
1
0
1
X
1
1
0
REF/N
HI-Z
X
o If TEST is selected by B6b6, only B6b7 controls
TEST_MODE. The FS_B/TEST_Mode pin is not used.
· Power must be cycled to exit TEST.
0
X
1
1
REF/N
B6b6: 1= ENTER TEST MODE, Default = 0 (NORMAL OPERATION)
B6b7: 1= REF/N, Default = 0 (HI-Z)
0815D—06/21/04
14
Integrated
Circuit
ICS954101
Systems, Inc.
c
56-Lead, 300 mil Body, 25 mil, SSOP
N
In Millimeters
In Inches
SYMBOL
COMMON DIMENSIONS
COMMON DIMENSIONS
L
MIN
2.41
0.20
0.20
0.13
MAX
2.80
0.40
0.34
0.25
MIN
.095
.008
.008
.005
MAX
.110
.016
.0135
.010
A
A1
b
E1
E
INDEX
AREA
c
D
E
E1
e
SEE VARIATIONS
SEE VARIATIONS
10.03
7.40
10.68
7.60
.395
.291
.420
.299
1
2
α
hh xx 45°
0.635 BASIC
0.025 BASIC
D
h
L
0.38
0.50
0.64
1.02
.015
.020
.025
.040
N
a
SEE VARIATIONS
SEE VARIATIONS
A
0°
8°
0°
8°
A1
VARIATIONS
- C -
D mm.
D (inch)
N
MIN
18.31
MAX
18.55
MIN
.720
MAX
.730
e
SEATING
PLANE
56
b
.10 (.004) C
Reference Doc.: JEDEC Publication 95, MO-118
10-0034
Ordering Information
ICS954101yFLFT
Example:
ICS XXXX y F LF T
Designation for tape and reel packaging
Lead Free (optional)
Package Type
F = SSOP
Revision Designator (will not correlate with datasheet revision)
DeviceType (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
0815D—06/21/04
15
Integrated
Circuit
ICS954101
Systems, Inc.
c
56-Lead 6.10 mm. Body, 0.50 mm. Pitch TSSOP
N
(240 mil)
(20 mil)
In Millimeters
COMMON DIMENSIONS COMMON DIMENSIONS
In Inches
L
SYMBOL
MIN
--
0.05
0.80
0.17
0.09
MAX
1.20
0.15
1.05
0.27
0.20
MIN
--
.002
.032
.007
.0035
MAX
.047
.006
.041
.011
.008
E1
E
A
A1
A2
b
INDEX
AREA
c
1
2
D
E
SEE VARIATIONS
8.10 BASIC
SEE VARIATIONS
0.319 BASIC
a
D
E1
e
6.00
0.50 BASIC
6.20
.236
0.020 BASIC
.244
L
0.45
0.75
.018
.030
N
SEE VARIATIONS
SEE VARIATIONS
A
A2
a
aaa
0°
--
8°
0.10
0°
--
8°
.004
A1
- C -
VARIATIONS
e
SEATING
PLANE
D mm.
D (inch)
b
N
MIN
13.90
MAX
14.10
MIN
.547
MAX
.555
aaa
C
56
Reference Doc.: JEDEC Publication 95, MO-153
10-0039
Ordering Information
ICS954101yGLFT
Example:
ICS XXXX y G LF T
Designation for tape and reel packaging
Lead Free (optional)
Package Type
G = TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
0815D—06/21/04
16
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