ICS97ULP844AH-T [ICSI]
1.8V Low-Power Wide-Range Frequency Clock Driver; 1.8V低功耗宽范围频率时钟驱动器
| 型号： | ICS97ULP844AH-T |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | 1.8V Low-Power Wide-Range Frequency Clock Driver |
| 文件： | 总12页 (文件大小：134K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS97ULP844A
Integrated
Circuit
Systems,Inc.
1.8V Low-Power Wide-Range Frequency Clock Driver
RecommendedApplication:
Pin Configuration
•
•
DDR2 Memory Modules / Zero Delay Board Fan Out
Provides complete DDR DIMM logic solution with
ICSSSTU32864/SSTUF32864/SSTUF32866
1
2
3
4
5
A
B
C
D
E
F
ProductDescription/Features:
•
•
•
•
•
Low skew, low jitter PLL clock driver
1 to 4 differential clock distribution (SSTL_18)
Feedback pins for input to output synchronization
Spread Spectrum tolerant inputs
Auto PD when input signal is at a certain logic state
SwitchingCharacteristics:
•
•
•
•
Period jitter:40ps
Half-period jitter: 60ps
CYCLE - CYCLE jitter 40ps
OUTPUT - OUTPUT skew: 40ps
28-Ball BGA
Top View
Block Diagram
Ball Assignments
1
2
3
4
5
CLKT0
CLKC0
LD* or OE
OE
A
B
C
D
E
F
CLKT0
CLKC0
CLKC1
CLKT1
FB_INT
Powerdown
Control and
Test Logic
CLKT1
CLKC1
OS
CK_INT
CK_INC
AGND
VDD
OE
NB
VDD
VDD
OS
FB_INC
FB_OUTC
FB_OUTT
GND
AVDD
CLKT2
CLKC2
PLL bypass
LD*
CLKT3
CLKC3
GND
GND
CLKT3
VDD
GND
GND
CLKT2
AVDD
NB
CLKC3
CLKC2
GND
CLK_INT
CLK_INC
FB_OUTT
FB_OUTC
10K-100k
PLL
GND
FB_INT
FB_INC
* The Logic Detect (LD) powers down the device when a
logic low is applied to both CLK_INT and CLK_INC.
1110B—06/06/05
ICS97ULP844A
Pin Descriptions
Terminal
Name
Electrical
Characteristics
Description
AGND
AVDD
Analog Ground
Analog power
Ground
1.8 V nominal
CLK_INT
CLK_INC
FB_INT
Clock input with a (10K-100K Ohm) pulldown resistor
Complentary clock input with a (10K-100K Ohm) pulldown resistor
Feedback clock input
Differential input
Differential input
Differential input
FB_INC
FB_OUTT
FB_OUTC
OE
Complementary feedback clock input
Feedback clock output
Differential input
Differential output
Differential output
LVCMOS input
LVCMOS input
Ground
Complementary feedback clock output
Output Enable (Asynchronous)
OS
Output Select (tied to GND or VDDQ
)
GND
Ground
VDDQ
Logic and output power
Clock outputs
1.8V nominal
CLKT[0:3]
CLKC[0:3]
NB
Differential outputs
Differential outputs
Complementary clock outputs
No ball
The PLL clock buffer, ICS97ULP844A, is designed for a VDDQ of 1.8 V, a AVDD of 1.8 V and differential data input and
output levels. Package options include a plastic 28-ball VFBGA.
ICS97ULP844A is a zero delay buffer that distributes a differential clock input pair (CLK_INT, CLK_INC) to four
differential pair of clock outputs (CLKT[0:3], CLKC[0:3]) and one differential pair feedback clock outputs (FB_OUTT,
FBOUTC).The clock outputs are controlled by the input clocks (CLK_INT, CLK_INC), the feedback clocks (FB_INT,
FB_INC), theLVCMOSprogrampins(OE, OS)andtheAnalogPowerinput(AVDD).WhenOEislow, theoutputs(except
FB_OUTT/FB_OUTC) are disabled while the internal PLL continues to maintain its locked-in frequency. OS (Output
Select) is a program pin thatmustbe tied toGND orVDDQ.WhenOSishigh, OEwillfunctionasdescribedabove.When
OS is low, OE has no effect on CLKT2/CLKC2 (they are free running in addition to FB_OUTT/FB_OUTC).When AVDD
is grounded, the PLL is turned off and bypassed for test purposes.
When both clock signals (CLK_INT, CLK_INC) are logic low, the device will enter a low power mode. An input logic
detection circuit on the differential inputs, independent from the input buffers, will detect the logic low level and perform
alowpowerstatewherealloutputs, thefeedbackandthePLLareOFF.Whentheinputstransitionfrombothbeinglogic
low to being differential signals, the PLL will be turned back on, the inputs and outputs will be enabled and the PLL
willobtainphaselockbetweenthefeedbackclockpair(FB_INT, FB_INC)andtheinputclockpair(CLK_INT, CLK_INC)
within the specified stabilization time tSTAB
.
The PLL in ICS97ULP844A clock driver uses the input clocks (CLK_INT, CLK_INC) and the feedback clocks (FB_INT,
FB_INC) to provide high-performance, low-skew, low-jitter output differential clocks (CLKT[0:4], CLKC[0:4]).
ICS97ULP844A is also able to track Spread Spectrum Clocking (SSC) for reduced EMI.
ICS97ULP844A is characterized for operation from 0°C to 70°C.
1110B—06/06/05
2
ICS97ULP844A
Function Table
Inputs
OE OS CLK_INT
Outputs
FB_OUTT
PLL
AVDD
GND
GND
GND
CLK_INT
CLKT
L
CLKC
H
FB_OUTC
H
H
L
X
X
H
L
H
L
H
L
L
H
L
H
L
Bypassed/Off
Bypassed/Off
Bypassed/Off
H
L
H
*L(Z)
*L(Z)
H
*L(Z),
CLKT2
active
*L(Z),
CLKC2
active
L
Bypassed/Off
GND
L
L
L
L
H
L
H
L
L
H
L
H
1.8V(nom)
1.8V(nom)
*L(Z)
*L(Z)
L
H
L
On
On
*L(Z),
CLKT2
active
*L(Z),
CLKC2
active
H
H
1.8V(nom)
1.8V(nom)
1.8V(nom)
1.8V(nom)
H
H
X
X
X
X
X
X
L
H
L
H
L
L
H
H
L
L
H
H
L
On
On
Off
L
*L(Z)
*L(Z)
*L(Z)
*L(Z)
H
H
Reserved
*L(Z) means the outputs are disabled to a low stated meeting the IODL limit.
1110B—06/06/05
3
ICS97ULP844A
Absolute Maximum Ratings
Supply Voltage (VDDQ & AVDD) . . . . . . . . . -0.5V to 2.5V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.5V to VDDQ + 0.5V
Ambient OperatingTemperature . . . . . . . . . . 0°C to +70°C
StorageTemperature . . . . . . . . . . . . . . . . . . . -65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These
ratingsarestressspecificationsonlyandfunctionaloperationofthedeviceattheseoranyotherconditionsabovethose
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage AVDDQ, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated)
SYMBOL
MIN
TYP
MAX
250
UNITS
µA
PARAMETER
Input High Current
(CLK_INT, CLK_INC)
Input Low Current (OE,
OS, FB_INT, FB_INC)
Output Disabled Low
Current
CONDITIONS
IIH
VI = VDDQ or GND
IIL
VI = VDDQ or GND
10
µA
µA
IODL
OE = L, VODL = 100mV
100
IDD1.8
IDDLD
VIK
CL = 0pf @ 270MHz
CL = 0pf
VDDQ = 1.7V Iin = -18mA
TBD
500
-1.2
Operating Supply
Current
mA
µA
V
Input Clamp Voltage
µ
V
DDQ - 0.2
I
I
OH = -100 A
V
V
V
V
pF
pF
VOH
VOL
High-level output voltage
OH = -9 mA
IOL=100 A
1.1
1.45
0.25
µ
0.10
0.6
3
Low-level output voltage
IOL=9 mA
Input Capacitance1
Output Capacitance1
CIN
COUT
VI = GND or VDDQ
2
2
3
VOUT = GND or VDDQ
1Guaranteed by design, not 100% tested in production.
1110B—06/06/05
4
ICS97ULP844A
Recommended Operating Condition
(see note1)
TA = 0 - 70°C; Supply Voltage AVDD, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated)
PARAMETER
Supply Voltage
SYMBOL
CONDITIONS
MIN
1.7
TYP
1.8
MAX
1.9
UNITS
V
VDDQ, AVDD
CLK_INT, CLK_INC, FB_INC,
FB_INT
OE, OS
CLK_INT, CLK_INC, FB_INC,
FB_INT
OE, OS
0.35 x VDDQ
0.35 x VDDQ
V
V
V
V
V
Low level input voltage
High level input voltage
VIL
0.65 x VDDQ
0.65 x VDDQ
-0.3
VIH
VIN
DC input signal voltage
(note 2)
VDDQ + 0.3
DC - CLK_INT, CLK_INC,
FB_INC, FB_INT
AC - CLK_INT, CLK_INC,
FB_INC, FB_INT
0.3
0.6
V
V
DDQ + 0.4
DDQ + 0.4
V
V
V
V
Differential input signal
voltage (note 3)
VID
Output differential cross-
voltage (note 4)
Input differential cross-
voltage (note 4)
VOX
VIX
VDDQ/2 - 0.10
VDDQ/2 + 0.10
VDDQ/2 - 0.15 VDD/2 VDDQ2 + 0.15
High level output current
IOH
IOL
-9
9
mA
mA
Low level output current
Operating free-air
temperature
TA
0
70
°C
Notes:
1. Unused inputs must be held high or low to prevent them from floating.
2. DC input signal voltage specifies the allowable DC execution of differential input.
3. Differential inputs signal voltages specifies the differential voltage [VTR-VCP]
required for switching, where VTR is the true input level and VCP is the
complementary input level.
4. Differential cross-point voltage is expected to track variations of VDDQ and is the
voltage at which the differential signal must be crossing.
1110B—06/06/05
5
ICS97ULP844A
Timing Requirements
TA = 0 - 70°C Supply Voltage AVDD, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated)
CONDITIONS
PARAMETER
SYMBOL
freqop
MIN
95
TYP
MAX
370
Max clock frequency
1.8V+0.1V @ 25°C
Application Frequency
Range
freqApp
dtin
1.8V+0.1V @ 25°C
160
40
350
60
Input clock duty cycle
CLK stabilization
TSTAB
2.4
2.95
Switching Characteristics1
TA = 0 - 70°C Supply Voltage AVDD, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated)
PARAMETER
Output enable time
Output disable time
Period jitter
CONDITION
OE to any output
OE to any output
SYMBOL
ten
tdis
tjit (per)
tjit(hper)
MIN
TYP
4.73
5.82
MAX UNITS
8
8
30
60
4
ns
ns
ps
-30
-60
1
0.5
1.5
0
0
-20
-50
Half-period jitter
ps
2.5
2.5
v/ns
v/ns
v/ns
ps
ps
ps
ps
ps
kHz
Input Clock
Output Enable (OE), (OS)
Input slew rate
SLr1(i)
3
Output clock slew rate
Cycle-to-cycle period jitter
SLr1(o)
tjit(cc+)
tjit(cc-)
40
-40
20
50
50
33
t( )dyn
Dynamic Phase Offset
Static Phase Offset
Output to Output Skew
SSC modulation frequency
SSC clock input frequency
deviation
2
0
tSPO
tskew
30.00
0.00
-0.50
%
PLL Loop bandwidth (-3 dB
from unity gain)
2.0
MHz
Notes:
1. Switching characteristics guaranteed for application frequency range.
2. Static phase offset shifted by design.
1110B—06/06/05
6
ICS97ULP844A
Parameter Measurement Information
V
DD
V
(CLKC)
V
(CLKC)
ICS97ULP844
GND
Figure 1. IBIS Model Output Load
VDD/2
C = 10 pF
- GND
SCOPE
ICS97ULP844A
R = 10Ω Z = 50Ω
Z = 60Ω
Z = 2.97"
R = 1M
Ω
C = 1 pF
Z = 120Ω
R = 10Ω
V
(TT)
Z = 50Ω
Z = 60Ω
Z = 2.97"
R = 1M
Ω
C = 1 pF
V
(TT)
C = 10 pF
Note: VTT = GND
GND
-VDD/2
Figure 2. Output Load Test Circuit
YX, FB_OUTC
YX, FB_OUTT
t
t
c(n+1)
c(n)
t
= t
t
jit(cc) c(n) c(n+1)
Figure 3. Cycle-to-Cycle Jitter
1110B—06/06/05
7
ICS97ULP844A
Parameter Measurement Information
CLK_INC
CLK_INT
FB_INC
FB_INT
t
t
( ) n
( ) n+1
n = N
1
t
( ) n
t
=
( )
N
(N is a large number of samples)
Figure 4. Static Phase Offset
YX
#
YX
YX, FB_OUTC
YX, FB_OUTT
t(skew)
Figure 5. Output Skew
YX, FB_OUTC
YX, FB_OUTT
tC(n)
YX, FB_OUTC
YX, FB_OUTT
1
fO
1
fO
t(jit_per) tc(n)
=
-
Figure 6. Period Jitter
1110B—06/06/05
8
ICS97ULP844A
Parameter Measurement Information
YX, FB_OUTC
YX, FB_OUTT
t
t
jit(hper_n+1)
jit(hper_n)
1
f
o
tjit(hper) = tjit(hper_n)
1
2xfO
-
Figure 7. Half-Period Jitter
80%
80%
V , V
ID OD
20%
20%
Clock Inputs
and Outputs
t
t
slf
slr
Figure 8. Input and Output Slew Rates
1110B—06/06/05
9
ICS97ULP844A
CK
CK
FBIN
FBIN
t(
t(
)
)
SSC OFF
SSC ON
SSC OFF
SSC ON
t(
t(
t(
t(
)dyn
)dyn
)dyn
)dyn
Figure 9. Dynamic Phase Offset
50% VDDQ
OE
t
Y
en
50% VDDQ
Y
Y/ Y
OE
50% VDDQ
t
dis
Y
Y
50 % VDDQ
Figure 10. Time delay between OE and Clock Output (Y,Y)
1110B—06/06/05
10
ICS97ULP844A
Figure 11. AVDD Filtering
- Place the 2200pF capacitor close to the PLL.
- Use a wide trace for the PLL analog power & ground. Connect PLL & caps to AGND trace & connect trace to one
GND via (farthest from PLL).
- Recommended bead: Fair-Rite P/N 2506036017Y0 or equivalent (0.8 Ohm DC max, 600 Ohms @ 100 MHz).
1110B—06/06/05
11
ICS97ULP844A
Millimeter
NOM
0.90
0.20
0.20
0.50
0.40
4.00
Inch
NOM
0.035
0.008
0.008
0.020
0.016
0.157
SYMBOL
MIN
0.80
0.165
0.16
0.475
0.35
3.90
MAX
1.00
0.235
0.24
0.525
0.45
4.10
MIN
MAX
0.039
0.009
0.009
0.021
0.018
0.161
A
A1
A2
A3
b
0.031
0.006
0.006
0.019
0.014
0.154
D
D1
E
2.60 BSC
4.50
0.102 BSC
0.177
4.40
4.60
0.173
0.181
E1
e
3.25 BSC
0.65 BSC
0.128 BSC
0.026 BSC
Ordering Information
ICS97ULP844AH(LF)-T
Example:
ICS XXXX y H (LF)- T
Designation for tape and reel packaging
RoHS Compliant (Optional)
Package Type
H = BGA
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
1110B—06/06/05
12
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