ICS97ULP877AHLF-T [ICSI]
1.8V Low-Power Wide-Range Frequency Clock Driver; 1.8V低功耗宽范围频率时钟驱动器
| 型号： | ICS97ULP877AHLF-T |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | 1.8V Low-Power Wide-Range Frequency Clock Driver |
| 文件： | 总14页 (文件大小：176K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS97ULP877A
Integrated
Circuit
Systems,Inc.
1.8V Low-Power Wide-Range Frequency Clock Driver
RecommendedApplication:
Pin Configuration
1
2
3
4
5
6
•
•
DDR2 Memory Modules / Zero Delay Board Fan Out
Provides complete DDR DIMM logic solution with
ICSSSTU32864/SSTUF32864/SSTUF32866/
SSTUA32864/SSTUA32866/SSTUA32S868/
SSTUA32S865/SSTUA32S869
A
B
C
D
E
F
ProductDescription/Features:
•
•
•
•
•
Low skew, low jitter PLL clock driver
G
1 to 10 differential clock distribution (SSTL_18)
Feedback pins for input to output synchronization
Spread Spectrum tolerant inputs
H
J
K
Auto PD when input signal is at a certain logic state
52-Ball BGA
SwitchingCharacteristics:
Top View
•
•
•
•
Period jitter:40ps (DDR2-400/533)
30ps (DDR2-667)
Half-period jitter: 60ps (DDR2-400/533)
50ps (DDR2-667)
OUTPUT - OUTPUT skew: 40ps (DDR2-400/533)
30ps (DDR2-667)
CYCLE - CYCLE jitter 40ps
1
2
3
4
5
6
A
B
C
D
E
F
G
H
J
CLKT1
CLKC1
CLKC2
CLKT2
CLK_INT
CLK_INC
AGND
AVDD
CLKT3
CLKC3
CLKT0
GND
GND
VDDQ
VDDQ
VDDQ
VDDQ
GND
CLKC0
GND
NB
CLKC5
GND
NB
CLKT5
GND
GND
OS
CLKT6
CLKC6
CLKC7
CLKT7
VDDQ
NB
VDDQ
NB
VDDQ
OE
VDDQ
GND
GND
CLKC9
FB_INT
FB_INC
FB_OUTC
FB_OUTT
CLKT8
NB
NB
VDDQ
NB
VDDQ
NB
GND
CLKC4
GND
CLKT4
GND
CLKT9
K
CLKC8
Block Diagram
CLKT0
CLKC0
LD(1) or OE
OE
LD(1), OS, or OE
CLKT1
CLKC1
OS
Powerdown
Control and
Test Logic
AVDD
CLKT2
CLKC2
VDDQ
CLKC2
CLKT2
1
2
CLKC7
CLKT7
VDDQ
30
PLL Bypass
29
28
27
26
25
24
23
LD(1)
3
CLKT3
CLKC3
CLK_INT
CLK_INC
VDDQ
4
FB_INT
FB_INC
FB_OUTC
FB_OUTT
VDDQ
5
CLKT4
CLKC4
6
AGND
7
8
AVDD
VDDQ
GND
CLKT5
CLKC5
9
OE
22
21
CLK_INT
CLK_INC
OS
10
CLKT6
CLKC6
PLL
CLKT7
CLKC7
GND
FB_INT
FB_INC
CLKT8
CLKC8
CLKT9
CLKC9
40-Pin MLF
NOTE:
1. TheLogicDetect(LD)powersdownthedevicewhenalogicLOWis
applied to both CLK_INT and CLK+INC.
FB_OUTT
FB_OUTC
7116—03/27/07
ICS97ULP877A
Pin Descriptions
Terminal
Name
Electrical
Characteristics
Description
AGND
AVDD
Analog Ground
Analog power
Ground
1.8 V nominal
CLK_INT
CLK_INC
FB_INT
Clock input with a (10K-100K Ohm) pulldown resistor
Complentary clock input with a (10K-100K Ohm) pulldown resistor
Feedback clock input
Differential input
Differential input
Differential input
FB_INC
FB_OUTT
FB_OUTC
OE
Complementary feedback clock input
Feedback clock output
Differential input
Differential output
Differential output
LVCMOS input
LVCMOS input
Ground
Complementary feedback clock output
Output Enable (Asynchronous)
OS
Output Select (tied to GND or VDDQ
)
GND
Ground
VDDQ
Logic and output power
Clock outputs
1.8V nominal
CLKT[0:9]
CLKC[0:9]
NB
Differential outputs
Differential outputs
Complementary clock outputs
No ball
The PLL clock buffer, ICS97ULP877A, is designed for aVDDQ of 1.8V, a AVDD of 1.8V and differential data input and
output levels. Package options include a plastic 52-ball VFBGA and a 40-pin MLF.
ICS97ULP877A is a zero delay buffer that distributes a differential clock input pair (CLK_INT, CLK_INC) to ten
differential pair of clock outputs (CLKT[0:9], CLKC[0:9]) and one differential pair feedback clock outputs (FB_OUTT,
FBOUTC).The clock outputs are controlled by the input clocks (CLK_INT, CLK_INC), the feedback clocks (FB_INT,
FB_INC), theLVCMOSprogrampins(OE, OS)andtheAnalogPowerinput(AVDD).WhenOEislow, theoutputs(except
FB_OUTT/FB_OUTC) are disabled while the internal PLL continues to maintain its locked-in frequency. OS (Output
Select) is a program pin that must be tied to GND orVDDQ.WhenOSishigh, OEwillfunctionasdescribedabove.When
OS is low, OE has no effect on CLKT7/CLKC7 (they are free running in addition to FB_OUTT/FB_OUTC).When AVDD
is grounded, the PLL is turned off and bypassed for test purposes.
When both clock signals (CLK_INT, CLK_INC) are logic low, the device will enter a low power mode. An input logic
detection circuit on the differential inputs, independent from the input buffers, will detect the logic low level and perform
alowpowerstatewherealloutputs, thefeedbackandthePLLareOFF.Whentheinputstransitionfrombothbeinglogic
low to being differential signals, the PLL will be turned back on, the inputs and outputs will be enabled and the PLL
willobtainphaselockbetweenthefeedbackclockpair(FB_INT, FB_INC)andtheinputclockpair(CLK_INT, CLK_INC)
within the specified stabilization time tSTAB
.
The PLL in ICS97ULP877A clock driver uses the input clocks (CLK_INT, CLK_INC) and the feedback clocks (FB_INT,
FB_INC) to provide high-performance, low-skew, low-jitter output differential clocks (CLKT[0:9], CLKC[0:9]).
ICS97ULP877A is also able to track Spread Spectrum Clocking (SSC) for reduced EMI.
ICS97ULP877A is characterized for operation from 0°C to 70°C.
7116—03/27/07
2
ICS97ULP877A
Function Table
Inputs
OE OS CLK_INT
Outputs
FB_OUTT
PLL
AVDD
GND
GND
GND
CLK_INT
CLKT
L
CLKC
H
FB_OUTC
H
H
L
X
X
H
L
H
L
H
L
L
H
L
H
L
Bypassed/Off
Bypassed/Off
Bypassed/Off
H
L
H
*L(Z)
*L(Z)
H
*L(Z),
CLKT7
active
*L(Z),
CLKC7
active
L
Bypassed/Off
GND
L
L
L
L
H
L
H
L
L
H
L
H
1.8V(nom)
1.8V(nom)
*L(Z)
*L(Z)
L
H
L
On
On
*L(Z),
CLKT7
active
*L(Z),
CLKC7
active
H
H
1.8V(nom)
1.8V(nom)
1.8V(nom)
1.8V(nom)
H
H
X
X
X
X
X
X
L
H
L
H
L
L
H
H
L
L
H
H
L
On
On
Off
L
*L(Z)
*L(Z)
*L(Z)
*L(Z)
H
H
Reserved
*L(Z) means the outputs are disabled to a low stated meeting the IODL limit.
0981C—04/05/05
3
ICS97ULP877A
Absolute Maximum Ratings
Supply Voltage (VDDQ & AVDD) . . . . . . . . . -0.5V to 2.5V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.5V to VDDQ + 0.5V
Ambient OperatingTemperature . . . . . . . . . . 0°C to +70°C
StorageTemperature . . . . . . . . . . . . . . . . . . . -65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device.These
ratingsarestressspecificationsonlyandfunctionaloperationofthedeviceattheseoranyotherconditionsabovethose
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage AVDDQ, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated)
PARAMETER
Input High Current
(CLK_INT, CLK_INC)
Input Low Current (OE,
OS, FB_INT, FB_INC)
Output Disabled Low
Current
SYMBOL
CONDITIONS
MIN
TYP
MAX
250
UNITS
µA
IIH
VI = VDDQ or GND
IIL
VI = VDDQ or GND
10
µA
µA
IODL
OE = L, VODL = 100mV
100
Operating Supply
Current
IDD1.8 CL = 0pf @ 270MHz
200
500
-1.2
mA
µA
IDDLD
VIK
CL = 0pf
Input Clamp Voltage
High-level output
voltage
VDDQ = 1.7V Iin = -18mA
IOH = -100 ٛA
V
V
VDDQ - 0.2
1.1
VOH
VOL
I
I
I
OH = -9 mA
OL=100 ٛA
OL=9 mA
1.45
0.25
V
0.10
0.6
3
V
Low-level output voltage
V
Input Capacitance1
Output Capacitance1
CIN
VI = GND or VDDQ
2
2
pF
pF
COUT
VOUT = GND or VDDQ
3
1Guaranteed by design, not 100% tested in production.
7116—03/27/07
4
ICS97ULP877A
Recommended Operating Condition
(see note1)
TA = 0 - 70°C; Supply Voltage AVDD, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated)
PARAMETER
Supply Voltage
SYMBOL
DDQ, AVDD
CONDITIONS
MIN
1.7
TYP
1.8
MAX
1.9
UNITS
V
V
CLK_INT, CLK_INC, FB_INC,
FB_INT
OE, OS
CLK_INT, CLK_INC, FB_INC,
FB_INT
OE, OS
0.35 x VDDQ
0.35 x VDDQ
V
V
V
V
V
Low level input voltage
High level input voltage
VIL
0.65 x VDDQ
0.65 x VDDQ
-0.3
VIH
VIN
DC input signal voltage
(note 2)
VDDQ + 0.3
DC - CLK_INT, CLK_INC,
FB_INC, FB_INT
AC - CLK_INT, CLK_INC,
FB_INC, FB_INT
0.3
0.6
V
V
DDQ + 0.4
DDQ + 0.4
V
V
V
V
Differential input signal
voltage (note 3)
VID
Output differential cross-
voltage (note 4)
Input differential cross-
voltage (note 4)
VOX
VIX
VDDQ/2 - 0.10
VDDQ/2 + 0.10
VDDQ/2 - 0.15 VDD/2 VDDQ2 + 0.15
High level output current
IOH
IOL
-9
9
mA
mA
Low level output current
Operating free-air
temperature
TA
0
70
°C
Notes:
1. Unused inputs must be held high or low to prevent them from floating.
2. DC input signal voltage specifies the allowable DC execution of differential input.
3. Differential inputs signal voltages specifies the differential voltage [VTR-VCP]
required for switching, where VTR is the true input level and VCP is the
complementary input level.
4. Differential cross-point voltage is expected to track variations of VDDQ and is the
voltage at which the differential signal must be crossing.
0981C—04/05/05
5
ICS97ULP877A
Timing Requirements
TA = 0 - 70°C Supply Voltage AVDD, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated)
CONDITIONS
PARAMETER
SYMBOL
freqop
MIN
95
MAX
410
UNITS
MHz
Max clock frequency
1.8V+0.1V @ 25°C
Application Frequency
Range
freqApp
dtin
1.8V+0.1V @ 25°C
160
40
350
60
MHz
%
Input clock duty cycle
CLK stabilization
TSTAB
15
µs
NOTE: The PLL must be able to handle spread spectrum induced skew.
NOTE: Operating clock frequency indicates a range over which the PLL must be able to lock, but in which it is not
required to meet the other timing parameters. (Used for low speed system debug.)
NOTE: Application clock frequency indicates a range over which the PLL must meet all timing parameters.
NOTE: Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback
signal to its reference signal, within the value specificied by the Static Phase Offset (t(Æ ), after power-up. During
normal operation, the stabilization time is also the time required for the integrated PLL circuit to obtain phase lock
of its feedback signal to its reference signal when CK and CK go to a logic low state, enter the power-down mode
and later return to active operation. CK and CK may be left floating after they have been driven low for one
complete clock cycle.
7116—03/27/07
6
ICS97ULP877A
Switching Characteristics1
TA = 0 - 70°C Supply Voltage AVDD, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated)
PARAMETER
Output enable time
Output disable time
SYMBOL
CONDITION
OE to any output
OE to any output
(MHz)
MIN
TYP
4.73
5.82
MAX
8
8
UNITS
ns
ns
ten
tdis
160 to 410
160 to 270
271 to 410
160 to 270
271 to 410
-40
-30
-60
-50
1
0.5
1.5
0
40
30
60
50
4
ps
ps
ps
ps
v/ns
v/ns
v/ns
ps
ps
ps
tjit (per)
tjit(hper)
Period jitter
Half-period jitter
Input Clock
Output Enable (OE), (OS)
2.5
2.5
Input slew rate
SLr1(i)
Output clock slew rate
Cycle-to-cycle period jitter
3
160 to 410
SLr1(o)
tjit(cc+)
tjit(cc-)
40
-40
50
20
50
0
160 to 270
271 to 410
271 to 410
-50
-20
-50
t(Ø)dyn
Dynamic Phase Offset
ps
ps
2
Static Phase Offset
0
tSPO
∑
(su)
t jit (per) + t (Ø)dyn + t skew(o)
80
ps
t
(Ø)dyn + tskew(o)
∑
60
40
30
33
ps
ps
ps
t (h)
160 to 270
271 to 410
tskew
Output to Output Skew
SSC modulation frequency
SSC clock input frequency
deviation
30.00
0.00
kHz
-0.50
%
PLL Loop bandwidth (-3 dB
from unity gain)
2.0
MHz
Notes:
1. Switching characteristics guaranteed for application frequency range.
2. Static phase offset shifted by design.
0981C—04/05/05
7
ICS97ULP877A
Parameter Measurement Information
VDD
VCLK
VCLK
ICS97ULP877A
GND
IBIS Model Output Load
VDD/2
ICS97ULP877A
SCOPE
C = 10pF
GND
R = 10Ω
Z = 60Ω
Z = 50Ω
Z = 50Ω
L = 2.97"
R = 1MΩ
C = 1pF
Z = 120Ω
R = 10Ω
Z = 60Ω
VTT
VTT
C = 10pF
L = 2.97"
R = 1MΩ
C = 1pF
GND
Note: VTT = GND
VDD/2
Output LoadTest Circuit
Yx, FB_OUTC
Yx, FB_OUTT
tC(n)
tC(n+1)
tJIT(CC) = tC(n) tC(n+1)
Cycle-to-Cycle Jitter
7116—03/27/07
8
ICS97ULP877A
Parameter Measurement Information
CLK_INC
CLK_INT
FB_INC
FB_INT
t(∅)n+1
t(∅)n
n = N
Σ1 t(∅)n
t(∅) =
n
(N is a large number of samples)
Static Phase Offsel
Yx
Yx
Yx, FB_OUTC
Yx, FB_OUTT
t(SKEW)
Output Skew
Yx, FB_OUTC
Yx, FB_OUTT
tC(n)
Yx, FB_OUTC
Yx, FB_OUTT
1
fo
1
t(JIT_PER) = tC(n)
fo
Period Jitter
0981C—04/05/05
9
ICS97ULP877A
Parameter Measurement Information
Yx, FB_OUTC
Yx, FB_OUTT
tJIT(HPER_n)
tJIT(HPER_n+1)
1
fo
1
2xfo
tJIT(HPER) = tJIT(HPER_n)
Half-PeriodJitter
80%
80%
VID, VOD
20%
20%
Clock Inputs
and Outputs
tSLR
tSLF
Input and Output Skew Rates
7116—03/27/07
10
ICS97ULP877A
Parameter Measurement Information
CLK
CLK
FBIN
FBIN
t(Ø)
t(Ø)
SSC OFF
SSC ON
SSC OFF
SSC ON
t(Ø)DYN
t(Ø)DYN
t(Ø)DYN
t(Ø)DYN
Dynamic Phase Offset
50% VDDQ
OE
tEN
Y
50% VDDQ
Y/Y
Y
OE
50% VDDQ
tDIS
Y
50% VDDQ
Y
Time Delay Between OE and Clock Output (Y, Y)
0981C—04/05/05
11
ICS97ULP877A
BEAD
0603
R1
VIA
CARD
AVDD
VDDQ
4.7uF
1206
0.1uF
0603
2200pF
0603
PLL
1Ω
GND
AGND
VIA
CARD
AVDD Filtering
- Place the 2200pF capacitor close to the PLL.
- Use a wide trace for the PLL analog power & ground. Connect PLL & caps to AGND trace & connect trace to one
GND via (farthest from PLL).
- Recommended bead:Fair-Rite P/N 2506036017Y0 or equivalent (0.8 Ohm DC max, 600 Ohms @ 100 MHz).
7116—03/27/07
12
ICS97ULP877A
C
SEATING
PLANE
Numeric Designations
for Horizontal Grid
A1
b REF
T
4
3
2
1
A
B
C
D
Alpha Designations
for Vertical Grid
(Letters I, O, Q, and
S not used)
D
d TYP
D1
-e-
TYP
TOP VIEW
E
c REF
-e-
TYP
h TYP
0.12
C
E1
ALL DIMENSIONS IN MILLIMETERS
----- BALL GRID -----
Max.
REF. DIMENSIONS
D
E
T
e
HORIZ
VERT
TOTAL
d
h
D1
5.85 Bsc
E1
b
c
Min/Max
0.86/1.00
Min/Max
0.35/0.45
Min/Max
0.15/0.21
7.00 Bsc
4.50 Bsc
0.65 Bsc
6
10
60
3.25 Bsc
0.575
0.625
**
Note: Ball grid total indicates maximum ball count for package. Lesser quantity may be used.
* Source Ref.: JEDEC Publication 95,
10-0055
MO-205*, MO-225**
Ordering Information
ICS97ULP877AHLF-T
Example:
ICS XXXX y H LF- T
Designation for tape and reel packaging
Annealed Lead Free (Optional)
Package Type
H = BGA
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
0981C—04/05/05
13
ICS97ULP877A
Seating Plane
A1
(Ref.)
ND & NE
Even
Index Area
N
(ND - 1) x
(Ref.)
e
L
A3
(Typ.)
e/2
If ND & NE
are Even
1
1
Anvil
Singulation
2
2
or
(NE - 1) x
(Ref.)
e
E
E2
Sawn
Singulation
E2/2
Top View
b
(Ref.)
ND & NE
Odd
e
A
Thermal
Base
D
D2/2
C
D2
0.08
C
THERMALLY ENHANCED, VERY THIN, FINE PITCH
QUAD FLAT / NO LEAD PLASTIC PACKAGE
ALL DIMENSIONS IN MILLIMETERS
40
10
N
ND
SYMBOL
A
MIN.
0.80
0
0.25 Reference
0.18
MAX.
1.00
10
NE
A1
A3
b
0.05
6.00 x 6.00
2.75 / 3.05
2.75 / 3.05
0.30 / 0.50
D x E BASIC
D2 MIN. / MAX.
E2 MIN. / MAX.
L MIN. / MAX.
0.30
0.50 BASIC
e
Source Reference: MLF2™SE
10-0053
Ordering Information
ICS97ULP877AKLF-T
Example:
ICS XXXX y K LF- T
Designation for tape and reel packaging
Annealed Lead Free (Optional)
Package Type
K = MLF
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
7116—03/27/07
14
相关型号：
ICS97ULP877AKLFT
97ULP SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC40, ROHS COMPLIANT, PLASTIC, VFQFN, MLF-40
IDT
ICS97ULP877BH
PLL Based Clock Driver, 97ULP Series, 10 True Output(s), 0 Inverted Output(s), PBGA52, PLASTIC, MO-205, MO-225, FBGA-52
IDT
ICS97ULP877BHLF
PLL Based Clock Driver, 97ULP Series, 10 True Output(s), 0 Inverted Output(s), PBGA52, GREEN, PLASTIC, MO-205, MO-225, FBGA-52
IDT
ICS97ULP877BHLF-T
PLL Based Clock Driver, 97ULP Series, 10 True Output(s), 0 Inverted Output(s), PBGA52, LEAD FREE ANNEALED, MO-205, MO-225, BGA-52
IDT
ICS97ULP877BK
PLL Based Clock Driver, 97ULP Series, 10 True Output(s), 0 Inverted Output(s), PQCC40, PLASTIC, MLF-40
IDT
ICS97ULP877BK-T
PLL Based Clock Driver, 97ULP Series, 10 True Output(s), 0 Inverted Output(s), PQCC40, PLASTIC, MLF-40
IDT
ICS97ULP877BKLF
PLL Based Clock Driver, 97ULP Series, 10 True Output(s), 0 Inverted Output(s), PQCC40, GREEN, PLASTIC, MLF-40
IDT
ICS97ULP877BKLF-T
PLL Based Clock Driver, 97ULP Series, 10 True Output(s), 0 Inverted Output(s), PQCC40, LEAD FREE ANNEALED, PLASTIC, MLF-40
IDT
ICS97ULP877YH-T
PLL Based Clock Driver, 97ULP Series, 10 True Output(s), 0 Inverted Output(s), PBGA52, PLASTIC, MO-205, MO-225, FBGA-52
IDT
ICS97ULP877YHLF-T
PLL Based Clock Driver, 97ULP Series, 10 True Output(s), 0 Inverted Output(s), PBGA52, LEAD FREE, PLASTIC, MO-205, MO-225, FBGA-52
IDT
©2020 ICPDF网 联系我们和版权申明