ICS9DB306BLT [ICSI]
PCI Express, Jitter Attenuator; PCI Express的，抖动衰减器
| 型号： | ICS9DB306BLT |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | PCI Express, Jitter Attenuator |
| 文件： | 总16页 (文件大小：273K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS9DB306
PCI EXPRESS,
JITTER ATTENUATOR
Integrated
Circuit
Systems, Inc.
GENERAL DESCRIPTION
Features
The ICS9DB306 is a high performance 1-to-6
• Six differential LVPECL output pairs
• 1 differential clock input
ICS
Differential-to LVPECL Jitter Attenuator designed
for use in PCI Express™ systems. In some PCI
Express™ systems, such as those found in desktop
PCs, the PCI Express™ clocks are generated from
a low bandwidth, high phase noise PLL frequency
HiPerClockS™
• CLK and nCLK supports the following input types:
LVPECL, LVDS, LVHSTL, SSTL, HCSL
synthesizer. In these systems, a zero delay buffer may be
required to attenuate high frequency random and deterministic
jitter components from the PLL synthesizer and from the system
board. The ICS9DB306 has 2 PLL bandwidth modes. In low
bandwidth mode, the PLL loop BW is about 500kHz and this
setting will attenuate much of the jitter from the reference clock
input while being high enough to pass a triangular input spread
spectrum profile. There is also a high bandwidth mode which
• Maximum output frequency: 140MHz
• Output skew: 135ps (maximum)
• Cycle-to-Cycle jitter: 25ps (maximum)
• RMS phase jitter @ 100MHz, (1.5MHz - 22MHz):
3ps (typical)
sets the PLL bandwidth at 1MHz which will pass more spread • 3.3V operating supply
spectrum modulation.
• 0°C to 70°C ambient operating temperature
For serdes which have x30 reference multipliers instead of x25
multipliers, 5 of the 6 PCI Express™ outputs (PCIEX1:5) can be
set for 125MHz instead of 100MHz by configuring the appropri-
ate frequency select pins (FS0:1). Output PCIEX0 will always
run at the reference clock frequency (usually 100MHz) in desk-
top PC PCI Express™ Applications.
• Lead-Free package fully RoHS compliant
• Industrial temperature information available upon request
BLOCK DIAGRAM
PIN ASSIGNMENT
1 Disabled
nOE0
1
2
3
4
28
27
26
25
VEE
PCIEXT1
PCIEXC1
PCIEXT2
PCIEXC2
VCC
VCC
0 Enabled
PCIEXC0
PCIEXT0
FS0
nCLK
CLK
PLL_BW
VCCA
VEE
0
1
PCIEXT0
nPCIEXC0
÷5
24
23
22
21
20
5
6
7
8
Buffer
nOE0
nOE1
VCC
9
CLK
Loop
PCIEXT1
nPCIEXC1
0
1
Phase
Detector
BYPASS
FS1
0 ÷4
PCIEXC3
10
11
12
13
19
18
17
16
15
VCO
nCLK
Filter
PCIEXT3
PCIEXC4
PCIEXT4
VEE
1 ÷5
PCIEXT2
nPCIEXC2
PCIEXT5
PCIEXC5
VCC
14
FS0
÷5
ICS9DB306
28-LeadTSSOP, 173-MIL
4.4mm x 9.7mm x 0.92mm
body package
Internal Feedback
PCIEXT3
nPCIEXC3
0
1
0 ÷5
1 ÷4
L Package
TopView
PCIEXT4
nPCIEXC4
ICS9DB306
28-Lead, 209-MIL SSOP
5.3mm x 10.2mm x 1.75mm
body package
PCIEXT5
nPCIEXC5
FS1
F Package
TopView
BYPASS
nOE1
1 Disabled
0 Enabled
9DB306BL
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REV. A APRIL 7, 2005
1
ICS9DB306
PCI EXPRESS,
JITTER ATTENUATOR
Integrated
Circuit
Systems, Inc.
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1, 14, 20
VEE
Power
Negative supply pins.
PCIEXT1,
PCIEXC1
PCIEXT2,
PCIEXC2
2, 3
Output
Differential output pairs. LVPECL interface levels.
4, 5
Output
Power
Differential output pairs. LVPECL interface levels.
Core supply pins.
6, 9, 15, 28
VCC
Output enable. When HIGH, forces true outputs (PCIEXTx) to go
Pulldown LOW and the inverted outputs (PCIEXCx) to go HIGH. When LOW,
outputs are enabled. LVCMOS/LVTTL interface levels.
7, 8
nOE0, nOE1
Input
PCIEXC3,
PCIEXT3
PCIEXC4,
PCIEXT4
PCIEXC5,
PCIEXT5
10, 11
12, 13
Output
Output
Output
Differential output pairs. LVPECL interface levels.
Differential output pairs. LVPECL interface levels.
16, 17
18
Differential output pairs. LVPECL interface levels.
FS1
Pulldown Frequency select pin. LVCMOS/LVTTL interface levels.
Bypass select pin. When HIGH, the PLL is in bypass mode, and the
Pulldown
19
BYPASS
Input
device can function as a 1:6 buffer. LVCMOS/LVTTL interface levels.
21
22
23
VCCA
PLL_BW
CLK
Power
Input
Input
Analog supply pin. Requires 24Ω series resistor.
Pullup
Selects PLL Bandwidth input. LVCMOS/LVTTL interface levels.
Pulldown Non-inverting differential clock input.
Pullup/
24
25
nCLK
Input
Input
Inverting differential clock input. VCC/2 default when left floating.
Pulldown
FS0
Pullup Frequency select pin. LVCMOS/LVTTL interface levels.
PCIEXT0,
PCIEXC0
26, 27
Output
Differential output pairs. LVPECL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum Typical
Maximum Units
Input Capacitance
Input Pullup Resistor
4
pF
KΩ
KΩ
RPULLUP
51
51
RPULLDOWN Input Pulldown Resistor
TABLE 3A. RATIO OF OUTPUT FREQUENCY TO
INPUT FREQUENCY FUNCTION TABLE, FS0
TABLE 3B. RATIO OF OUTPUT FREQUENCY TO
INPUT FREQUENCY FUNCTION TABLE, FS1
Inputs
Outputs
PCIEX1
5/4
Inputs
Outputs
PCIEX4
1
FS0
0
PCIEX0
PCIEX2
FS1
0
PCIEX3
PCIEX5
1
1
5/4
1
1
1
1
1
1
5/4
5/4
5/4
TABLE 3E. PLL BANDWIDTH
FUNCTION TABLE
TABLE 3F. PLL MODE
FUNCTION TABLE
Inputs
TABLE 3C. OUTPUT ENABLE
FUNCTION TABLE, nOE0
TABLE 3D. OUTPUT ENABLE
FUNCTION TABLE, nOE1
Inputs
Inputs
Outputs
PCIEX0:2
Enabled
Inputs
Outputs
PCIEX3:5
Enabled
Bandwidth
PLL_BW
PLL Mode
BYPASS
nOE0
nOE1
0
1
500kHz
1MHz
1
0
Disabled
Enabled
0
1
0
1
Disabled
Disabled
9DB306BL
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REV. A APRIL 7, 2005
2
ICS9DB306
PCI EXPRESS,
JITTER ATTENUATOR
Integrated
Circuit
Systems, Inc.
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
CC
Inputs, V
-0.5V to VCC + 0.5V
I
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
PackageThermal Impedance, θ
49.8°C/W (0 lfpm)
-65°C to 150°C
JA
StorageTemperature, T
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VCC
VCCA
ICC
Core Supply Voltage
3.135
3.135
3.3
3.3
3.465
3.465
135
V
Analog Supply Voltage
Power Supply Current
Analog Supply Current
V
mA
mA
ICCA
25
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VIH
VIL
Input High Voltage
2
VCC + 0.3
0.8
mV
mV
Input Low Voltage
-0.3
nOE0, nOE1, FS1,
BYPASS
V
CC = VIN = 3.465V
150
5
µA
µA
µA
µA
IIH
Input High Current
FS0, PLL_BW
nOE0, nOE1, FS1,
BYPASS
V
CC = 3.465V, VIN = 0V
-5
IIL
Input Low Current
FS0, PLL_BW
-150
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VCC = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
VCC = VIN = 3.465V
VCC = 3.465V, VIN = 0V
Minimum Typical Maximum Units
IIH
Input High Current CLK, nCLK
Input Low Current CLK, nCLK
150
150
µA
µA
V
IIL
VPP
VCMR
Peak-to-Peak Input Voltage
0.15
1.3
Common Mode Input Voltage; NOTE 1, 2
VEE + 0.5
VCC - 0.85
V
NOTE 1: Common mode voltage is defined as VIH.
NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK is VCC + 0.3V.
9DB306BL
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REV. A APRIL 7, 2005
3
ICS9DB306
PCI EXPRESS,
JITTER ATTENUATOR
Integrated
Circuit
Systems, Inc.
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical
Maximum Units
VOH
Output High Voltage; NOTE 1
VCC - 1.4
VCC - 2.0
0.6
VCC - 0.9
VCC - 1.7
1.0
V
V
V
VOL
Output Low Voltage; NOTE 1
VSWING
Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.
TABLE 5. AC CHARACTERISTICS, VCC = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter Test Conditions
Minimum Typical Maximum Units
fMAX
Output Frequency
140
135
25
MHz
ps
tsk(o)
tjit(cc)
Output Skew; NOTE 1, 2
55
3
Cycle-to-Cycle Jitter, NOTE 2
ps
RMS Phase Jitter (Random);
NOTE 3
Integration Range:
1.5MHz - 22MHz
tjit(Ø)
ps
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20ꢀ to 80ꢀ
200
48
700
52
ps
ꢀ
NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Please refer to the Phase Noise Plot following this section.
9DB306BL
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REV. A APRIL 7, 2005
4
ICS9DB306
PCI EXPRESS,
JITTER ATTENUATOR
Integrated
Circuit
Systems, Inc.
TYPICAL PHASE NOISE AT 100MHZ
0
-10
-20
-30
-40
-50
-60
-70
PCI Express™ Filter
100MHz
RMS Phase Jitter (Random)
1.5MHz to 22MHz = 3ps (typical)
-80
-90
-100
-110
-120
Raw Phase Noise Data
-130
-140
-150
-160
-170
-180
Phase Noise Result by adding
PCI Express™ Filter to raw data
-190
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
The illustrated phase noise plot was taken using a low phase test. Due to the tracking ability of a PLL, it will track the input
noise signal generator, the noise floor of the signal generator is signal up to its loop bandwidth.Therefore, if the input phase noise
less than that of the device under test.
is greater than that of the VCO, it will increase the output phase
noise performance of the device. It is recommended that the
Using this configuration allows one to see the true spectral pu- phase noise performance of the input is verified in order to
rity or phase noise performance of the PLL in the device under achieve the above phase noise performance.
9DB306BL
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REV. A APRIL 7, 2005
5
ICS9DB306
PCI EXPRESS,
JITTER ATTENUATOR
Integrated
Circuit
Systems, Inc.
PARAMETER MEASUREMENT INFORMATION
2V
VCC
SCOPE
VCC
Qx
nCLK
CLK
VPP
VCMR
Cross Points
LVPECL
nQx
VEE
VEE
-1.3V 0.165V
3.3V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
PCIEXC0:5
PCIEXC0:5x
PCIEXT0:5x
PCIEXT0:5
➤
➤
tcycle n
tcycle n+1
➤
➤
PCIEXC0:5y
tjit(cc) = tcycle n –tcycle n+1
1000 Cycles
PCIEXT0:5y
tsk(o)
OUTPUT SKEW
CYCLE-TO-CYCLE JITTER
PCIEXC0:5
PCIEXT0:5
80ꢀ
tF
80ꢀ
VSWING
20ꢀ
Pulse Width
Clock
20ꢀ
tPERIOD
Outputs
tR
tPW
odc =
tPERIOD
OUTPUT RISE/FALL TIME
OUTPUT DUTY CYCLE/PULSE WIDTH PERIOD
9DB306BL
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REV. A APRIL 7, 2005
6
ICS9DB306
PCI EXPRESS,
JITTER ATTENUATOR
Integrated
Circuit
Systems, Inc.
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise.The ICS9DB306 provides separate
power supplies to isolate any high switching noise from the out-
puts to the internal PLL.VCC andVCCA should be individually con-
nected to the power supply plane through vias, and bypass ca-
pacitors should be used for each pin.To achieve optimum jitter
performance, power supply isolation is required. Figure 1 illus-
trates how a 24Ω resistor along with a 10μF and a .01μF by-
pass capacitor should be connected to each VCCA pin.
3.3V
VCC
.01μF
24Ω
VCCA
.01μF
10μF
FIGURE 1. POWER SUPPLY FILTERING
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 2 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VCC/2 is
generated by the bias resistors R1, R2 and C1.This bias circuit
should be located as close as possible to the input pin.The ratio
of R1 and R2 might need to be adjusted to position theV_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V andVCC = 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
VCC
R1
1K
Single Ended Clock Input
V_REF
CLKx
nCLKx
C1
0.1u
R2
1K
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
9DB306BL
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REV. A APRIL 7, 2005
7
ICS9DB306
PCI EXPRESS,
JITTER ATTENUATOR
Integrated
Circuit
Systems, Inc.
TERMINATION FOR LVPECL OUTPUTS
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs.The two different layouts mentioned
are recommended only as guidelines.
50Ω transmission lines. Matched impedance techniques should
be used to maximize operating frequency and minimize signal
distortion. Figures 3A and 3B show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs.Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
3.3V
Z
o = 50Ω
125Ω
125Ω
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
VCC - 2V
1
RTT =
Zo
RTT
((VOH + VOL) / (VCC – 2)) – 2
84Ω
84Ω
FIGURE 3A. LVPECL OUTPUT TERMINATION
FIGURE 3B. LVPECL OUTPUT TERMINATION
9DB306BL
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REV. A APRIL 7, 2005
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ICS9DB306
PCI EXPRESS,
JITTER ATTENUATOR
Integrated
Circuit
Systems, Inc.
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL here are examples only. Please consult with the vendor of the
and other differential signals.BothVSWING and VOH must meet the driver component to confirm the driver termination requirements.
VPP and VCMR input requirements. Figures 4A to 4D show inter- For example in Figure 4A, the input termination applies for ICS
face examples for the HiPerClockS CLK/nCLK input driven by HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
the most common driver types.The input interfaces suggested from another vendor, use their termination recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50 Ohm
CLK
Zo = 50 Ohm
CLK
Zo = 50 Ohm
nCLK
Zo = 50 Ohm
HiPerClockS
Input
LVPECL
nCLK
HiPerClockS
Input
LVHSTL
R1
50
R2
50
ICS
HiPerClockS
R1
50
R2
50
LVHSTL Driver
R3
50
FIGURE 4A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
ICS HIPERCLOCKS LVHSTL DRIVER
FIGURE 4B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
3.3V
3.3V
3.3V
3.3V
Zo = 50 Ohm
3.3V
R3
125
R4
125
LVDS_Driver
Zo = 50 Ohm
Zo = 50 Ohm
CLK
CLK
R1
100
nCLK
Receiv er
nCLK
HiPerClockS
Input
Zo = 50 Ohm
LVPECL
R1
84
R2
84
FIGURE 4C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 4D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
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REV. A APRIL 7, 2005
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ICS9DB306
PCI EXPRESS,
JITTER ATTENUATOR
Integrated
Circuit
Systems, Inc.
SCHEMATIC EXAMPLE
Figure 5 shows an example of ICS9DB306 application
schematic.In this example, the device is operated atVCC = 3.3V.
LVPECL output drivers, one of terminations approaches is shown
in this schematic. For additional termination approaches, please
The decoupling capacitor should be located as close as pos- refer to the LVPECLTermination Application Note.
sible to the power pin.The input is driven by a HCSL driver. For
Zo = 50
VCC
+
R11
1K
VCC
Zo = 50
-
R7
24
VCCA
LVPECL
U1
ICS9DB306
VCC
VCC
R4
50
R5
50
C16
C11
10uF
0.1uF
15
16
17
18
19
20
21
22
23
24
25
26
27
28
14
VCC
VEE
PCIEXT4
PCIEXC4
PCIEXT3
PCIEXC3
VCC
13
12
11
10
9
PCIEXC5
PCIEXT5
FS1
BYPASS
VEE
VCCA
PLL_BW
CLK
nCLK
FS0
PCIEXT0
PCIEXC0
VCC
R6
50
VCC
8
7
6
5
4
3
nOE1
nOE0
VCC
R12 33
Zo = 50
Zo = 50
PCIEXC2
PCIEXT2
PCIEXC1
PCIEXT1
VEE
R8
1K
R9
1K
2
1
HCSL
R13 33
R1
50
R2
50
R10
1K
Zo = 50
Zo = 50
+
-
LVPECL
(U1-15)
(U1-28)
(U1-6)
(U1-9)
VCC
R14 R15
50 50
C1
0.1uF
C2
0.1uF
C3
0.1uF
C3
0.1uF
VCC=3.3V
R16
50
FIGURE 5. EXAMPLE OF ICS9DB306 SCHEMATIC
9DB306BL
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REV. A APRIL 7, 2005
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ICS9DB306
PCI EXPRESS,
JITTER ATTENUATOR
Integrated
Circuit
Systems, Inc.
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS9DB306.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS9DB306 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5ꢀ = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 135mA = 467.8mW
Power (outputs)MAX = 30mW/Loaded Output pair
If all outputs are loaded, the total power is 6 * 30mW = 180mW
Total Power_MAX (3.465V, with all outputs switching) = 467.8mW + 180mW = 647.8mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device.The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = JunctionTemperature
θJA = Junction-to-AmbientThermal Resistance
Pd_total =Total Device Power Dissipation (example calculation is in section 1 above)
TA = AmbientTemperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 43.9°C/W perTable 6 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.648W * 43.9°C/W = 98.4°C. This is well below the limit of 125°C.
This calculation is only an example.Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE θJA FOR 28-PIN TSSOP, FORCED CONVECTION
θJA byVelocity (Linear Feet per Minute)
0
200
68.7°C/W
43.9°C/W
500
60.5°C/W
41.2°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
82.9°C/W
49.8°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
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REV. A APRIL 7, 2005
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ICS9DB306
PCI EXPRESS,
JITTER ATTENUATOR
Integrated
Circuit
Systems, Inc.
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 5.
VCCO
Q1
VOUT
R L
50
VCCO - 2V
FIGURE 5. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage ofV - 2V.
CCO
•
•
For logic high, VOUT = V
= V
– 0.9V
OH_MAX
CCO_MAX
)
= 0.9V
OH_MAX
(V
- V
CCO_MAX
For logic low, VOUT = V
= V
– 1.7V
OL_MAX
CCO_MAX
)
= 1.7V
OL_MAX
(V
- V
CCO_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
))
Pd_H = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
/R ] * (V
- V
) =
OH_MAX
CCO_MAX
CCO_MAX
OH_MAX
CCO_MAX
OH_MAX
CCO_MAX
OH_MAX
L
L
[(2V - 0.9V)/50Ω] * 0.9V = 19.8mW
))
Pd_L = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
/R ] * (V
- V
) =
OL_MAX
CCO_MAX
CCO_MAX
OL_MAX
CCO_MAX
OL_MAX
CCO_MAX
OL_MAX
L
L
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
9DB306BL
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REV. A APRIL 7, 2005
12
ICS9DB306
PCI EXPRESS,
JITTER ATTENUATOR
Integrated
Circuit
Systems, Inc.
RELIABILITY INFORMATION
TABLE 7A. θJAVS. AIR FLOW TABLE FOR 28 LEAD TSSOP PACKAGE
θJA byVelocity (Linear Feet per Minute)
0
200
68.7°C/W
43.9°C/W
500
60.5°C/W
41.2°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
82.9°C/W
49.8°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TABLE 7B. θJAVS. AIR FLOW TABLE FOR 28 LEAD SSOP PACKAGE
θJA byVelocity (Linear Feet per Minute)
0
200
500
Multi-Layer PCB, JEDEC Standard Test Boards
49°C/W
36°C/W
30°C/W
TRANSISTOR COUNT
The transistor count for ICS9DB306 is: 2190
9DB306BL
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REV. A APRIL 7, 2005
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ICS9DB306
PCI EXPRESS,
JITTER ATTENUATOR
Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE - L SUFFIX FOR 28 LEAD TSSOP
PACKAGE OUTLINE - F SUFFIX FOR 28 LEAD SSOP
TABLE 8A. PACKAGE DIMENSIONS
TABLE 8B. PACKAGE DIMENSIONS
Millimeters
Millimeters
SYMBOL
SYMBOL
Minimum
Maximum
Minimum
Maximum
N
A
28
N
A
28
2.00
--
1.20
0.15
1.05
0.30
0.20
9.80
A1
A2
b
0.05
1.65
0.22
0.09
9.90
7.40
5.00
A1
A2
b
0.05
0.80
0.19
0.09
9.60
1.85
0.38
0.25
10.50
8.20
5.60
c
c
D
D
E
E
6.40 BASIC
0.65 BASIC
E1
e
E1
e
4.30
4.50
0.65 BASIC
L
0.55
0°
0.95
8°
L
0.45
0°
0.75
8°
α
α
Reference Document: JEDEC Publication 95, MO-150
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
9DB306BL
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REV. A APRIL 7, 2005
14
ICS9DB306
PCI EXPRESS,
JITTER ATTENUATOR
Integrated
Circuit
Systems, Inc.
TABLE 9. ORDERING INFORMATION
Part/Order Number
Marking
Package
Count
Temperature
0°C to 70°C
0°C to 70°C
0°C to 70°C
ICS9DB306BL
ICS9DB306BLT
ICS9DB306BLLF
ICS9DB306BL
ICS9DB306BL
ICS9DB306BLLF
28 Lead TSSOP
48 per Tube
1000
28 Lead TSSOP on Tape and Reel
28 Lead "Lead-Free" TSSOP
48 per Tube
28 Lead "Lead-Free" TSSOP on
Tape and Reel
ICS9DB306BLLFT
ICS9DB306BLLF
1000
0°C to 70°C
ICS9DB306BF
ICS9DB306BFT
ICS9DB306BF
ICS9DB306BF
28 Lead SSOP
46 per Tube
1000
0°C to 70°C
0°C to 70°C
28 Lead SSOP on Tape and Reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS
compliant.
The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
9DB306BL
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REV. A APRIL 7, 2005
15
ICS9DB306
PCI EXPRESS,
JITTER ATTENUATOR
Integrated
Circuit
Systems, Inc.
REVISION HISTORY SHEET
Description of Change
Added PLL Mode Function Table.
Rev
Table
3F
Page
Date
A
2
4/7/05
9DB306BL
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REV. A APRIL 7, 2005
16
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