ICS9DB401BFLFT [IDT]
PLL Based Clock Driver, 9DB Series, 4 True Output(s), 0 Inverted Output(s), PDSO28, 0.209 INCH, GREEN, MO-150,SSOP-28;
| 型号： | ICS9DB401BFLFT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | PLL Based Clock Driver, 9DB Series, 4 True Output(s), 0 Inverted Output(s), PDSO28, 0.209 INCH, GREEN, MO-150,SSOP-28 光电二极管 |
| 文件： | 总20页 (文件大小：277K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated
Circuit
ICS9DB401
Systems, Inc.
Four Output Differential Buffer for PCI Express
Recommended Application:
Pin Configurations
DB800 Version 2.0 Yellow Cover part with PCI Express
support with extended bypass mode frequency range.
VDD 1
SRC_IN 2
SRC_IN# 3
28 VDDA
27 GNDA
26 IREF
Output Features:
4
5
6
7
25 OE_INV
24 VDD
GND
VDD
DIF_1
DIF_1#
•
•
•
4 - 0.7V current-mode differential output pairs
Supports zero delay buffer mode and fanout mode
Bandwidth programming available
23
22
DIF_6
DIF_6#
OE_1 8
21 OE_6
Key Specifications:
9
20
19
18 VDD
17 HIGH_BW#
16 SRC_STOP#
15 PD#
DIF_2
DIF_2#
VDD
BYPASS#/PLL
SCLK
DIF_5
DIF_5#
•
•
•
Outputs cycle-cycle jitter: < 50ps
Outputs skew: < 50ps
Extended frequency range in bypass mode:
Revision B: up to 333.33MHz
Revision C: up to 400MHz
10
11
12
13
14
SDATA
Features/Benefits:
•
OE_INV = 0
Spread spectrum modulation tolerant, 0 to -0.5% down
spread and +/- 0.25% center spread
•
Supports undriven differential outputs in PD# and
SRC_STOP# modes for power management.
VDD 1
SRC_IN 2
SRC_IN# 3
28 VDDA
27 GNDA
26 IREF
4
5
6
7
25 OE_INV
24 VDD
GND
VDD
DIF_1
DIF_1#
23
22
DIF_6
DIF_6#
OE1# 8
21 OE6#
9
20
19
18 VDD
17 HIGH_BW#
16 SRC_STOP
15 PD
DIF_2
DIF_2#
VDD
BYPASS#/PLL
SCLK
DIF_5
DIF_5#
10
11
12
13
14
SDATA
OE_INV = 1
28-pin SSOP & TSSOP
1014B—09/07/06
Integrated
Circuit
ICS9DB401
Systems, Inc.
Pin Decription When OE_INV = 0
PIN #
PIN NAME
VDD
SRC_IN
SRC_IN#
GND
VDD
DIF_1
DIF_1#
PIN TYPE
DESCRIPTION
1
2
3
4
5
6
7
PWR
IN
IN
PWR
PWR
OUT
OUT
Power supply, nominal 3.3V
0.7 V Differential SRC TRUE input
0.7 V Differential SRC COMPLEMENTARY input
Ground pin.
Power supply, nominal 3.3V
0.7V differential true clock output
0.7V differential complement clock output
Active high input for enabling output 1.
0 = tri-state outputs, 1= enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Power supply, nominal 3.3V
8
OE_1
IN
9
10
11
DIF_2
DIF_2#
VDD
OUT
OUT
PWR
Input to select Bypass(fan-out) or PLL (ZDB) mode
0 = Bypass mode, 1= PLL mode
Clock pin of SMBus circuitry, 5V tolerant.
Data pin for SMBus circuitry, 5V tolerant.
12
BYPASS#/PLL
IN
13
14
SCLK
SDATA
IN
I/O
Asynchronous active low input pin used to power down the device. The
internal clocks are disabled and the VCO and the crystal are stopped.
15
PD#
IN
16
17
SRC_STOP#
HIGH_BW#
IN
IN
Active low input to stop SRC outputs.
3.3V input for selecting PLL Band Width
0 = High, 1= Low
18
19
20
VDD
DIF_5#
DIF_5
PWR
OUT
OUT
Power supply, nominal 3.3V
0.7V differential complement clock output
0.7V differential true clock output
Active high input for enabling output 6.
0 = tri-state outputs, 1= enable outputs
0.7V differential complement clock output
0.7V differential true clock output
21
OE_6
IN
22
23
24
DIF_6#
DIF_6
VDD
OUT
OUT
PWR
Power supply, nominal 3.3V
This latched input selects the polarity of the OE pins.
0 = OE pins active high, 1 = OE pins active low (OE#)
This pin establishes the reference current for the differential current-
mode output pairs. This pin requires a fixed precision resistor tied to
ground in order to establish the appropriate current. 475 ohms is the
standard value.
25
OE_INV
IN
26
IREF
OUT
27
28
GNDA
VDDA
PWR
PWR
Ground pin for the PLL core.
3.3V power for the PLL core.
1014B—09/07/06
2
Integrated
Circuit
ICS9DB401
Systems, Inc.
Pin Decription When OE_INV = 1
PIN #
PIN NAME
VDD
SRC_IN
SRC_IN#
GND
VDD
DIF_1
DIF_1#
PIN TYPE
DESCRIPTION
1
2
3
4
5
6
7
PWR
IN
IN
PWR
PWR
OUT
OUT
Power supply, nominal 3.3V
0.7 V Differential SRC TRUE input
0.7 V Differential SRC COMPLEMENTARY input
Ground pin.
Power supply, nominal 3.3V
0.7V differential true clock output
0.7V differential complement clock output
Active low input for enabling DIF pair 1.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Power supply, nominal 3.3V
8
OE1#
IN
9
10
11
DIF_2
DIF_2#
VDD
OUT
OUT
PWR
Input to select Bypass(fan-out) or PLL (ZDB) mode
0 = Bypass mode, 1= PLL mode
12
BYPASS#/PLL
IN
13
14
SCLK
SDATA
IN
I/O
Clock pin of SMBus circuitry, 5V tolerant.
Data pin for SMBus circuitry, 5V tolerant.
Asynchronous active high input pin used to power down the device. The
internal clocks are disabled and the VCO is stopped.
Active high input to stop SRC outputs.
3.3V input for selecting PLL Band Width
0 = High, 1= Low
15
16
17
PD
IN
IN
IN
SRC_STOP
HIGH_BW#
18
19
20
VDD
DIF_5#
DIF_5
PWR
OUT
OUT
Power supply, nominal 3.3V
0.7V differential complement clock output
0.7V differential true clock output
Active low input for enabling DIF pair 6.
1 = tri-state outputs, 0 = enable outputs
0.7V differential complement clock output
0.7V differential true clock output
21
OE6#
IN
22
23
24
DIF_6#
DIF_6
VDD
OUT
OUT
PWR
Power supply, nominal 3.3V
This latched input selects the polarity of the OE pins.
0 = OE pins active high, 1 = OE pins active low (OE#)
This pin establishes the reference current for the differential current-
mode output pairs. This pin requires a fixed precision resistor tied to
ground in order to establish the appropriate current. 475 ohms is the
standard value.
25
OE_INV
IN
26
IREF
OUT
27
28
GNDA
VDDA
PWR
PWR
Ground pin for the PLL core.
3.3V power for the PLL core.
1014B—09/07/06
3
Integrated
Circuit
ICS9DB401
Systems, Inc.
General Description
The ICS9DB401 follows the Intel DB400 Differential Buffer Specification v2.0. This buffer provides four PCI-Express SRC
clocks. The ICS9DB401 is driven by a differential input pair from a CK409/CK410/CK410M main clock generator, such as the
ICS952601, ICS954101 or ICS954201. It provides ouputs meeting tight cycle-to-cycle jitter (50ps) and output-to-output skew
(50ps) requirements.
Block Diagram
4
OE(3:0)
SPREAD
SRC_IN
COMPATIBLE
PLL
SRC_IN#
4
M
U
X
STOP
LOGIC
DIF(3:0))
PD
BYPASS#/PLL
SDATA
CONTROL
LOGIC
SCLK
IREF
Note: Polarities shown for OE_INV = 0.
Power Groups
Pin Number
Description
VDD
GND
1
5,11,18, 24
N/A
4
4
27
27
SRC_IN/SRC_IN#
DIF(1,2,5,6)
IREF
28
Analog VDD & GND for PLL core
1014B—09/07/06
4
Integrated
Circuit
ICS9DB401
Systems, Inc.
Absolute Max
Symbol
VDD_A
VDD_In
VIL
Parameter
Min
Max
4.6
4.6
Units
3.3V Core Supply Voltage
3.3V Logic Supply Voltage
Input Low Voltage
V
V
V
GND-0.5
VIH
Input High Voltage
VDD+0.5V
V
Ts
Tambient
Tcase
Storage Temperature
Ambient Operating Temp
Case Temperature
-65
0
150
70
115
°C
°C
°C
Input ESD protection
human body model
ESD prot
2000
V
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
SYMBOL
CONDITIONS
MIN
TYP
MAX
VDD + 0.3
0.8
UNITS NOTES
VIH
VIL
IIH
3.3 V +/-5%
3.3 V +/-5%
VIN = VDD
2
GND - 0.3
-5
V
V
uA
5
VIN = 0 V; Inputs with no pull-up
resistors
IIL1
-5
uA
Input Low Current
VIN = 0 V; Inputs with pull-up
resistors
IIL2
-200
uA
IDD3.3PLL
IDD3.3ByPass
175
160
200
175
40
4
200
mA
mA
mA
mA
MHz
Full Active, CL = Full load;
Operating Supply Current
all diff pairs driven
all differential pairs tri-stated
PLL Mode
IDD3.3PD
FiPLL
Powerdown Current
Input Frequency
Input Frequency
50
0
Bypass Mode (Revision B/REV
FiBypass
333.33
400
MHz
MHz
ID = 1H)
Bypass Mode (Revision C/REV
ID = 2H)
FiBypass
Input Frequency
Pin Inductance1
0
Lpin
CIN
COUT
7
4
4
nH
pF
pF
1
1
1
Logic Inputs
1.5
Input Capacitance1
Output pin capacitance
PLL Bandwidth when
PLL_BW=0
2.4
0.7
3
1
3.4
1.4
MHz
MHz
1
1
PLL Bandwidth
BW
PLL Bandwidth when
PLL_BW=1
From VDD Power-Up and after
input clock stabilization or de-
assertion of PD# to 1st clock
Clk Stabilization1,2
TSTAB
0.5
10
1
ms
1,2
Modulation Frequency
Tdrive_SRC_STOP#
fMOD
Triangular Modulation
DIF output enable after
SRC_Stop# de-assertion
DIF output enable after
PD# de-assertion
30
33
15
kHz
ns
1
1,3
Tdrive_PD#
Tfall
300
5
us
ns
ns
1,3
1
Fall time of PD# and
SRC_STOP#
Rise time of PD# and
SRC_STOP#
Trise
5
2
1Guaranteed by design and characterization, not 100% tested in production.
2See timing diagrams for timing requirements.
3Time from deassertion until outputs are >200 mV
1014B—09/07/06
5
Integrated
Circuit
ICS9DB401
Systems, Inc.
Electrical Characteristics - DIF 0.7V Current Mode Differential Pair
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2Ω, RP=49.9Ω, ΙREF = 475Ω
PARAMETER
SYMBOL
Zo1
CONDITIONS
MIN
TYP
MAX
850
UNITS NOTES
Current Source Output
Impedance
VO = Vx
3000
Ω
1
Statistical measurement on single
ended signal using oscilloscope
math function.
Voltage High
Voltage Low
VHigh
VLow
660
1,3
1,3
mV
-150
150
Measurement on single ended
signal using absolute value.
Max Voltage
Min Voltage
Crossing Voltage (abs)
Vovs
Vuds
Vcross(abs)
1150
1
1
1
mV
mV
mV
-300
250
550
140
Variation of crossing over all
edges
Crossing Voltage (var)
d-Vcross
1
Long Accuracy
Rise Time
Fall Time
Rise Time Variation
Fall Time Variation
ppm
tr
tf
d-tr
d-tf
see Tperiod min-max values
VOL = 0.175V, VOH = 0.525V
VOH = 0.525V VOL = 0.175V
0
ppm
ps
ps
ps
ps
1,2
1
1
1
1
175
175
700
700
125
125
Measurement from differential
wavefrom
dt3
Duty Cycle
Skew
45
55
50
%
1
1
tsk3
VT = 50%
ps
PLL mode,
Measurement from differential
wavefrom
BYPASS mode as additive jitter
50
50
ps
ps
1
1
tjcyc-cyc
Jitter, Cycle to cycle
1Guaranteed by design and characterization, not 100% tested in production.
2 All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that the input clock
complies with CK409/CK410 accuracy requirements
3IREF = VDD/(3xRR). For RR = 475Ω (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50Ω.
1014B—09/07/06
6
Integrated
Circuit
ICS9DB401
Systems, Inc.
SRC Reference Clock
Common Recommendations for Differential Routing
L1 length, Route as non -coupled 50 ohm trace.
Dimension or Value
Unit
inch
inch
inch
ohm
ohm
Figure
2, 3
2, 3
2, 3
2, 3
2, 3
0.5 max
0.2 max
0.2 max
33
L2 length, Route as non
-coupled 50 ohm trace.
-coupled 50 ohm trace.
L3 length, Route as non
Rs
Rt
49.9
Down Device Differential Routing
Dimension or Value
2 min to 16 max
Unit
inch
Figure
L4 length, Route as coupled
microstrip 100 ohm
2
2
differential trace.
L4 length, Route as coup
differential trace.
led stripline 100 ohm
1.8 min to 14.4 max
inch
Differential Routing to PCI Express Connector
Dimension or Value
0.25 to 14 max
Unit
inch
Figure
L4 length, Route as coupled
differential trace.
microstrip 100 ohm
3
3
L4 length, Rout e as coupled stripline 100 ohm
differential trace.
0.225 min to 12.6
max
inch
L1
L2
L4
L4’
Rs
L1’
L2’
Rs
Rt
Rt
Fig.1
HSCL Output
Buffer
PCI Ex
REF_CLK
Test Load
L3’
L3
L1
L2
L4
Rs
Rs
L4’
L1’
L2’
Fig.2
Rt
Rt
HSCL Output
Buffer
PCI Ex Board
Down Device
L3’
L3
REF_CLK Input
L1
L2
L4
L4’
Rs
Rs
L1’
L2’
Rt
Rt
Fig.3
HSCL Output
Buffer
PCI Ex
Add In Board
REF_CLK Input
L3’
L3
1014B—09/07/06
7
Integrated
Circuit
ICS9DB401
Systems, Inc.
General SMBus serial interface information for the ICS9DB401
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address DC(H)
• ICS clock will acknowledge
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the write address DC(H)
• ICS clock will acknowledge
• Controller (host) sends the begining byte location = N
• ICS clock will acknowledge
• Controller (host) sends the begining byte
location = N
• Controller (host) sends the data byte count = X
• ICS clock will acknowledge
• Controller (host) starts sending Byte N through
Byte N + X -1
• ICS clock will acknowledge
• Controller (host) will send a separate start bit.
• Controller (host) sends the read address DD(H)
• ICS clock will acknowledge
(see Note 2)
• ICS clock will send the data byte count = X
• ICS clock sends Byte N + X -1
• ICS clock will acknowledge each byte one at a time
• ICS clock sends Byte 0 through byte X (if X(H)
was written to byte 8).
• Controller (host) sends a Stop bit
• Controller (host) will need to acknowledge each byte
• Controllor (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
Index Block Read Operation
Index Block Write Operation
Controller (Host)
Controller (Host)
ICS (Slave/Receiver)
ICS (Slave/Receiver)
s t a rT bi t
T
s t arT bit
T
S l ave A ddres s DC
S l ave A dd r e s s D C
( H )
( H )
R
Ri t e
R
R
i
t
e
A CK
A CK
A CK
A CK
A CK
A CK
B
e
g
i
n
n
i
n
g
B
y
t
e
N
B egi nni ng B y t e
Dat a B y t e Count
B egi nni ng B y t e N
N
RT
R D
R
e
p
e
a
t
s
t
a
r
T
S
l
a
v
e
A
d
d
r
e
s
s
D
D
(
H
)
R
e
a
D
A
C
K
Dat a B y t e Count
B egi nni n g B y t e N
A CK
A CK
B
y
t
e
N
- 1
s t oP bi t
A
C
K
P
B
y
t
e
N
-
1
N
P
Not ac k nowl edge
s t oP bi t
1014B—09/07/06
8
Integrated
Circuit
ICS9DB401
Systems, Inc.
SMBus Table: Frequency Select Register, READ/WRITE ADDRESS (DC/DD)
Byte 0
Bit 7
Bit 6
Pin #
Name
PD_Mode
Control Function
PD# drive mode
Type
RW
0
1
Hi-Z
Hi-Z
PWD
0
0
-
-
driven
driven
STOP_Mode SRC_Stop# drive mode RW
Power Down
-
PD_SRC_INV
RW Normal
Invert
0
Bit 5
and SRC Invert
Reserved
Reserved
Select PLL BW
BYPASS#/PLL
-
-
-
-
-
Reserved
Reserved
PLL_BW#
BYPASS#
SRC_DIV#
RW
RW
Reserved
Reserved
X
X
1
1
1
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RW High BW Low BW
RW fan-out
ZDB
1x
SRC Divide by 2 Select RW
x/2
SMBus Table: Output Control Register
Byte 1
Bit 7
Pin #
Name
Reserved
DIF_6
Control Function
Reserved
Output Control
Output Control
Reserved
Type
RW
0
1
PWD
-
Reserved
X
1
1
X
X
1
1
X
22,23
19,20
RW Disable Enable
RW Disable Enable
RW
RW
RW Disable Enable
RW Disable Enable
RW
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DIF_5
-
-
Reserved
Reserved
DIF_2
DIF_1
Reserved
Reserved
Reserved
Reserved
9,10
6,7
-
Output Control
Output Control
Reserved
Reserved
SMBus Table: Output Control Register
Byte 2
Bit 7
Pin #
Name
Reserved
Control Function
Type
RW
0
1
PWD
X
-
Reserved
Reserved
22,23
19,20
DIF_6
DIF_5
Output Control
Output Control
RW Free-run Stoppable
RW Free-run Stoppable
0
0
Bit 6
Bit 5
-
-
Reserved
Reserved
Reserved
Reserved
RW
RW
Reserved
Reserved
X
X
Bit 4
Bit 3
9,10
DIF_2
Output Control
RW Free-run Stoppable
RW Free-run Stoppable
0
Bit 2
6,7
-
DIF_1
Output Control
Reserved
0
Bit 1
Bit 0
Reserved
RW
Reserved
X
1014B—09/07/06
9
Integrated
Circuit
ICS9DB401
Systems, Inc.
SMBus Table: Output Control Register
Byte 3
Bit 7
Pin #
Name
Control Function
Reserved
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
PWD
Reserved
X
X
X
X
X
X
X
X
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SMBus Table: Vendor & Revision ID Register
Byte 4
Bit 7
Pin #
Name
RID3
RID2
RID1
RID0
VID3
VID2
VID1
VID0
Control Function
Type
R
R
R
R
R
R
R
R
0
1
-
-
-
-
-
-
-
-
PWD
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
X
X
X
X
0
0
0
1
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
REVISION ID
VENDOR ID
SMBus Table: DEVICE ID
Byte 5 Pin # Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Control Function
Device ID 7 (MSB)
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
PWD
-
-
-
-
-
-
-
-
Reserved
0
1
0
0
0
0
0
1
Device ID 6
Device ID 5
Device ID 4
Device ID 3
Device ID 2
Device ID 1
Device ID 0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SMBus Table: Byte Count Register
Control
Function
Byte 6
Pin #
Name
Type
0
1
PWD
-
-
-
-
-
-
-
-
BC7
BC6
BC5
BC4
BC3
BC2
BC1
BC0
RW
RW
RW
RW
RW
RW
RW
RW
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
0
0
0
0
1
1
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Writing to this register
configures how many
bytes will be read back.
1014B—09/07/06
10
Integrated
Circuit
ICS9DB401
Systems, Inc.
PD#
The PD# pin cleanly shuts off all clocks and places the device into a power saving mode. PD# must be asserted before
shutting off the input clock or power to insure an orderly shutdown. PD is asynchronous active-low input for both powering
down the device and powering up the device. When PD# is asserted, all clocks will be driven high, or tri-stated (depending
on the PD# drive mode and Output control bits) before the PLL is shut down.
PD# Assertion
When PD# is sampled low by two consecutive rising edges of DIF#, all DIF outputs must be held High, or tri-stated (depending
on the PD# drive mode and Output control bits) on the next High-Low transition of the DIF# outputs. When the PD# drive mode
bit is set to ‘0’, all clock outputs will be held with DIF driven High with 2 x IREF and DIF# tri-stated. If the PD# drive mode bit is
set to ‘1’, both DIF and DIF# are tri-stated.
PWRDWN#
DIF
DIF#
PD# De-assertion
Power-up latency is less than 1 ms. This is the time from de-assertion of the PD# pin, or VDD reaching 3.3V, or the time from
valid SRC_IN clocks until the time that stable clocks are output from the device (PLL Locked). If the PD# drive mode bit is set
to ‘1’, all the DIF outputs must driven to a voltage of >200 mV within 300 ms of PD# de-assertion.
Tstable
<1mS
PWRDWN#
DIF
DIF#
Tdrive_PwrDwn#
<300uS, >200mV
1014B—09/07/06
11
Integrated
Circuit
ICS9DB401
Systems, Inc.
N
o
t
e
:
P
o
l
a
r
i
t
i
e
s
i
n
t
i
m
i
n
g
d
i
a
g
r
a
m
s
a
r
e
s
h
o
w
n
O
E
I
N
V
0
.
T
h
e
y
a
r
e
s
i
m
i
l
a
r
t
o
O
E
I
N
V
1 .
SRC_STOP#
The SRC_STOP# signal is an active-low asynchronous input that cleanly stops and starts the DIF outputs. A valid clock must
be present on SRC_IN for this input to work properly. The SRC_STOP# signal is de-bounced and must remain stable for two
consecutive rising edges of DIF# to be recognized as a valid assertion or de-assertion.
SRC_STOP# - Assertion (transition from '1' to '0')
Asserting SRC_STOP# causes all DIF outputs to stop after their next transition (if the control register settings allow the output
to stop). When the SRC_STOP# drive bit is ‘0’, the final state of all stopped DIF outputs is DIF = High and DIF# = Low. There
is no change in output drive current. DIF is driven with 6xIREF. DIF# is not driven, but pulled low by the termination. When the
SRC_STOP# drive bit is ‘1’, the final state of all DIF output pins is Low. Both DIF and DIF# are not driven.
SRC_STOP# - De-assertion (transition from '0' to '1')
All stopped differential outputs resume normal operation in a glitch-free manner. The de-assertion latency to active outputs is
2-6 DIF clock periods, with all DIF outputs resuming simultaneously. If the SRC_STOP# drive control bit is ‘1’ (tri-state), all
stopped DIF outputs must be driven High (>200 mV) within 10 ns of de-assertion.
SRC_STOP_1 (SRC_Stop = Driven, PD = Driven)
1mS
SRC_Stop#
PWRDWN#
DIF (Free Running)
DIF# (Free Running)
DIF (Stoppable)
DIF# (Stoppable)
SRC_STOP_2 (SRC_Stop =Tristate, PD = Driven)
1mS
SRC_Stop#
PWRDWN#
DIF (Free Running)
DIF# (Free Running)
DIF (Stoppable)
DIF# (Stoppable)
1014B—09/07/06
12
Integrated
Circuit
ICS9DB401
Systems, Inc.
SRC_STOP_3 (SRC_Stop = Driven, PD = Tristate)
1mS
SRC_Stop#
PWRDWN#
DIF (Free Running)
DIF# (Free Running)
DIF (Stoppable)
DIF# (Stoppable)
SRC_STOP_4 (SRC_Stop = Tristate, PD = Tristate)
1mS
SRC_Stop#
PWRDWN#
DIF (Free Running)
DIF# (Free Running)
DIF (Stoppable)
DIF# (Stoppable)
1014B—09/07/06
13
Integrated
Circuit
ICS9DB401
Systems, Inc.
209 mil SSOP
I n M ill im e t e r s
c
I n I n c h e s
N
S YM B O L
C O M M O N D I MEN S I O N S C O M MO N D I M E N SI O N S
M IN
- -
0 .0 5
1 .65
0 .2 2
0 .0 9
M A
2.0 0
- -
1.8 5
0 .3 8
0 .2 5
M I N
- -
. 0 0 2
. 06 5
. 0 0 9
. 0 03 5
M A
.0 79
- -
.0 73
.0 1 5
.0 1 0
L
A
A 1
A2
b
E1
E
INDEX
AREA
c
D
E
E1
e
S EE V ARI A T I O NS
S E E V A RIA T IO N S
7 .4 0
5 .00
8 .2 0
5.6 0
. 2 9 1
. 19 7
.3 2 3
.2 20
1
22
0 .6 5 BA SIC
0
.
0
2
5
6
B
A
S
I
C
α
L
N
α
0
.
5
5
0 .9 5
. 0 2 2
.0 3 7
D
S EE V ARI A T I O NS
0
S E E V A RIA T IO N S
0
A
A2
8
8
A1
V
A
R
I
A
T
I
O
N
S
- C -
D m m .
D ( inc h)
N
M IN
9 .9 0
M A
1 0. 5 0
M I N
. 3 90
M A
e
SEATING
PLANE
2 8
.4 1 3
b
R e fe r enc e D o c. : E D E C P u bl i c ati o n 95 , MO - 150
.10 (.004) C
10- 0 033
Ordering Information
ICS9DB401yFLFT
Example:
ICS XXXX y F LF T
Designation for tape and reel packaging
RoHS Compliant (Optional)
Package Type
F = SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 to 7 digit numbers)
Prefix
ICS, AV = Standard Device
1014B—09/07/06
14
Integrated
Circuit
ICS9DB401
Systems, Inc.
4.40 mm. Body, 0.65 mm. Pitch TSSOP
(173 mil) (25.6 mil)
In Millimeters
COMMON DIMENSIONS
c
N
In Inches
COMMON DIMENSIONS
SYMBOL
L
MIN
--
MAX
1.20
0.15
1.05
0.30
0.20
MIN
--
MAX
.047
.006
.041
.012
.008
A
A1
A2
b
0.05
0.80
0.19
0.09
.002
E1
E
.032
.007
.0035
INDEX
AREA
c
D
E
SEE VARIATIONS
6.40 BASIC
SEE VARIATIONS
0.252 BASIC
1
22
E1
e
L
4.30
0.65 BASIC
0.45
4.50
.169
.177
0.0256 BASIC
.030
SEE VARIATIONS
α
0.75
.018
D
N
SEE VARIATIONS
a
aaa
0°
--
8°
0.10
0°
--
8°
.004
A
VARIATIONS
A2
D mm.
D (inch)
N
MIN
9.60
MAX
9.80
MIN
.378
MAX
.386
A1
28
- CC --
Reference Doc.: JEDEC Publication 95, MO-153
10-0035
e
SEATING
PLANE
b
aaa
C
Ordering Information
ICS9DB401yGLFT
Example:
ICS XXXX y G LF T
Designation for tape and reel packaging
RoHS Compliant (Optional)
Package Type
G = TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 to 7 digit numbers)
Prefix
ICS, AV = Standard Device
1014B—09/07/06
15
Integrated
Circuit
ICS9DB401
Systems, Inc.
Revision History
Rev.
Issue Date Description
Page #
0.1
4/21/2005 Changed Ordering Information from"LN" to "LF".
1. Updated LF Ordering Information to RoHS Compliant.
8/15/2005 2. Release to web.
14,15
14-15
A
B
9
/
7
/
2
0
0
6
U
p
d
a
t
e
d
E
l
e
c
t
r
i
c
a
l
C
h
a
r
a
c
t
e
r
i
s
t
i
c
s
.
5
1014B—09/07/06
16
G l o ba l S i t es
S
e
a
r
c
h
E
n
t
i
r
e
S
i
t
e
C on ta c t I D T | Inv es t or s | P re s s
Ema i l | Pri n t
Do c u m e n t S e a r c h | P a c k a g e S e a r c h | P a r a m e t r i c S e a r c h | Cr o s s R e f e r e n c e S e a r c h | Gr e e n & R o H S | Ca l c u l a t o r s | Th e rm a l D a t a | R e l i a b i l i t y & Q u a l i t y | M i l i t a ry
H
o
m
e
>
P
r
o
d
u
c
t
s
>
P
C
C
l
o
c
k
s
>
C
l
o
c
k
B
u
f
f
e
r
s
>
9
D
B
4
0
1
Y ou m ay al s o l i k e. . .
Add to myIDT [?]
9DB401 (Clock Buffers)
Description
F o u r O ut p u t D if f e r en t i a l B u f f er f o r P C I E xpr ess. D B8 0 0 Ve rs io n 2 .0 Ye llo w Co ve r p ar t w it h P C I E xp re ss S u p p o rt w it h e xt e n d e d b yp a s s m o d e
f re q ue n cy r an g e.
Market Group
PC C LOC K
Additional Info
T he IC S9 D B401 f ol lo ws th e In te l D B4 00 Di f fe ren t ia l B uff er S pec i fi ca ti on v2 .0. Th is b uff er p rov i des fo ur P CI- E xp res s S RC c lo c k s . T he IC S9 DB4 01
is dr i v en by a d if fe re n t ia l i np u t p a ir f r om a CK4 09 /C K 4 1 0/ C K4 1 0 M m a i n c l oc k gen e ra to r, su ch as th e I CS 952 60 1, ICS 9 5410 1 o r IC S9 5 4 2 0 1 . It
p ro vi de s ou p u ts m eet in g ti gh t cyc le- to - cyc l e j i t t e r (5 0p s) a nd o ut pu t - t o -o ut put s k ew ( 5 0 p s) r e q ui r em e nt s. 2 8 - p in S SOP / T SS O P
Related Orderable Parts
1 2
A tt ri b ut es
Package
9DB 4 01B F LF
9
D
B
4
0
1
B
F
L
F
T
9DB 401 B GL F
9 D B4 0 1 B GL FT
9D B4 0 1 C F L F
9 D B 4 01 C F L F T
S
S
O
P
2
8
(
P
Y
G
2
8
)
SSO P 2 8 ( PYG2 8)
TS S O P 2 8 (P G G 28)
T
S
S
O
P
2
8
(
P
G
G
2
8
)
SSO P 28 ( PYG 28)
SSO P 28 ( PYG 28)
N A
C
N A
C
N A
C
N A
C
NA
C
NA
C
Speed
Temperature
Voltage
Status
3.3 V
Ac t i ve
Y es
3 .3 V
Ac t i v e
No
3 .3 V
Ac t i v e
Ye s
3 .3 V
A ct i ve
No
3. 3 V
A ct i ve
Yes
3. 3 V
A ct i ve
No
Sample
Minimum Order
Quantity
18 8
47
1 00 0
1 00 0
1 92
4 8
1 00 0
1 00 0
18 8
47
10 00
10 00
Factory Order
Increment
1 2
Related Documents
Typ e
T itle
Size
Re visi o n D at e
D at ash ee t
9D B 401 Da t a she e t
2 44 K B
0 5/2 2 /20 0 7
H om e | S i t e Ma p | A b o ut I DT | P r e ss R oo m | I nv est o r R e la t i o n s | Tr ad em a rk | P ri v a c y P ol i c y | C ar ee rs | R eg i s te r | Co n t a ct U s
U s e of th i s w eb s i te s i g ni f i es y ou r ag re em e nt to th e a cc ep t a ble us e a n d p riv a c y p oli cy . C o p y r ig ht 1 9 9 7 - 20 07 In t e g r a te d D e vice T ec hn olo g y , In c. A l l R i g ht s R e s e r v e d.
N o d e: ww w . id t . co m
Se a rch En t i re Si t e
Co n t a ct I DT | I n ve st o rs | Pre ss
Do c u me n t Se a r c h | Pa c ka g e Se a r c h | Pa r a me t r ic Se a r c h | Cr o s s Re f e r e n c e Se a r c h | Gr e e n & Ro HS | Ca lc u la t o r s | Th e r ma l Da t a | Re lia b ilit y & Qu a lit y | Milit a r y
A d d t o m y I DT [ ?] Ho m e > Pro d u ct s > PC Cl o cks > Cl o ck Bu f f e rs > 9 DB4 0 1
9DB401 (Clock Buffe rs)
De s c r ipt ion
Fo u r Ou tp u t D i ffe r e n ti a l Bu ffe r fo r PC I Exp r e s s . D B8 0 0 Ve r s i o n 2 .0 Ye l l o w C o ve r p a r t w i th PC I Exp r e s s Su p p o r t w i th e xte n d e d b yp a s s m o d e
fr e q u e n c y r a n g e .
M a r k e t Gr oup
PC C L OC K
Addit iona l Inf o
Th e IC S9 D B4 0 1 fo l l o w s th e In te l D B4 0 0 D i ffe r e n ti a l Bu ffe r Sp e c i fi c a ti o n v2 .0 . Th i s b u ffe r p r o vi d e s fo u r PC I- Exp r e s s SR C c l o c k s . Th e
IC S9 D B4 0 1 i s d r i ve n b y a d i ffe r e n ti a l i n p u t p a i r fr o m a C K4 0 9 /C K4 1 0 /C K4 1 0 M m a i n c l o c k g e n e r a to r , s u c h a s th e IC S9 5 2 6 0 1 , IC S9 5 4 1 0 1 o r
IC S9 5 4 2 0 1 . It p r o vi d e s o u p u ts m e e ti n g ti g h t c ycl e - to - c yc l e j i tte r ( 5 0 p s ) a n d o u tp u t- to - o u tp u t s k e w ( 5 0 p s ) r e q u i r e m e n ts . 2 8 - p i n SSOP/TSSOP
Yo u m a y a l so l i ke . . .
Re la t e d Or de r a ble Pa r t s
2
1
Attr i b u te s
Pa c k a ge
9 D B4 0 1 BFL F
9 D B4 0 1 BFL FT
9 D B4 0 1 BGL F
9 D B4 0 1 BGL FT
9 D B4 0 1 C FL F
9 D B4 0 1 C FL FT
SSOP 2 8 ( PYG2 8 )
SSOP 2 8 ( PYG2 8 )
TSSOP 2 8 ( PGG2 8 )
TSSOP 2 8 ( PGG2 8 )
SSOP 2 8 ( PYG2 8 )
SSOP 2 8 ( PYG2 8 )
Spe e d
N A
C
N A
C
N A
C
N A
C
N A
C
N A
C
Te m pe r a t ur e
Volt a ge
St a t us
3 .3 V
Ac ti ve
Ye s
3 .3 V
Ac ti ve
N o
3 .3 V
Ac ti ve
Ye s
3 .3 V
Acti ve
N o
3 .3 V
Ac ti ve
Ye s
3 .3 V
Ac ti ve
N o
Sa m ple
M inim um Or de r
Qua nt it y
1 8 8
4 7
1 0 0 0
1 0 0 0
1 9 2
4 8
1 0 0 0
1 0 0 0
1 8 8
4 7
1 0 0 0
1 0 0 0
Fa c t or y Or de r
Inc r e m e nt
2
1
Re la t e d Doc um e nt s
Typ e
Ti tl e
9 D B4 0 1 D a ta s h e e t
Si ze
R e vi s i o n D a te
D a ta s h e e t
2 4 4 KB
0 5 /2 2 /2 0 0 7
Ho m e | Si t e M a p | Ab o u t I DT | Pre ss Ro o m | I n ve st o r Re l a t i o n s | T ra d e m a rk | Pri va cy Po l i cy | Ca re e rs | Re g i st e r | Co n t a ct Us
Use o f t h i s we b si t e si g n i f i e s yo u r a g re e m e n t t o t h e a cce p t a b l e u se a n d p ri va cy p o l i cy. Co p yri g h t 1 9 9 7 -2 0 0 7 I n t e g ra t e d De vi ce T e ch n o l o g y, I n c. Al l Ri g h t s Re se rve d .
N o d e : w w w .i d t.c o m
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