ICS9FG104 [ICSI]
Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks; 差分P4TM CPU ， PCI - Express的＆ SATA时钟可编程FTG
| 型号： | ICS9FG104 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks |
| 文件： | 总15页 (文件大小：163K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated
Circuit
ICS9FG104
Systems, Inc.
Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks
Recommended Application:
Pin Configuration
Frequency Timing Generator for Differential CPU & SATA clocks
XIN/CLKIN
X2
1
2
3
4
5
6
7
8
9
28 VDDA
27 GNDA
26 IREF
25 FS0
Features:
VDD
GND
•
Generates common CPU frequencies from 14.318 MHz
or 25 MHz
•
•
•
•
Crystal or reference input
4 - 0.7V current-mode differential output pairs
Supports Serial-ATA at 100 MHz
Two spread spectrum modes: 0 to -0.5 downspread and
+/-0.25% centerspread
REFOUT
FS2
DIF_3
DIF_3#
VDD
GND 10
DIF_2 11
DIF_2# 12
SDATA 13
24 FS1
23
22
21
DIF_0
DIF_0#
VDD
20 GND
19
•
•
Unused inputs may be disabled in either driven or Hi-Z
state for power management.
M/N Programming
DIF_1
18 DIF_1#
17 SEL14M_25M#
16 SPREAD
Key Specifications:
14
15
DIF_STOP#
SCLK
•
•
•
Output cycle-to-cycle jitter < 50 ps
Output to output skew < 35 ps
+/-300 ppm frequency accuracy on output clocks
28-pin SSOP/TSSOP
Frequency Select Table
SEL14M_25M#
FS2 FS1 FS0 OUTPUT(MHz)
(FS3)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
100.00
125.00
133.33
166.67
200.00
266.00
333.00
400.00
100.00
125.00
133.33
166.67
200.00
266.00
333.00
400.00
0839D—06/02/05
Integrated
Circuit
ICS9FG104
Systems, Inc.
Pin Description
PIN #
PIN NAME
XIN/CLKIN
X2
VDD
PIN TYPE
DESCRIPTION
Crystal input or Reference Clock input
Crystal output, Nominally 14.318MHz
Power supply, nominal 3.3V
1
2
3
4
IN
OUT
PWR
IN
GND
Ground pin.
5
6
REFOUT
FS2
IN
IN
Reference Clock output
Frequency select pin.
7
8
9
10
11
12
13
14
15
DIF_3
DIF_3#
VDD
IN
0.7V differential true clock outputs
0.7V differential complement clock outputs
Power supply, nominal 3.3V
OUT
PWR
PWR
OUT
OUT
I/O
GND
Ground pin.
DIF_2
DIF_2#
SDATA
SCLK
DIF_STOP#
0.7V differential true clock outputs
0.7V differential complement clock outputs
Data pin for SMBus circuitry, 5V tolerant.
Clock pin of SMBus circuitry, 5V tolerant.
Active low input to stop differential output clocks.
IN
IN
Asynchronous, active high input, with internal 120Kohm pull-up resistor,
to enable spread spectrum functionality.
Select 14.31818 MHz or 25 Mhz input frequency. 1 = 14.31818 MHz, 0 =
25 MHz
16
17
SPREAD
IN
IN
SEL14M_25M#
18
19
20
21
22
23
24
25
DIF_1#
DIF_1
GND
OUT
OUT
PWR
PWR
OUT
OUT
IN
0.7V differential complement clock outputs
0.7V differential true clock outputs
Ground pin.
Power supply, nominal 3.3V
0.7V differential complement clock outputs
0.7V differential true clock outputs
VDD
DIF_0#
DIF_0
FS1
Frequency select pin.
Frequency select pin.
FS0
IN
This pin establishes the reference current for the differential current-
mode output pairs. This pin requires a fixed precision resistor tied to
ground in order to establish the appropriate current. 475 ohms is the
standard value.
26
IREF
OUT
27
28
GNDA
VDDA
PWR
PWR
Ground pin for the PLL core.
3.3V power for the PLL core.
0839D—06/02/05
2
Integrated
Circuit
ICS9FG104
Systems, Inc.
General Description
The ICS9FG104 is a Frequency Timing Generator that provides 4 differential output pairs that are compliant to the Intel CK410
specification. It also provides support for PCI-Express and SATA. The part synthesizes several output frequencies from either
a 14.31818 Mhz crystal or a 25 MHz crystal. The device can also be driven by a reference input clock instead of a crystal. It
provides outputs with cycle-to-cycle jitter of less than 50 ps and output-to-output skew of less than 35 ps.
The ICS9FG104 also provides a copy of the reference clock. Frequency selection can be accomplished via strap pins or
SMBus control.
Block Diagram
XIN/CLKIN
X2
REFOUT
OSC
2
4
PROGRAMMABLE
SPREAD PLL
STOP
LOGIC
DIF(3:0)
SPREAD
SEL14M_25M#
CONTROL
LOGIC
DIF_STOP#
FS(2:0)
SDATA
SCLK
IREF
Power Groups
Pin Number
VDD
3
GND
4
Description
REFOUT, Digital Inputs
DIF Outputs
9,21
28
10,20
27
IREF, Analog VDD, GND for PLL Core
0839D—06/02/05
3
Integrated
Circuit
ICS9FG104
Systems, Inc.
Absolute Max
Symbol
VDD_A
VDD_In
Parameter
Min
Max
Units
3.3V Core Supply Voltage
3.3V Logic Input Supply Voltage
V
V
DD + 0.5V
DD + 0.5V
V
V
°C
°C
°C
GND - 0.5
Ts
Tambient
Tcase
Storage Temperature
Ambient Operating Temp
Case Temperature
Input ESD protection
-65
0
150
70
115
human body model
ESD prot
2000
V
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
SYMBOL
CONDITIONS
MIN TYP MAX UNITS NOTES
VDD + 0.3
VIH
VIL
IIH
3.3 V +/-5%
3.3 V +/-5%
VIN = VDD
2
V
V
uA
1
1
1
VSS - 0.3
0.8
5
-5
-5
VIN = 0 V; Inputs with no pull-up
resistors
IIL1
uA
1
Input Low Current
VIN = 0 V; Inputs with pull-up
resistors
IIL2
-200
uA
1
Full Active, CL = Full load;
125
110
150
125
mA
mA
1
1
f = 400 MHz
Full Active, CL = Full load;
IDD3.3OP
Operating Supply Current
Input Frequency3
f = 100 MHz
All outputs stopped driven
All outputs stopped Hi-Z
VDD = 3.3 V
106
48
120
60
25
7
5
6
mA
mA
MHz
nH
pF
pF
1
1
3
1
1
1
IDD3.3STOP
Fi
Lpin
CIN
COUT
14
Pin Inductance1
Input/Output
Logic Inputs
Output pin capacitance
From VDD Power-Up and after
input clock stabilization to 1st
clock
1.5
Capacitance1
Clk Stabilization1,2
TSTAB
1.8
ms
1,2
fMOD
Modulation Frequency
DIF output enable
Triangular Modulation
DIF output enable after
DIF_Stop# de-assertion
30
33
15
kHz
ns
1
1
tDIFOE
tR/tF
Input Rise and Fall times
20% to 80% of VDD
5
ns
1
1Guaranteed by design, not 100% tested in production.
2See timing diagrams for timing requirements.
3 Input frequency should be measured at the REFOUT pin and tuned to ideal 14.31818MHz or 25 MHz to
meet
0839D—06/02/05
4
Integrated
Circuit
ICS9FG104
Systems, Inc.
Electrical Characteristics - DIF 0.7V Current Mode Differential Pair
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2Ω, RP=49.9Ω, ΙREF = 475Ω
PARAMETER
SYMBOL
Zo1
CONDITIONS
VO = Vx
MIN
TYP
MAX
850
UNITS NOTES
Output Impedance
3000
1
1
Ω
Statistical measurement on single
ended signal using oscilloscope
math function.
Voltage High
Voltage Low
VHigh
660
mV
VLow
-150
150
1
Measurement on single ended
signal using absolute value.
Max Voltage
Min Voltage
Crossing Voltage (abs)
Vovs
Vuds
Vcross(abs)
1150
1
1
1
mV
mV
mV
-300
250
550
140
Crossing Voltage (var)
Long Accuracy
d-Vcross
ppm
Crossing variation over all edges
1
see Tperiod min-max values
400MHz nominal
-300
300
ppm
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
1,2
2
2,3
2
2,3
2
2,3
2
2,3
2
2,3
2
2,3
2
2,3
1,2
1,2
1,2
1,2
1,2
1,2
1,2
1
1
1
1
1
4
2.4993
2.4993
2.9991
2.9991
3.7489
3.7489
4.9985
4.9985
5.9982
5.9982
7.4978
7.4978
9.9970
9.9970
2.4143
2.9141
3.6639
4.8735
5.8732
7.3728
9.8720
175
2.5008
2.5133
3.0009
3.016
3.7511
3.77
5.0015
5.0266
6.0018
6.0320
7.5023
5.4000
10.0030
10.0533
400MHz spread
333.33MHz nominal
333.33MHz spread
266.66MHz nominal
266.66MHz spread
200MHz nominal
200MHz spread
166.66MHz nominal
166.66MHz spread
133.33MHz nominal
133.33MHz spread
100.00MHz nominal
Average period
Tperiod
100.00MHz spread
400MHz nominal/spread
333.33MHz nominal/spread
266.66MHz nominal/spread
200MHz nominal/spread
166.66MHz nominal/spread
133.33MHz nominal/spread
100.00MHz nominal/spread
VOL = 0.175V, VOH = 0.525V
VOH = 0.525V VOL = 0.175V
Tabsmin
Absolute min period
tr
tf
d-tr
d-tf
dt3
tsk3
Rise Time
Fall Time
Rise Time Variation
Fall Time Variation
Duty Cycle
700
700
125
125
55
175
ps
ps
ps
%
Measured Differentially
VT = 50%
45
Skew, output to output
35
ps
22MHz/1.5MHz/1.5MHz/10ns,
14.31818 MHz REF Clock
22MHz/1.5MHz/1.5MHz/10ns,
25 MHz REF Clock
tjPCI-ephase14
Jitter, PCI-e SRC phase
42
ps
4
tjPCI-ephase25
tjcyc-cyc
Jitter, PCI-e SRC phase
Jitter, Cycle to cycle
39
50
ps
ps
4
1
Measured Differentially
1Guaranteed by design and characterization, not 100% tested in production.
2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz
or 25 MHz
3 Figures are for down spread.
4 This figure is the peak-to-peak phase jitter as defined by PCI-SIG for a PCI Express reference clock. Please visit
http://www.pcisig.com for additional details
0839D—06/02/05
5
Integrated
Circuit
ICS9FG104
Systems, Inc.
Electrical Characteristics - REF-14.318/25 MHz
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 30 pF (unless otherwise specified)
SYMBO
PARAMETER
Long Accuracy
Clock period
CONDITIONS
MIN
-300
TYP
0
MAX UNITS Notes
L
ppm
see Tperiod min-max values
14.318MHz output nominal
25.000MHz output nominal
IOH = -1 mA
300
ppm
ns
ns
V
1
1
1
1
1
69.8270 69.8413 69.8550
Tperiod
39.9880 40.0000 40.0120
Output High Voltage
Output Low Voltage
VOH
VOL
2.4
IOL = 1 mA
0.4
V
VOH @MIN = 1.0 V,
VOH@MAX = 3.135 V
VOL @MIN = 1.95 V,
VOL @MAX = 0.4 V
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
Output High Current
Output Low Current
IOH
IOL
-29
29
-23
27
mA
mA
1
1
Rise Time
Fall Time
Duty Cycle
Jitter
tr1
tf1
1
1
1.6
1.6
2
2
ns
ns
%
1
1,2
1,2
1
dt1
45
52.5
150
55
200
tjcyc-cyc
VT = 1.5 V
ps
1Guaranteed by design and characterization, not 100% tested in production.
2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at
14.31818MHz or 25 MHz
0839D—06/02/05
6
Integrated
Circuit
ICS9FG104
Systems, Inc.
General SMBus serial interface information for the ICS9FG104
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address DC(H)
• ICS clock will acknowledge
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the write address DC(H)
• ICS clock will acknowledge
• Controller (host) sends the begining byte location = N
• ICS clock will acknowledge
• Controller (host) sends the begining byte
location = N
• Controller (host) sends the data byte count = X
• ICS clock will acknowledge
• Controller (host) starts sending Byte N through
Byte N + X -1
• ICS clock will acknowledge
• Controller (host) will send a separate start bit.
• Controller (host) sends the read address DD(H)
• ICS clock will acknowledge
(see Note 2)
• ICS clock will send the data byte count = X
• ICS clock sends Byte N + X -1
• ICS clock will acknowledge each byte one at a time
• ICS clock sends Byte 0 through byte X (if X(H)
was written to byte 8).
• Controller (host) sends a Stop bit
• Controller (host) will need to acknowledge each byte
• Controllor (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
Index Block Read Operation
Index Block Write Operation
Controller (Host)
ICS (Slave/Receiver)
Controller (Host)
ICS (Slave/Receiver)
starT bit
T
starT bit
T
Slave Address DC(H)
Slave Address DC(H)
WR
WRite
WR
WRite
Beginning Byte = N
Data Byte Count = X
Beginning Byte N
ACK
ACK
ACK
ACK
ACK
ACK
Beginning Byte = N
RT
Repeat starT
Slave Address DD(H)
RD
ReaD
ACK
Data Byte Count = X
Beginning Byte N
ACK
ACK
Byte N + X - 1
ACK
P
stoP bit
Byte N + X - 1
N
P
Not acknowledge
stoP bit
0839D—06/02/05
7
Integrated
Circuit
ICS9FG104
Systems, Inc.
SMBus Table: Device Control Register, READ/WRITE ADDRESS (DC/DD)
Byte 0
Pin #
Name
Control Function
SEL14M_25M#1
Type
0
1
PWD
17
RW
Pin 17
Bit 7
See Frequency
Selection Table,
Page 1
(FS3)
FS21
FS11
FS01
6
RW
RW
RW
Pin 6
Pin 24
Pin 25
Bit 6
Bit 5
Bit 4
24
25
16
Spread Enable1
RW
Off
On
Pin 16
Bit 3
Enable Software Control of Frequency,
Spread Enable (Spread Type always
Software Control)
Hardware Software
-
RW
0
Bit 2
Select
Select
DIF_STOP# drive mode
SPREAD TYPE
RW
RW
Driven
Down
Hi-Z
Center
0
0
Bit 1
Bit 0
Notes:
1. These bits reflect the state of the corresponding pins at power up, but may be written to
if Byte 0, bit 2 is set to '1'. FS3 is the SEL14M_25M# pin.
SMBus Table: Output Enable Register
Byte 1
Bit 7
Pin #
Name
Control Function
Reserved
Output Enable
Output Enable
Reserved
Type
0
1
PWD
-
-
-
-
-
-
-
-
1
1
1
1
1
1
1
1
DIF_3 EN
DIF_2 EN
RW Disable
RW Disable
Enable
Enable
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
DIF_1 EN
DIF_0 EN
Output Enable
Output Enable
Reserved
RW Disable
RW Disable
Enable
Enable
SMBus Table: Output Stop Control Register
Byte 2
Bit 7
Pin #
Name
Control Function
Type
0
1
PWD
-
-
-
-
-
-
-
-
Reserved
0
0
0
0
0
0
0
0
DIF_3 STOP EN Free Run/ Stop Enable RW Free-run Stop-able
DIF_2 STOP EN Free Run/ Stop Enable RW Free-run Stop-able
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Reserved
DIF_1 STOP EN Free Run/ Stop Enable RW Free-run Stop-able
DIF_0 STOP EN Free Run/ Stop Enable RW Free-run Stop-able
Reserved
0839D—06/02/05
8
Integrated
Circuit
ICS9FG104
Systems, Inc.
SMBus Table: Frequency Select Readback Register
Byte 3
Pin #
Name
SEL14M_25M#1
(FS3)
Control Function
Type
0
1
PWD
17
State of pin 17
R
Pin 17
Bit 7
See Frequency
Selection Table,
Page 1
FS21
6
State of pin 6
State of pin 24
State of pin 25
R
R
R
R
Pin 6
Pin 24
Pin 25
Bit 6
Bit 5
Bit 4
FS11
24
25
16
FS01
SPREAD1
State of pin 16
Reserved
Off
On
Pin 16
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
Reserved
Reserved
Notes:
1. These bits reflect the state of the corresponding pins, regardless of whether software
programming is enabled or not.
SMBus Table: Vendor & Revision ID Register
Byte 4
Bit 7
Pin #
Name
RID3
RID2
RID1
RID0
VID3
VID2
VID1
VID0
Control Function
Type
R
R
R
R
R
R
R
R
0
-
-
-
-
-
-
-
-
1
-
-
-
-
-
-
-
-
PWD
-
-
-
-
-
-
-
-
X
X
X
X
0
0
0
1
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
REVISION ID
VENDOR ID
SMBus Table: DEVICE ID
Byte 5 Pin #
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
DID7
DID6
DID5
DID4
DID3
DID2
DID1
DID0
Control Function
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
-
-
-
-
-
-
-
-
1
-
-
-
-
-
-
-
-
PWD
-
-
-
-
-
-
-
-
0
0
0
0
1
0
0
0
Device ID = 08 hex
0839D—06/02/05
9
Integrated
Circuit
ICS9FG104
Systems, Inc.
SMBus Table: Byte Count Register
Byte 6
Bit 7
Pin #
Name
BC7
BC6
BC5
BC4
BC3
BC2
BC1
BC0
Control Function
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
-
-
-
-
-
-
-
-
1
-
-
-
-
-
-
-
-
PWD
-
-
-
-
-
-
-
-
0
0
0
0
0
1
1
1
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Writing to this register
will configure how
many bytes will be
read back, default is
07 = 7 bytes.
SMBus Table: Reserved Register
Byte 7 Pin # Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Control Function
Reserved
Type
Type
Type
0
0
0
1
PWD
-
-
-
-
-
-
-
-
0
0
0
0
0
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SMBus Table: Reserved Register
Byte 8 Pin # Name
Bit 7
Control Function
Reserved
1
PWD
-
-
-
-
-
-
-
-
0
0
0
0
0
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SMBus Table: M/N Programming Enable
Byte 9
Bit 7
Pin #
Name
M/N_Enable
Control Function
M/N Prog. Enable
Reserved
REFOUT Enable
Reserved
1
PWD
-
-
RW Disable
Enable
0
1
1
0
0
0
0
0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
5
-
REFOUT_En
RW Disable
Enable
-
-
-
-
Reserved
Reserved
Reserved
Reserved
0839D—06/02/05
10
Integrated
Circuit
ICS9FG104
Systems, Inc.
SMBus Table: PLL Frequency Control Register
Byte 10
Bit 7
Pin #
Name
Control Function
N Divider Prog bit 8
N Divider Prog bit 9
Type
RW
RW
RW
RW
RW
RW
RW
0
1
PWD
X
X
X
X
X
X
X
The decimal
-
-
-
-
-
-
-
PLL N Div8
PLL N Div9
PLL M Div5
PLL M Div4
PLL M Div3
PLL M Div2
PLL M Div1
representation of M and
N Divider in Byte 11 and
12 will configure the PLL
VCO frequency.
Default at power up =
latch-in or Byte 0 Rom
table. VCO Frequency
= 14.318 x
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
M Divider
Programming
bit (5:0)
[NDiv(9:0)+8] /
[MDiv(5:0)+2]
-
PLL M Div0
RW
X
Bit 0
SMBus Table: PLL Frequency Control Register
Byte 11
Bit 7
Pin #
Name
Control Function
Type
RW
RW
RW
RW
0
1
PWD
X
X
X
X
X
X
X
The decimal
-
-
-
-
-
-
-
PLL N Div7
PLL N Div6
PLL N Div5
PLL N Div4
PLL N Div3
PLL N Div2
PLL N Div1
representation of M and
N Divider in Byte 11 and
12 will configure the PLL
VCO frequency.
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
N Divider
Programming Byte11
bit(7:0) and Byte10
bit(7:6)
RW Default at power up =
latch-in or Byte 0 Rom
RW
table. VCO Frequency
RW
= 14.318 x
[NDiv(9:0)+8] /
[MDiv(5:0)+2]
-
PLL N Div0
RW
X
Bit 0
SMBus Table: PLL Spread Spectrum Control Register
Byte 12
Bit 7
Pin #
Name
Control Function
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
PWD
X
X
X
X
X
X
X
X
-
-
-
-
-
-
-
-
PLL SSP7
PLL SSP6
PLL SSP5
PLL SSP4
PLL SSP3
PLL SSP2
PLL SSP1
PLL SSP0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
These Spread
Spectrum bits in Byte
13 and 14 will program
the spread pecentage
of PLL
Spread Spectrum
Programming bit(7:0)
SMBus Table: PLL Spread Spectrum Control Register
Byte 13
Bit 7
Pin #
Name
Control Function
Type
0
1
PWD
0
X
X
X
X
X
X
X
-
-
-
-
-
-
-
-
Reserved
PLL SSP14
PLL SSP13
PLL SSP12
PLL SSP11
PLL SSP10
PLL SSP9
PLL SSP8
RW
RW
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
These Spread
RW Spectrum bits in Byte
Spread Spectrum
Programming bit(14:8)
13 and 14 will program
RW
the spread pecentage
RW
of PLL
RW
RW
0839D—06/02/05
11
Integrated
Circuit
ICS9FG104
Systems, Inc.
DIF_STOP# - Assertion (transition from '1' to '0')
Asserting DIF_STOP# pin stops all DIF outputs that are set to be stoppable after their next transition. When the SMBus
DIF_STOP tri-state bit corresponding to the DIF output of interest is programmed to a '0', DIF output will stop DIF_True =
HIGH and DIF_Complement = LOW. When the SMBus DIF_STOP tri-state bit corresponding to the DIF output of interest is
programmed to a '1', DIFoutputs will be tri-stated.
DIF_STOP#
DIF
DIF#
DIF_STOP# - De-assertion (transition from '0' to '1')
With the de-assertion of DIF_STOP# all stopped DIF outputs will resume without a glitch. The maximum latency from the
de-assertion to active outputs is 2 - 6 DIF clock periods. If the control register tristate bit corresponding to the output of
interest is programmed to '1', then the stopped DIF outputs will be driven High within 15nS of DIF_Stop# de-assertion to a
voltage greater than 200mV.
DIF_Stop#
DIF
DIF#
DIF Internal
Tdrive_DIF_Stop, 15nS >200mV
0839D—06/02/05
12
Integrated
Circuit
ICS9FG104
Systems, Inc.
c
5.3 mm. Body, 0.65 mm. Pitch SSOP
N
(204mil)
In Millimeters
COMMON DIMENSIONS
(25.6 mil)
In Inches
L
SYMBOL
COMMON DIMENSIONS
MIN
--
0.05
1.65
0.22
0.09
MAX
2.00
--
1.85
0.38
0.25
MIN
--
.002
.065
.009
.0035
MAX
.079
--
.073
.015
.010
E1
E
A
A1
A2
b
INDEX
AREA
1
2
c
D
E
E1
e
SEE VARIATIONS
SEE VARIATIONS
α
h x 45°
D
7.40
5.00
8.20
5.60
.291
.197
.323
.220
0.65 BASIC
0.0256 BASIC
L
N
0.55
0.95
.022
.037
A
SEE VARIATIONS
SEE VARIATIONS
α
0°
8°
0°
8°
A1
- C -
VARIATIONS
e
SEEAATTIINNGG
PLANE
D mm.
D (inch)
b
N
MIN
9.90
MAX
10.50
MIN
.390
MAX
.413
.10 (.004)
C
28
Reference Doc.: JEDEC Publication 95, MO-150
Ordering Information
ICS9FG104yFLFT
Example:
ICS XXXX y F - LF T
Designation for tape and reel packaging
RoHS Compliant (Optional)
Package Type
F = SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 to 7 digit numbers)
Prefix
ICS, AV = Standard Device
0839D—06/02/05
13
Integrated
Circuit
ICS9FG104
Systems, Inc.
4.40 mm. Body, 0.65 mm. Pitch TSSOP
c
N
(173 mil)
(25.6 mil)
In Millimeters
In Inches
SYMBOL
COMMON DIMENSIONS
COMMON DIMENSIONS
L
MIN
--
MAX
1.20
0.15
1.05
0.30
0.20
MIN
--
MAX
.047
.006
.041
.012
.008
A
A1
A2
b
0.05
0.80
0.19
0.09
.002
.032
.007
.0035
E1
E
INDEX
AREA
c
D
E
SEE VARIATIONS
6.40 BASIC
SEE VARIATIONS
0.252 BASIC
1
22
E1
e
L
4.30
0.65 BASIC
0.45
4.50
.169
0.0256 BASIC
.018 .030
SEE VARIATIONS
.177
α
0.75
D
N
SEE VARIATIONS
α
0°
--
8°
0.10
0°
--
8°
.004
aaa
VARIATIONS
A
A2
D mm.
D (inch)
N
MIN
9.60
MAX
9.80
MIN
.378
MAX
.386
A1
28
- CC --
Reference Doc.: JEDEC Publication 95, MO-153
10-0035
e
SEATING
PLANE
b
aaa
C
Ordering Information
ICS9FG104yGLFT
Example:
ICS XXXX y G LF T
Designation for tape and reel packaging
RoHS Compliant (Optional)
Package Type
G = TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 to 7 digit numbers)
Prefix
ICS, AV = Standard Device
0839D—06/02/05
14
Integrated
Circuit
ICS9FG104
Systems, Inc.
Revision History
Rev.
Issue Date Description
Page #
9, 13-14
1. Updated SMBus Byte 3 bit 7, 5, 4 and 3.
D
6/2/2005 2. Updated LF Ordering Information to RoHS Compliant.
0839D—06/02/05
15
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