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ICS9FG107YFLFT [ICSI]

Programmable FTG for Differential CPU, PCI Express & SATA Clocks; 可编程FTG微分CPU ，支持PCI Express＆ SATA时钟
ICS9FG107YFLFT
型号： ICS9FG107YFLFT
厂家： INTEGRATED CIRCUIT SOLUTION INC    INTEGRATED CIRCUIT SOLUTION INC
描述：

Programmable FTG for Differential CPU, PCI Express & SATA Clocks
可编程FTG微分CPU ，支持PCI Express＆ SATA时钟

PC 时钟
文件： 总14页 (文件大小：109K)
中文：  中文翻译
下载：  下载PDF数据表文档文件
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Integrated  
Circuit  
ICS9FG107  
Systems, Inc.  
Programmable FTG for Differential CPU, PCI Express* & SATA Clocks  
Recommended Application:  
Pin Configuration  
Frequency Timing Generator for Differential CPU, PCI Express  
& SATA clocks  
XIN/CLKIN  
X2  
1
2
3
4
5
6
7
8
9
48 VDDA  
47 GNDA  
46 IREF  
45 *DWNSPRD#  
44 **FS1  
43 *OE_0  
42 DIF_0  
41 DIF_0#  
40 VDD  
Features:  
VDD  
GND  
•
Generates common CPU/PCI Express frequencies from  
14.318 MHz or 25 MHz  
*FS2/REFOUT  
GND  
*FS0/PCICLK_F  
PCICLK0  
PCICLK1  
•
•
•
•
•
•
Crystal or reference input  
7 - 0.7V current-mode differential output pairs  
3 - 33MHz PCI outputs  
1 - REFOUT  
Supports Serial-ATA at 100 MHz  
VDD 10  
**OE_6 11  
DIF_6 12  
DIF_6# 13  
VDD 14  
39 DIF_1  
Two spread spectrum modes: 0 to -0.5 downspread and  
+/-0.25% centerspread  
38 DIF_1#  
37 **OE_1  
36 VDD  
•
Unused inputs may be disabled in either driven or Hi-Z  
state for power management.  
35 GND  
Key Specifications:  
GND 15  
34 **OE_2  
33 DIF_2  
32 DIF_2#  
31 VDD  
•
Output cycle-to-cycle jitter for DIF outputs < 50 ps (<85ps  
@ 266 MHz)  
**OE_5 16  
DIF_5 17  
DIF_5# 18  
VDD 19  
•
•
Output to output skew for DIF outputs < 85 ps  
+/-300 ppm frequency accuracy on output clocks  
30 DIF_3  
DIF_4 20  
DIF_4# 21  
*OE_4 22  
SDATA 23  
SCLK 24  
29 DIF_3#  
28 *OE_3  
27 **SEL14M_25M#  
26 *SPREAD  
25 DIF_STOP#  
Frequency Select Table  
SEL14M_25M#  
FS2 FS1 FS0 OUTPUT(MHz)  
(FS3)  
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
100.00  
125.00  
133.33  
166.67  
200.00  
266.66  
333.33  
400.00  
100.00  
125.00  
133.33  
166.67  
200.00  
266.66  
333.33  
400.00  
48-pin SSOP & TSSOP  
Notes:  
Pins preceeded by * have 120 Kohm pull DOWN resistors  
Pins preceeded by ** have 120 Kohm pull UP resistors  
0863C—11/22/04  
*Other names and brands may be claimed as the property of others.  
Integrated  
Circuit  
ICS9FG107  
Systems, Inc.  
Pin Description  
PIN  
#
1
PIN NAME  
XIN/CLKIN  
PIN TYPE  
DESCRIPTION  
Crystal input or Reference Clock input  
IN  
2
3
4
5
6
X2  
VDD  
GND  
*FS2/REFOUT  
GND  
OUT  
PWR  
PWR  
I/O  
Crystal output, Nominally 14.318MHz  
Power supply, nominal 3.3V  
Ground pin.  
Frequency select latch input pin / Reference clock output  
Ground pin.  
PWR  
7
*FS0/PCICLK_F  
I/O  
Frequency select latch input pin / 3.3V PCI free running clock output.  
8
9
10  
PCICLK0  
PCICLK1  
VDD  
OUT  
OUT  
PWR  
PCI clock output.  
PCI clock output.  
Power supply, nominal 3.3V  
Active high input for enabling outputs.  
0 = tri-state outputs, 1= enable outputs  
0.7V differential true clock outputs  
0.7V differential complement clock outputs  
Power supply, nominal 3.3V  
11  
**OE_6  
IN  
12  
13  
14  
15  
DIF_6  
DIF_6#  
VDD  
OUT  
OUT  
PWR  
PWR  
GND  
Ground pin.  
Active high input for enabling outputs.  
0 = tri-state outputs, 1= enable outputs  
0.7V differential true clock outputs  
0.7V differential complement clock outputs  
Power supply, nominal 3.3V  
0.7V differential true clock outputs  
0.7V differential complement clock outputs  
Active high input for enabling outputs.  
0 = tri-state outputs, 1= enable outputs  
Data pin for SMBus circuitry, 5V tolerant.  
Clock pin of SMBus circuitry, 5V tolerant.  
16  
**OE_5  
IN  
17  
18  
19  
20  
21  
DIF_5  
DIF_5#  
VDD  
DIF_4  
DIF_4#  
OUT  
OUT  
PWR  
OUT  
OUT  
22  
*OE_4  
IN  
23  
24  
SDATA  
SCLK  
I/O  
IN  
0863C—11/22/04  
2
Integrated  
Circuit  
ICS9FG107  
Systems, Inc.  
Pin Description (Continued)  
PIN  
#
25  
PIN NAME  
DIF_STOP#  
PIN TYPE  
DESCRIPTION  
IN  
IN  
Active low input to stop differential output clocks.  
Asynchronous, active high input, with internal 120Kohm pull-up  
resistor, to enable spread spectrum functionality.  
Select 14.31818 MHz or 25 Mhz input frequency. 1 = 14.31818 MHz,  
0 = 25 MHz  
Active high input for enabling outputs.  
0 = tri-state outputs, 1= enable outputs  
0.7V differential complement clock outputs  
0.7V differential true clock outputs  
26  
27  
28  
*SPREAD  
**SEL14M_25M#  
*OE_3  
IN  
IN  
29  
30  
31  
32  
33  
DIF_3#  
DIF_3  
VDD  
DIF_2#  
DIF_2  
OUT  
OUT  
PWR  
OUT  
OUT  
Power supply, nominal 3.3V  
0.7V differential complement clock outputs  
0.7V differential true clock outputs  
Active high input for enabling outputs.  
0 = tri-state outputs, 1= enable outputs  
Ground pin.  
34  
**OE_2  
IN  
35  
36  
GND  
VDD  
PWR  
PWR  
Power supply, nominal 3.3V  
Active high input for enabling outputs.  
0 = tri-state outputs, 1= enable outputs  
0.7V differential complement clock outputs  
0.7V differential true clock outputs  
Power supply, nominal 3.3V  
0.7V differential complement clock outputs  
0.7V differential true clock outputs  
37  
**OE_1  
IN  
38  
39  
40  
41  
42  
DIF_1#  
DIF_1  
VDD  
DIF_0#  
DIF_0  
OUT  
OUT  
PWR  
OUT  
OUT  
Active high input for enabling outputs.  
0 = tri-state outputs, 1= enable outputs  
Frequency select latch input pin / 3.3V 66.66MHz clock output.  
3.3V input that selects spread mode. This input is not latched at  
power up.  
43  
44  
*OE_0  
**FS1  
IN  
I/O  
45  
*DWNSPRD#  
IN  
0 = Down Spread, 1 = Center Spread  
This pin establishes the reference current for the differential current-  
mode output pairs. This pin requires a fixed precision resistor tied to  
ground in order to establish the appropriate current. 475 ohms is the  
standard value.  
46  
IREF  
OUT  
47  
48  
GNDA  
VDDA  
PWR  
PWR  
Ground pin for the PLL core.  
3.3V power for the PLL core.  
Pins preceeded by * have 120 Kohm pull DOWN resistors  
Pins preceeded by ** have 120 Kohm pull UP resistors  
0863C—11/22/04  
3
Integrated  
Circuit  
ICS9FG107  
Systems, Inc.  
General Description  
ICS9FG107 is a Frequency Timing Generator that provides 7 differential output pairs that are compliant to the Intel CK409/  
CK410 specification. It provides support for PCI-Express, next generation I/O, and SATA. The part synthesizes several output  
frequencies from either a 14.31818 Mhz crystal or a 25 MHz crystal. The device can also be driven by a reference input clock  
instead of a crystal. It provides outputs with cycle-to-cycle jitter of less than 85 ps and output-to-output skew of less than 85 ps.  
ICS9FG107 also provides a copy of the reference clock and 3 33 MHz PCI output clocks. Frequency selection can be  
accomplished via strap pins or SMBus control.  
Block Diagram  
XIN/CLKIN  
X2  
REFOUT  
PCICLK (1:0)  
PCICLK_F  
SCLK  
SDATA  
Programmable  
Spread  
Programmable  
Frequency  
Dividers  
DIF_STOP#  
SEL14M_25M#  
SPREAD  
PLL1  
DIF (6:0)  
Control  
Logic  
DIF# (6:0)  
DWNSPRD#  
OE (6:0)  
FS (2:0)  
I REF  
Power Groups  
Pin Number  
VDD  
3
10  
GND  
4
6
Description  
REFOUT, Digital Inputs, SMBus  
PCI Outputs  
DIF Outputs  
14,19,31,36,40  
15,35  
47  
47  
N/A  
48  
IREF  
Analog VDD & GND for PLL Core  
0863C—11/22/04  
4
Integrated  
Circuit  
ICS9FG107  
Systems, Inc.  
Absolute Max  
Symbol  
Parameter  
Min  
Max  
Units  
VDD_A  
3.3V Core Supply Voltage  
V
V
DD + 0.5V  
DD + 0.5V  
V
V
VDD_In 3.3V Logic Input Supply Voltage GND - 0.5  
Ts  
Tambient  
Tcase  
Storage Temperature  
Ambient Operating Temp  
Case Temperature  
-65  
0
150  
70  
115  
°C  
°C  
°C  
Input ESD protection  
human body model  
ESD prot  
2000  
V
Electrical Characteristics - Input/Supply/Common Output Parameters  
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%  
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS NOTES  
Input High Voltage  
Input Low Voltage  
Input High Current  
VIH  
VIL  
IIH  
3.3 V +/-5%  
3.3 V +/-5%  
2
VSS - 0.3  
-5  
VDD + 0.3  
V
V
0.8  
5
VIN = VDD  
uA  
VIN = 0 V; Inputs with no pull-  
up resistors  
IIL1  
-5  
uA  
Input Low Current  
VIN = 0 V; Inputs with pull-up  
resistors  
IIL2  
-200  
uA  
Full Active, CL = Full load;  
250  
200  
mA  
mA  
f = 400 MHz  
Full Active, CL = Full load;  
Operating Supply Current IDD3.3OP  
f = 100 MHz  
VDD = 3.3 V  
Input Frequency3  
Fi  
14  
25  
7
MHz  
nH  
3
1
1
1
Pin Inductance1  
Lpin  
Input/Output  
Capacitance1  
CIN  
Logic Inputs  
1.5  
5
pF  
COUT  
Output pin capacitance  
6
pF  
From VDD Power-Up and after  
input clock stabilization to 1st  
clock  
Clk Stabilization1,2  
TSTAB  
1.8  
ms  
1,2  
Modulation Frequency  
DIF output enable  
fMOD  
Triangular Modulation  
DIF output enable after  
DIF_Stop# de-assertion  
30  
40  
10  
kHz  
ns  
1
1
tDIFOE  
Input Rise and Fall times  
tR/tF  
20% to 80% of VDD  
5
ns  
1
1Guaranteed by design and characterization, not 100% tested in production.  
2See timing diagrams for timing requirements.  
3 Input frequency should be measured at the REFOUT pin and tuned to ideal 14.31818MHz or 25 MHz to meet  
ppm frequency accuracy on PLL outputs.  
0863C—11/22/04  
5
Integrated  
Circuit  
ICS9FG107  
Systems, Inc.  
Electrical Characteristics - DIF 0.7V Current Mode Differential Pair  
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2 , RP=49.9  
9,  
REF  
PARAMETER  
SYMBOL  
Zo1  
CONDITIONS  
VO = Vx  
MIN  
TYP  
MAX  
850  
UNITS NOTES  
1
Current Source Output  
Impedance  
3000  
Statistical measurement on  
single ended signal using  
oscilloscope math function.  
Voltage High  
Voltage Low  
VHigh  
VLow  
660  
1
mV  
-150  
150  
1
Max Voltage  
Min Voltage  
Crossing Voltage (abs)  
Vovs  
Vuds  
Vcross(abs)  
Measurement on single ended  
signal using absolute value.  
1150  
1
mV  
1
mV  
-300  
250  
550  
140  
1
Variation of crossing over all  
edges  
see Tperiod min-max values  
400MHz nominal  
Crossing Voltage (var)  
Long Accuracy  
d-Vcross  
ppm  
mV  
1
-300  
300  
ppm  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ps  
ps  
1,2  
2
2,3  
2
2,3  
2
2,3  
2
2,3  
2
2,3  
2
2,3  
2
2,3  
1,2  
1,2  
1,2  
1,2  
1,2  
1,2  
1,2  
1
2.4993  
2.4993  
2.9991  
2.9991  
3.7489  
3.7489  
4.9985  
4.9985  
5.9982  
5.9982  
7.4978  
7.4978  
9.9970  
9.9970  
2.4143  
2.9141  
3.6639  
4.8735  
5.8732  
7.3728  
9.8720  
175  
2.5008  
2.5133  
3.0009  
3.016  
3.7511  
3.77  
5.0015  
5.0266  
6.0018  
6.0320  
7.5023  
5.4000  
10.0030  
10.0533  
400MHz spread  
333.33MHz nominal  
333.33MHz spread  
266.66MHz nominal  
266.66MHz spread  
200MHz nominal  
200MHz spread  
166.66MHz nominal  
166.66MHz spread  
133.33MHz nominal  
133.33MHz spread  
100.00MHz nominal  
100.00MHz spread  
Average period  
Tperiod  
400MHz nominal/spread  
333.33MHz nominal/spread  
266.66MHz nominal/spread  
200MHz nominal/spread  
166.66MHz nominal/spread  
133.33MHz nominal/spread  
100.00MHz nominal/spread  
VOL = 0.175V, VOH = 0.525V  
VOH = 0.525V VOL = 0.175V  
Absolute min period  
Tabsmin  
Rise Time  
Fall Time  
tr  
700  
700  
125  
125  
tf  
175  
1
Rise Time Variation  
Fall Time Variation  
d-tr  
d-tf  
ps  
ps  
1
1
Measurement from differential  
wavefrom  
Duty Cycle  
Skew  
dt3  
45  
55  
85  
50  
%
ps  
ps  
1
1
1
tsk3  
VT = 50%  
Measurement from differential  
wavefrom f not equal 266 MHz  
Measurement from differential  
wavefrom f = 266 MHz  
Jitter, Cycle to cycle  
tjcyc-cyc  
85  
ps  
1
1Guaranteed by design and characterization, not 100% tested in production.  
2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at  
14.31818MHz or 25 MHz  
3 Figures are for down spread.  
0863C—11/22/04  
6
Integrated  
Circuit  
ICS9FG107  
Systems, Inc.  
Electrical Characteristics - PCICLK/PCICLK_F  
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 30 pF (unless otherwise specified)  
PARAMETER  
Long Accuracy  
SYMBOL  
ppm  
CONDITIONS  
MIN  
-300  
TYP  
MAX  
300  
UNITS  
ppm  
ns  
ns  
ns  
Notes  
1,2  
2
2
2
see Tperiod min-max values  
33.33MHz output nominal  
33.33MHz output spread  
33.33MHz output nominal  
33.33MHz output spread  
29.99100  
29.99100  
29.49100  
29.49100  
12  
30.00900  
30.15980  
30.50900  
30.65980  
N/A  
Clock period  
Tperiod  
Tabs  
Absolute Min/Max Clock  
period  
ns  
2
Clk High Time  
Clock Low Time  
th1  
tl1  
ns  
1
12  
N/A  
ns  
1
Output High Voltage  
Output Low Voltage  
VOH  
VOL  
IOH = -1 mA  
IOL = 1 mA  
2.4  
-33  
30  
V
0.55  
-33  
38  
V
V
OH @MIN = 1.0 V  
OH@ MAX = 3.135 V  
OL @ MIN = 1.95 V  
mA  
mA  
mA  
mA  
Output High Current  
Output Low Current  
IOH  
IOL  
V
V
V
OL @ MAX = 0.4 V  
Rising edge rate  
Falling edge rate  
Edge Rate  
Edge Rate  
Rise Time  
Fall Time  
Duty Cycle  
Skew  
1
1
4
4
V/ns  
V/ns  
ns  
1
1
1
1
1
1
1
tr1  
tf1  
VOL = 0.4 V, VOH = 2.4 V  
VOH = 2.4 V, VOL = 0.4 V  
VT = 1.5 V  
0.5  
0.5  
45  
1.4  
1.4  
2
2
ns  
dt1  
55  
500  
250  
%
tsk1  
VT = 1.5 V  
ps  
Jitter  
tjcyc-cyc  
VT = 1.5 V  
ps  
1Guaranteed by design, not 100% tested in production.  
2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at  
14.31818MHz or 25 MHz  
Electrical Characteristics - REF-14.318/25 MHz  
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified)  
SYMBO  
PARAMETER  
Long Accuracy  
Clock period  
CONDITIONS  
MIN  
TYP  
0
MAX UNITS Notes  
L
ppm  
see Tperiod min-max values  
14.318MHz output nominal  
25.000MHz output nominal  
IOH = -1 mA  
-300  
300  
ppm  
1
1,2  
1,2  
1
69.8270 69.8413 69.8550 ns  
39.9880 40.0000 40.0120 ns  
Tperiod  
Output High Voltage  
Output Low Voltage  
VOH  
VOL  
2.4  
V
V
IOL = 1 mA  
0.4  
-23  
1
VOH @MIN = 1.0 V,  
Output High Current  
Output Low Current  
IOH  
IOL  
-29  
29  
mA  
mA  
1
1
V
OH@MAX = 3.135 V  
VOL @MIN = 1.95 V,  
OL @MAX = 0.4 V  
27  
V
Rise Time  
Fall Time  
Duty Cycle  
Jitter  
tr1  
tf1  
VOL = 0.4 V, VOH = 2.4 V  
VOH = 2.4 V, VOL = 0.4 V  
VT = 1.5 V  
1
1
1.6  
1.6  
2
2
ns  
ns  
%
1
1
1
1
dt1  
45  
55  
250  
tjcyc-cyc  
VT = 1.5 V  
160  
ps  
1Guaranteed by design and characterization, not 100% tested in production.  
2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818 or 25.00 MHz  
0863C—11/22/04  
7
Integrated  
Circuit  
ICS9FG107  
Systems, Inc.  
General SMBus serial interface information for the ICS9FG107  
How to Write:  
How to Read:  
• Controller (host) sends a start bit.  
• Controller (host) sends the write address DC(H)  
• ICS clock will acknowledge  
• Controller (host) will send start bit.  
• Controller (host) sends the write address DC(H)  
• ICS clock will acknowledge  
• Controller (host) sends the begining byte location = N  
• ICS clock will acknowledge  
• Controller (host) sends the begining byte  
location = N  
• Controller (host) sends the data byte count = X  
• ICS clock will acknowledge  
• Controller (host) starts sending Byte N through  
Byte N + X -1  
• ICS clock will acknowledge  
• Controller (host) will send a separate start bit.  
• Controller (host) sends the read address DD(H)  
• ICS clock will acknowledge  
(see Note 2)  
• ICS clock will send the data byte count = X  
• ICS clock sends Byte N + X -1  
• ICS clock will acknowledge each byte one at a time  
• ICS clock sends Byte 0 through byte X (if X(H)  
was written to byte 8).  
• Controller (host) sends a Stop bit  
• Controller (host) will need to acknowledge each byte  
• Controllor (host) will send a not acknowledge bit  
• Controller (host) will send a stop bit  
Index Block Read Operation  
Index Block Write Operation  
Controller (Host)  
ICS (Slave/Receiver)  
Controller (Host)  
ICS (Slave/Receiver)  
T
starT bit  
starT bit  
T
Slave Address DC(H)  
Slave Address DC(H)  
WR  
WRite  
WR  
WRite  
Beginning Byte = N  
Data Byte Count = X  
Beginning Byte N  
ACK  
ACK  
ACK  
ACK  
ACK  
ACK  
Beginning Byte = N  
RT  
Repeat starT  
Slave Address DD(H)  
RD  
ReaD  
ACK  
Data Byte Count = X  
Beginning Byte N  
ACK  
ACK  
Byte N + X - 1  
ACK  
P
stoP bit  
Byte N + X - 1  
N
P
Not acknowledge  
stoP bit  
0863C—11/22/04  
8
Integrated  
Circuit  
ICS9FG107  
Systems, Inc.  
I2C Table: Device Control Register, READ/WRITE ADDRESS (DC/DD)  
Control  
Byte 0  
Pin #  
Name  
Type  
0
1
PWD  
Function  
FS31  
FS21  
FS11  
FS01  
27  
5
RW  
RW  
RW  
RW  
RW  
Pin 27  
Pin 5  
Pin 44  
Pin 7  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
See Frequency  
Selection Table, Page 1  
44  
7
26  
Spread Enable1  
Off  
On  
Pin 26  
Enable Software Control of  
Frequency, Spread Enable and  
Spread Type  
Hardware  
Select  
Software  
Select  
-
RW  
0
Bit 2  
DIF_STOP# drive mode  
DWNSPRD#1  
RW  
RW  
Driven  
Down  
Hi-Z  
Center  
0
Bit 1  
Bit 0  
45  
Pin 45  
Notes:  
1. These bits reflect the latched state of the corresponding pins at power up, but may be written to  
if Byte 0, bit 2 is set to '1'. FS3 is the SEL14M_25M# pin.  
I2C Table: Output Enable Register  
Control  
Byte 1  
Pin #  
Name  
Type  
0
1
PWD  
Function  
8
PCICLK0  
DIF_6  
DIF_5  
DIF_4  
DIF_3  
DIF_2  
DIF_1  
DIF_0  
Output Enable  
Output Enable  
Output Enable  
Output Enable  
Output Enable  
Output Enable  
Output Enable  
Output Enable  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
Stop Low  
Disable  
Disable  
Disable  
Disable  
Disable  
Disable  
Disable  
Enable  
Enable  
Enable  
Enable  
Enable  
Enable  
Enable  
Enable  
1
1
1
1
1
1
1
1
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
12,13  
17,18  
20,21  
30,29  
33,32  
39,38  
42,41  
I2C Table: Output Stop Mode Register  
Control  
Function  
Byte 2  
Pin #  
Name  
Type  
0
1
PWD  
9
PCICLK1  
DIF_6  
DIF_5  
DIF_4  
DIF_3  
DIF_2  
DIF_1  
DIF_0  
Output Enable  
Stop Mode  
Stop Mode  
Stop Mode  
Stop Mode  
Stop Mode  
Stop Mode  
Stop Mode  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
Stop Low  
Free-run  
Free-run  
Free-run  
Free-run  
Free-run  
Free-run  
Free-run  
Enable  
1
0
0
0
0
0
0
0
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
12,13  
17,18  
20,21  
30,29  
33,32  
39,38  
42,41  
Stop-able  
Stop-able  
Stop-able  
Stop-able  
Stop-able  
Stop-able  
Stop-able  
0863C—11/22/04  
9
Integrated  
Circuit  
ICS9FG107  
Systems, Inc.  
I2C Table: Frequency Select Readback Register  
Control  
Function  
Byte 3  
Pin #  
Name  
Type  
0
1
PWD  
SEL14M_25M#1  
(FS3)  
27  
State of pin 27  
R
Pin 27  
Bit 7  
See Frequency  
Selection Table, Page 1  
FS21  
FS11  
5
State of pin 6  
State of pin 44  
R
R
Pin 5  
Bit 6  
Bit 5  
44  
Pin 44  
FS01  
7
State of pin 7  
State of pin 26  
RESERVED  
RESERVED  
State of pin 45  
R
R
R
R
R
Pin 7  
Pin 26  
X
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
SPREAD1  
26  
Off  
RESERVED  
RESERVED  
Down Center  
On  
X
DWNSPRD1  
45  
Pin 45  
Notes:  
1. These read-only bits always reflect the latched state of the corresponding pins at power up.  
I2C Table: Vendor & Revision ID Register  
Control  
Byte 4  
Pin #  
Name  
Type  
0
1
PWD  
Function  
-
-
-
-
-
-
-
-
RID3  
RID2  
RID1  
RID0  
VID3  
VID2  
VID1  
VID0  
R
R
R
R
R
R
R
R
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
0
0
0
0
0
0
1
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
REVISION ID  
VENDOR ID  
I2C Table: DEVICE ID  
Byte 5  
Control  
Function  
Pin #  
Name  
Type  
0
1
PWD  
-
-
-
-
-
-
-
-
R
R
R
R
R
R
R
R
RESERVED  
RESERVED  
RESERVED  
RESERVED  
RESERVED  
RESERVED  
RESERVED  
RESERVED  
0
0
0
0
0
1
1
1
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Device ID = 07 Hex  
Bit 7 is MSB  
0863C—11/22/04  
10  
Integrated  
Circuit  
ICS9FG107  
Systems, Inc.  
I2C Table: Byte Count Register  
Control  
Function  
Byte 6  
Pin #  
Name  
Type  
0
1
PWD  
Writing to this  
register will  
configure how  
many bytes  
will be read  
back, default  
-
-
-
-
-
-
-
-
BC7  
BC6  
BC5  
BC4  
BC3  
BC2  
BC1  
BC0  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
0
0
0
0
1
1
1
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
is 07 = 7  
bytes.  
0863C—11/22/04  
11  
Integrated  
Circuit  
ICS9FG107  
Systems, Inc.  
DIF_STOP# - Assertion (transition from '1' to '0')  
Asserting DIF_STOP# pin stops all DIF outputs that are set to be stoppable after their next transition. When the I2C  
DIF_STOP tri-state bit corresponding to the DIF output of interest is programmed to a '0', DIF output will stop DIF_True =  
HIGH and DIF_Complement = LOW. When the I2C DIF_STOP tri-state bit corresponding to the DIF output of interest is  
programmed to a '1', DIFoutputs will be tri-stated.  
DIF_STOP#  
DIF  
DIF#  
DIF_STOP# - De-assertion (transition from '0' to '1')  
With the de-assertion of DIF_STOP# all stopped DIF outputs will resume without a glitch. The maximum latency from the  
de-assertion to active outputs is 2 - 6 DIF clock periods. If the control register tristate bit corresponding to the output of  
interest is programmed to '1', then the stopped DIF outputs will be driven High within 10nS of DIF_Stop# de-assertion to a  
voltage greater than 200mV.  
DIF_Stop#  
DIF  
DIF#  
DIF Internal  
Tdrive_DIF_Stop, 10nS >200mV  
0863C—11/22/04  
12  
Integrated  
Circuit  
ICS9FG107  
Systems, Inc.  
c
In Millimeters  
In Inches  
N
SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS  
MIN  
2.41  
0.20  
0.20  
0.13  
MAX  
2.80  
0.40  
0.34  
0.25  
MIN  
.095  
.008  
.008  
.005  
MAX  
.110  
.016  
.0135  
.010  
L
A
A1  
b
E1  
E
INDEX  
AREA  
c
D
E
E1  
e
SEE VARIATIONS  
SEE VARIATIONS  
10.03  
7.40  
10.68  
7.60  
.395  
.291  
.420  
.299  
1
2
α
h x 45°  
D
0.635 BASIC  
0.025 BASIC  
h
L
0.38  
0.50  
0.64  
1.02  
.015  
.020  
.025  
.040  
N
α
SEE VARIATIONS  
SEE VARIATIONS  
A
0°  
8°  
0°  
8°  
A1  
- C -  
VARIATIONS  
D mm.  
D (inch)  
e
SEEAATTIINNGG  
PLANE  
N
b
MIN  
15.75  
MAX  
16.00  
MIN  
.620  
MAX  
.10 (.004)  
C
48  
.630  
Reference Doc.: JEDEC Publication 95, MO-118  
10-0034  
Ordering Information  
ICS9FG107yFLFT  
Example:  
ICS XXXX y F Lx T  
Designation for tape and reel packaging  
LeadOption(optional)  
LF = Lead Free  
LN = Lead Free Annealed  
Package Type  
F = SSOP  
Revision Designator (will not correlate with datasheet revision)  
Device Type (consists of 3 or 4 digit numbers)  
Prefix  
ICS, AV = Standard Device  
0863C—11/22/04  
13  
Integrated  
Circuit  
ICS9FG107  
Systems, Inc.  
48-Lead, 6.10 mm. Body, 0.50 mm. Pitch TSSOP  
(240 mil) (20 mil)  
In Millimeters  
COMMON DIMENSIONS  
c
N
In Inches  
COMMON DIMENSIONS  
L
SYMBOL  
MIN  
--  
0.05  
0.80  
0.17  
0.09  
MAX  
1.20  
0.15  
1.05  
0.27  
0.20  
MIN  
--  
.002  
.032  
.007  
.0035  
MAX  
.047  
.006  
.041  
.011  
.008  
E1  
E
A
A1  
A2  
b
INDEX  
AREA  
c
1
2
D
E
E1  
e
L
SEE VARIATIONS  
8.10 BASIC  
SEE VARIATIONS  
0.319 BASIC  
a
6.00  
6.20  
.236  
.244  
0.020 BASIC  
.030  
SEE VARIATIONS  
D
0.50 BASIC  
0.45  
0.75  
.018  
N
SEE VARIATIONS  
a
aaa  
0°  
--  
8°  
0.10  
0°  
--  
8°  
.004  
A
A2  
A1  
VARIATIONS  
- CC --  
D mm.  
D (inch)  
N
MIN  
12.40  
MAX  
12.60  
MIN  
.488  
MAX  
.496  
e
SEATING  
PLANE  
48  
b
aaa  
C
Reference Doc.: JEDEC Publication 95, MO-153  
10-0039  
Ordering Information  
ICS9FG107yGLFT  
Example:  
ICS XXXX y G Lx T  
Designation for tape and reel packaging  
LeadOption(optional)  
LF = Lead Free  
LN = Lead Free Annealed  
Package Type  
G = TSSOP  
Revision Designator (will not correlate with datasheet revision)  
Device Type (consists of 3 or 4 digit numbers)  
Prefix  
ICS, AV = Standard Device  
0863C—11/22/04  
14  

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