ICSLV810RILF [ICSI]
Buffer/Clock Driver; 缓冲器/时钟驱动器
| 型号： | ICSLV810RILF |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Buffer/Clock Driver |
| 文件： | 总12页 (文件大小：244K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICSLV810
Buffer/Clock Driver
Description
Features
The ICSLV810 is a low skew 1.5 V to 2.5 V, 1:10 fanout
buffer. This device is specifically designed for data
communications clock management. The large fanout
from a single input line reduces loading on the input
clock. The TTL level outputs reduce noise levels on the
part. Typical applications are clock and signal
distribution.
• Packaged in 20-pin QSOP/SSOP
• Split 1:10 fanout Buffer
• Maximum skew between outputs of different
packages 0.75 ns
• Max propagation delay of 3.8 ns
• Operating voltage of 1.5 V to 2.5 V on Bank A
• Operating voltage of 1.5 V to 2.5 V on Banks B and C
• Advanced, low power, CMOS process
• Industrial temperature range -40° C to +85° C
• 3.3 V tolerant input when VDDA=2.5 V
• Available in Pb (lead) free packaging
Block Diagram
VDDA
CLK 1
CLK 2
CLK 3
CLK 4
CLK 5
CLKIN
CLK 6
CLK 7
CLK 8
CLK 9
CLK 10
VDDB
VDDC
MDS LV810 F
1
Revision 101305
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICSLV810
Buffer/Clock Driver
Pin Assignment
1
2
3
4
5
20
19
18
17
16
15
14
13
12
11
CLKIN
GND
VDDB
CLK 10
CLK 9
GND
CLK 1
VDDA
CLK 2
GND
CLK 8
VDDC
CLK 7
GND
6
7
CLK 3
VDDA
CLK 4
GND
8
9
CLK 6
CLK 5
10
20 pin (150mil) SSOP
Pin Descriptions
Pin
Number
Pin
Name
Pin
Type
Pin Description
1
2
CLKIN
GND
Input
Clock input.
Power
Connect to ground.
3
CLK1
VDDA
CLK2
GND
Output Clock output.
4
Power
Connect to +1.5 - +2.5 V.
5
Output Clock output.
6
Power
Connect to ground.
7
CLK3
VDDA
CLK4
GND
Output Clock output.
8
Power
Connect to +1.5 - +2.5 V.
9
Output Clock output.
10
11
12
13
14
15
16
17
18
19
20
Power
Connect to ground.
CLK5
CLK6
GND
Output Clock output.
Output Clock output.
Power
Connect to ground.
CLK7
VDDC
CLK8
GND
Output Clock output.
Power
Connect to +1.5 - 2.5 V.
Output Clock output.
Power
Connect to ground.
CLK9
CLK10
VDDB
Output Clock output.
Output Clock output.
Power
Connect to +1.5 - 2.5 V.
MDS LV810 F
2
Revision 101305
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICSLV810
Buffer/Clock Driver
with the clock line, as close to the clock output pin as
possible. The nominal impedance of the clock output is
20Ω.
External Components
The ICSLV810 requires a minimum number of external
components for proper operation.
PCB Layout Recommendations
Decoupling Capacitors
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
Decoupling capacitors of 0.01µF must be connected
between VDD and GND, as close to these pins as
possible. For optimum device performance, the
decoupling capacitors should be mounted on the
component side of the PCB. Avoid the use of vias in the
decoupling circuit.
1) The 0.01µF decoupling capacitors should be
mounted on the component side of the board as close
to the VDD pins as possible. No vias should be used
between the decoupling capacitors and VDD pins. The
PCB trace to VDD pin should be kept as short as
possible, as should the PCB trace to the ground via.
Series Termination Resistor
When the PCB trace between the clock outputs and the
loads are over 1 inch, series termination should be
used. To series terminate a 50Ω trace (a commonly
used trace impedance) place a 33Ω resistor in series
2) To minimize EMI the 33Ω series termination resistor,
if needed, should be placed close to the clock output.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICSLV810. These ratings,
which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of
the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Item
Rating
Supply Voltage, VDD MAX
All Inputs and Outputs
7 V
-0.5 V to VDDA + 1.2 V
-40 to +85°C
-65 to +150°C
125°C
Ambient Operating Temperature
Storage Temperature
Junction Temperature
Soldering Temperature
260°C
Recommended Operation Conditions
Parameter
Min.
-40
Typ.
Max.
+85
Units
Ambient Operating Temperature
°C
V
Power Supply Voltage (measured with respect to GND), VDDA
Power Supply Voltage (measured with respect to GND), VDDB
Power Supply Voltage (measured with respect to GND), VDDC
1.425
1.425
1.425
2.625
2.625
2.625
V
V
MDS LV810 F
3
Revision 101305
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICSLV810
Buffer/Clock Driver
DC Electrical Characteristics—CLKIN and Bank A
VDDA = 2.5 V, Ambient Temperature -40° C to +85° C
Parameter
Symbol
VDDA
Conditions
Min.
Typ.
Max. Units
Operating Voltage
1.425
2.625
V
Quiescent Power Supply
Current
IDDA
No Load
F = 40 MHz
15
80
mA
mA
V
Short Circuit Current
IOS
CLK 1 - 5
Input High Voltage,
CLKIN
Guaranteed
Logic Level
High
1.6
1.8
V
IH
Input Low Voltage,
CLKIN
V
Guaranteed
Logic Level Low
0.8
0.4
V
V
V
IL
IOH = -7 mA
IOL =12 mA
Output High Voltage
V
VIN = VIH or
VIL
OH
Output Low Voltage
V
VIN = VIH or
VIL
OL
Input High Current
Input Low Current
Input High Current
IIH
VDD = max
VDD = max
VDD = max
VIN = 2.4 V
VIN = 0.5 V
1
µA
µA
µA
IIL
II
-1
20
VIN = VDD
(max)
Input Capacitance
Output Capacitance
CIN
VIN = 0V, Note1
5
6.0
8.0
pF
pF
COUT
V
= 0V,
5.5
OUT
Note1
Note1: This parameter is not tested, guaranteed by design.
DC Electrical Characteristics—Bank B
VDDB = 2.5 V, Ambient Temperature -40° C to +85° C, unless otherwise noted
Parameter
Symbol
VDDB
IDDB
Conditions
Min.
Typ.
Max.
Units
Operating Voltage
1.425
2.625
V
Quiescent Power
Supply Current
VDDB = 2.5 V
No Load
7
3
mA
mA
F = 40 MHz
VDDB = 1.5 V
No Load
F = 40 MHz
Short Circuit
Current
IOS
VDDB = 1.5 V
VDDB = 2.5 V
CLK8-10
CLK8-10
35
80
mA
mA
MDS LV810 F
4
Revision 101305
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICSLV810
Buffer/Clock Driver
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
IOH = -7 mA
IOH = -7 mA
IOL =12 mA
IOL =12 mA
Output High Voltage
V
VDDB = 1.5 V
VIN = VIH or VIL
1.1
V
OH
VDDB = 2.5 V
VIN = VIH or VIL
1.8
V
V
V
Output Low Voltage
V
VDDB = 1.5 V
VIN = VIH or VIL
0.42
0.4
OL
VDDB = 2.5 V
VIN = VIH or VIL
Input High Current
Input Low Current
Input High Current
IIH
VDDB = max
VDDB = max
1
µA
µA
µA
IIL
II
-1
20
VDDB = max,
VIN = VDD (max)
Input Capacitance
Output Capacitance
CIN
VIN = 0V, Note1
5
6.0
8.0
pF
pF
COUT
V
= 0V,
5.5
OUT
Note 1
Note1: This parameter is not tested, guaranteed by design.
DC Electrical Characteristics—Bank C
VDDC = 2.5 V, Ambient Temperature -40° C to +85° C, unless otherwise noted
Parameter
Symbol
VDDC
IDDC
Conditions
Min.
Typ.
Max.
Units
Operating Voltage
1.425
2.625
V
Quiescent Power
Supply Current
VDDC = 2.5 V
No Load
3
2
mA
mA
F = 40 MHz
VDDC = 1.5 V
No Load
F = 40 MHz
Short Circuit Current
Output High Voltage
IOS
VDDC = 1.5 V
VDDC = 2.5 V
CLK6-7
CLK6-7
35
80
mA
mA
V
IOH = -7 mA
V
VDDC = 1.5 V
VIN = VIH or VIL
1.1
1.8
OH
IOH = -7 mA
IOL =12 mA
IOL =12 mA
VDDC = 2.5 V
VIN = VIH or VIL
V
V
V
Output Low Voltage
V
VDDC = 1.5 V
VIN = VIH or VIL
0.42
0.4
OL
VDDC = 2.5 V
VIN = VIH or VIL
Input High Current
Input Low Current
IIH
IIL
VDDC = max
VDDC = max
1
µA
µA
-1
MDS LV810 F
5
Revision 101305
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICSLV810
Buffer/Clock Driver
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Input High Current
VDDC = max,
VIN = VDD (max)
20
µA
II
Input Capacitance
Output Capacitance
CIN
VIN = 0V, Note1
5
6.0
8.0
pF
pF
COUT
V
= 0V,
5.5
OUT
Note 1
Note1: This parameter is not tested, guaranteed by design.
AC Electrical Characteristics—Bank A
VDDA = 2.5 V, Ambient Temperature -40° C to +85° C
Parameter
Symbol
Conditions
Min.
Typ. Max. Units
Output Skew: skew between
outputs of same package
tSK(0)
CL = 3 pF,
RL = 500Ω
Figure 3
-200
-200
1.5
200
200
3.5
ps
ps
ns
ps
Pulse Skew: skew between
opposite transitions of same
output (tPLH-tPHL)
tSK(P)
CL = 3 pF,
RL = 500Ω
Figure 4
Propagation Delay
tpLH / tpHL CL = 3 pF,
RL = 500Ω
2.6
Figure 2
Part to Part Skew
tSK(t)
CL = 3 pF,
RL = 500Ω
Figure 5
-650
650
Output Rise Time
20% to 80%
tr(o)
tf(o)
CL = 3 pF,
RL = 500Ω
0.8
0.8
ns
ns
Output Fall Time
80% to 20%
CL = 3 pF,
RL = 500Ω
Additive Jitter
t
All Outputs
50
55
ps
%
J
Duty Cycle
DC
CL = 3 pF,
45
Measured at VDD/2
RL = 500Ω
Duty Cycle, VDDA=1.8V
Output Frequency Range
DC
40
1
50
60
%
133
MHz
MDS LV810 F
6
Revision 101305
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICSLV810
Buffer/Clock Driver
AC Electrical Characteristics—Bank B
VDDB = 2.5 V, Ambient Temperature -40° C to +85° C, unless otherwise noted
Parameter
Symbol
Conditions
Min.
Typ. Max. Units
Output Skew: skew between
outputs of same package
tSK(0)
CL = 3 pF, RL = 500Ω
Figure 3
-200
200
ps
Pulse Skew: skew between
opposite transitions of same
output (tPLH-tPHL)
tSK(P)
CL = 3 pF, RL = 500Ω
Figure 4
-200
200
ps
Propagation Delay
Part to Part Skew
tpLH / tpHL CL = 3 pF, RL = 500Ω,
VDDB = 1.5 V
5.5
2.6
ns
ns
ns
ps
Figure 2
CL = 3 pF, RL = 500Ω,
VDDB = 2.5 V
Figure 2
1.5
-1
3.5
1
CL = 3 pF, RL = 500Ω
VDDB = 1.5 V
Figure 5
CL = 3 pF, RL = 500Ω
VDDB = 2.5 V
Figure 5
-650
650
Output Rise Time
20% to 80%
tr(o)
tf(o)
CL = 3 pF, RL = 500Ω
VDDB = 1.5 V
1.0
0.8
1.0
0.8
ns
ns
ns
ns
ps
ps
%
CL = 3 pF, RL = 500Ω
VDDB = 2.5 V
Output Fall Time
80% to 20%
CL = 3 pF, RL = 500Ω
VDDB = 1.5 V
CL = 3 pF, RL = 500Ω
VDDB = 2.5 V
Additive Jitter
t
All Outputs,
VDDB = 1.5 V
34
50
55
J
All Outputs,
VDDB = 2.5 V
Duty Cycle
Measured at VDD/2
DC
DC
CL = 3 pF,
RL = 500Ω
45
Duty Cycle, VDDB = 1.8V
Output Frequency Range
40
1
50
60
%
133
MHz
MDS LV810 F
7
Revision 101305
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICSLV810
Buffer/Clock Driver
AC Electrical Characteristics—Bank C
VDDC = 2.5 V, Ambient Temperature -40° C to +85° C, unless otherwise noted
Parameter
Symbol
Conditions
Min.
Typ. Max. Units
Output Skew: skew between
outputs of same package
tSK(0)
CL = 3 pF, RL = 500Ω
Figure 3
-200
200
ps
Pulse Skew: skew between
opposite transitions of same
output (tPLH-tPHL)
tSK(P)
CL = 3 pF, RL = 500Ω
Figure 4
-200
200
ps
Propagation Delay
tpLH / tpHL
CL = 3 pF, RL = 500Ω,
VDDC = 1.5 V
Figure 2
5.5
2.6
ns
ns
ns
ps
CL = 3 pF, RL = 500Ω,
VDDC = 2.5 V
Figure 2
1.5
-1
3.5
1
Part to Part Skew
CL = 3 pF, RL = 500Ω
VDDC = 1.5 V
Figure 5
CL = 3 pF, RL = 500Ω
VDDC = 2.5 V
Figure 5
-650
650
Output Rise Time
20% to 80%
tr(o)
tf(o)
CL = 3 pF, RL = 500Ω
VDDC = 1.5 V
1.0
0.8
1.0
0.8
ns
ns
ns
ns
ps
ps
%
CL = 3 pF, RL = 500Ω
VDDC = 2.5 V
Output Fall Time
80% to 20%
CL = 3 pF, RL = 500Ω
VDDC = 1.5 V
CL = 3 pF, RL = 500Ω
VDDC = 2.5 V
Additive Jitter
t
All Outputs,
VDDC = 1.5 V
34
50
55
J
All Outputs,
VDDC = 2.5 V
Duty Cycle
Measured at VDD/2
DC
DC
CL = 3 pF,
RL = 500Ω
45
Duty Cycle, VDDC=1.8V
Output Frequency Range
40
1
50
60
%
133
MHz
MDS LV810 F
8
Revision 101305
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICSLV810
Buffer/Clock Driver
Thermal Characteristics for 20QSOP
Parameter
Symbol
Conditions
Min.
Min.
Typ. Max. Units
Thermal Resistance Junction to
Ambient
θ
θ
θ
Still air
135
93
°C/W
°C/W
°C/W
°C/W
JA
JA
JA
JC
1 m/s air flow
3 m/s air flow
78
Thermal Resistance Junction to Case
θ
60
Thermal Characteristics for 20SOIC
Parameter
Symbol
Conditions
Still air
Typ. Max. Units
Thermal Resistance Junction to
Ambient
θ
θ
θ
83
71
58
46
°C/W
°C/W
°C/W
°C/W
JA
JA
JA
JC
1 m/s air flow
3 m/s air flow
Thermal Resistance Junction to Case
θ
From Output
Under Test
500 ohm
CL=3pF
Figure 1. Load Circuit
VIH
VIL
Input
Input
tPLH
tPHL
tPLH1
tPHL1
VOH
VOL
VOH
VOL
Output
Output 1
Figure 2. Propagation Delay
Figure 4. Pulse Skew ( tSK(p)=|tpLH – tpH| )
Input
Input
tPLH1
tPHL1
tPLH1
tPHL1
VOH
VOH
Package
1 Output
Output 1
tSK
tSK
VOL
VOH
VOL
VOH
tSK
tSK
Package
2 Output
Output 2
VOL
VOL
tPLH2
( tSK(O)=|tPLH2-tPHL2| or |tPLH1-tPHL1| )
Figure 5. Part-to-Part Skew
tPHL2
tPLH2
( tSK(O)=|tPLH2-tPHL2| or |tPLH1-tPHL1| )
Figure 3. Output Skew
tPHL2
MDS LV810 F
9
Revision 101305
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICSLV810
Buffer/Clock Driver
Package Outline and Package Dimensions (20-pin QSOP, 150 Mil. Body)
Package dimensions are kept current with JEDEC Publication No. 95
Millimeters
Inches*
Min
20
Symbol
A
Min
Max
1.75
0.25
1.50
0.30
0.25
8.75
6.20
4.00
Max
.069
.010
.059
0.012
.010
.344
.244
.157
1.35
0.10
--
.053
.0040
--
A1
A2
b
C
D
E
E1
e
E1
E
INDEX
AREA
0.20
0.18
8.55
5.80
3.80
0.008
.007
.337
.228
.150
1
2
0.635 Basic
0.025 Basic
D
L
α
0.40
0°
1.27
8°
.016
.050
0°
8°
*For reference only. Controlling dimensions in mm.
A
2
A
A
1
c
- C -
e
SEATING
PLANE
b
L
.10 (.004)
C
MDS LV810 F
10
Revision 101305
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICSLV810
Buffer/Clock Driver
Package Outline and Package Dimensions (20-pin SSOP, 209 Mil. Body)
Package dimensions are kept current with JEDEC Publication No. 95
20
Millimeters
Inches*
Symbol
Min
Max
2.00
—
Min
Max
.079
—
A
A1
A2
b
—
—
0.05
1.65
0.22
0.09
6.90
7.40
5.00
.002
.065
0.009
.0035
.271
.291
.197
E1
E
1.85
0.38
0.25
7.50
8.20
5.60
.073
0.015
.010
.295
.323
.220
INDEX
AREA
c
D
E
E1
e
1
2
0.65 Basic
0.0256 Basic
D
L
0.55
0.95
.022
.037
α
0°
8°
0°
8°
*For reference only. Controlling dimensions in mm.
A
2
A
A
1
c
- C -
e
SEATING
PLANE
b
L
.10 (.004)
C
Ordering Information
Part / Order Number
ICSLV810RI
Marking
ICSLV810RI
Shipping Packaging
Tubes
Package
Temperature
-40 to +85° C
-40 to +85° C
-40 to +85° C
-40 to +85° C
-40 to +85° C
-40 to +85° C
-40 to +85° C
-40 to +85° C
20-pin QSOP
20-pin QSOP
20-pin SSOP
20-pin SSOP
20-pin QSOP
20-pin QSOP
20-pin SSOP
20-pin SSOP
ICSLV810RIT
ICSLV810RI
ICSLV810FI
ICSLV810FI
LV810RILF
LV810RILF
LV810FILF
LV810FILF
Tape and Reel
Tubes
ICSLV810FI
ICSLV810FIT
Tape and Reel
Tubes
ICSLV810RILF
ICSLV810RILFT
ICSLV810FILF
ICSLV810FILFT
Tape and Reel
Tubes
Tape and Reel
Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no
responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other
circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as
those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without
additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant
any ICS product for use in life support devices or critical medical instruments.
MDS LV810 F
11
Revision 101305
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICSLV810
Buffer/Clock Driver
Revision History
Rev. Originator
Date
Description of Change
A
B
P.Griffith
P.Griffith
03/25/05 New device/datasheet.
05/02/05 Released from Preliminary to final; changed Short Circuit Current parameter in 2.5 V DC
Char table to 80 mA; changed Short Circuit Current parameter in 1.5 V DC Char table to
35 mA
C
P.Griffith
05/12/05 Added bullet in “Features” for operating voltage of 2.5 V on Bank A and specified that
operating voltages of 1.5 and 2.5 V are on Banks B and C; changed block diagram input
and pin 1 from IN to CLKIN; removed +1.5 V spec from pin 4 and pin 8 descriptions; added
“VDDA + 1.2 V” to “All Inputs and Outputs” section of Absolute Maximum Ratings; added
min and max values for Banks A, B, and C “Power Supply Voltage” in Recommended
Operating Conditions; expanded DC Electrical Char tables in to include a separate table
for Banks A, B, and C; expanded AC Electrical Char tables in to include a separate table
for Banks A, B, and C;
D
E
P.Griffith
06/21/05 Added 209 mil 20-pin SSOP package and ordering info.
K. Beckmeyer 07/27/05 Specified operating voltage on Bank A from 1.5V to 2.5V; Added figures 4 and 5 on page
10 to explain Pulse Skew and Part-to-Part Skew; Changed Output Frequency Max
Specification to 133MHz in AC Electrical Char tables for Banks A, B, and C; Added Duty
Cycle Spec for VDD = 1.5V in AC Electrical Char tables for Banks A, B, C; Changed CLK
conditions in DC Electrical Char tables on Banks B and C; removed SOIC package.
F
K. Beckmeyer 10/13/05 Added “LF” packaging and ordering info to both “R” and”F” packages.
MDS LV810 F
12
Revision 101305
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
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SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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