ICSSSTVA16859BK-T [ICSI]
DDR 13-Bit to 26-Bit Registered Buffer; DDR 13位至26位寄存缓冲器
| 型号： | ICSSSTVA16859BK-T |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | DDR 13-Bit to 26-Bit Registered Buffer |
| 文件： | 总11页 (文件大小：130K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICSSSTVA16859B
Integrated
Circuit
Systems,Inc.
DDR 13-Bit to 26-Bit Registered Buffer
Recommended Applications:
Pin Configurations
• DDR Memory Modules:
Q13A
Q12A
Q11A
Q10A
Q9A
VDDQ
GND
Q8A
Q7A
Q6A
Q5A
Q4A
Q3A
Q2A
GND
Q1A
Q13B
VDDQ
Q12B
Q11B
Q10B
Q9B
1
2
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
VDDQ
GND
D13
- DDRI (PC1600, PC2100)
- DDR333 (PC2700)
3
4
5
6
7
8
9
D12
- DDRI-400 (PC3200)
VDD
VDDQ
GND
D11
D10
D9
GND
D8
D7
RESET#
GND
CLK#
CLK
VDDQ
VDD
VREF
D6
• Provides complete DDR DIMM solution with
ICS93V857 or ICS95V857
• SSTL_2 compatible data registers
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Product Features:
• Differential clock signals
• Meets SSTL_2 signal data
• Supports SSTL_2 class I specifications on outputs
• Low-voltage operation
- VDD = 2.3V to 2.7V
• Available in 64 pin TSSOP and 56 pin MLF packages
• Exceeds SSTVN16859 performance
GND
D5
D4
Q8B
Q7B
Q6B
GND
VDDQ
Q5B
Q4B
Q3B
Truth Table1
D3
GND
VDDQ
VDD
D2
D1
GND
VDDQ
Inputs
CLK
X or
Q Outputs
Q
RESET#
CLK#
D
X or
X or
L
L
Q2B
Q1B
Floating Floating Floating
H
H
↑
↑
↓
↓
H
L
H
L
Q0(2)
64-Pin TSSOP
6.10 mm. Body, 0.50 mm. pitch
H
L or H
L or H
X
Notes:
1.
H = "High" Signal Level
L = "Low" Signal Level
56
43
↑ = Transition "Low"-to-"High"
↓ = Transition "High"-to-"Low"
X = Don't Care
1
Q7A
Q6A
Q5A
Q4A
Q3A
42
D10
D9
D8
2.
Output level before the indicated steady state
input conditions were established.
D7
RESET#
GND
CLK#
CLK
VDDQ
VDD
VREF
D6
Block Diagram
Q2A
Q1A
ICSSSTVA16859B
Q13B
VDDQ
Q12B
Q11B
Q10B
Q9B
CLK
CLK#
RESET#
R
Q1A
Q1B
CLK
D1
VREF
D5
29
D4
D1
14
Q8B
15
28
To 12 Other Channels
56-Pin VFQFN (MLF2)
1050A—01/07/05
ICSSSTVA16859B
General Description
The 13-bit-to-26-bit ICSSSTVA16859B is a universal bus driver designed for 2.3V to 2.7V VDD operation and SSTL_2
I/O levels, except for the LVCMOS RESET# input.
Data flow from D to Q is controlled by the differential clock (CLK/CLK#) and a control signal (RESET#). The positive
edge of CLK is used to trigger the data flow and CLK# is used to maintain sufficient noise margins where as RESET#,
an LVCMOS asynchronous signal, is intended for use at the time of power-up only. ICSSSTVA16859B supports low-
power standby operation. A logic level “Low” at RESET# assures that all internal registers and outputs (Q) are reset
to the logic “Low” state, and all input receivers, data (D) and clock (CLK/CLK#) are switched off. Please note that
RESET# must always be supported with LVCMOS levels at a valid logic state because VREF may not be stable during
power-up.
To ensure that outputs are at a defined logic state before a stable clock has been supplied, RESET# must be held
at a logic “Low” level during power up.
In the DDR DIMM application, RESET# is specified to be completely asynchronous with respect to CLK and CLK#.
Therefore, no timing relationship can be guaranteed between the two signals.When entering a low-power standby state,
the register will be cleared and the outputs will be driven to a logic “Low” level quickly relative to the time to disable
the differential input receivers.This ensures there are no glitches on the output. However, when coming out of low-power
standby state, the register will become active quickly relative to the time to enable the differential input receivers. When
the data inputs are at a logic level “Low” and the clock is stable during the “Low”-to-”High” transition of RESET# until
the input receivers are fully enabled, the design ensures that the outputs will remain at a logic “Low” level.
Pin Configuration (64-Pin TSSOP)
PIN NUMBER
PIN NAME
TYPE
DESCRIPTION
1-5, 8-14, 16, 17, 19-25, 28-32
Q (13:1)
OUTPUT
Data output
Ground
7, 15, 26, 34, 39, 43, 50, 54,
58, 63
GND
VDDQ
D (13:1)
PWR
PWR
6, 18, 27, 33, 38, 47, 59, 64
Output supply voltage, 2.5V nominal
Data input
35, 36, 40-42, 44, 52, 53, 55-
57, 61, 62
INPUT
48
49
CLK
CLK#
INPUT
INPUT
PWR
Positive master clock input
Negative master clock input
Core supply voltage, 2.5V nominal
Reset (active low)
37, 46, 60
51
VDD
RESET#
VREF
INPUT
INPUT
45
Input reference voltage, 2.5V nominal
Pin Configuration (56-Pin MLF2)
PIN NUMBER
PIN NAME
Q (13:1)
GND
TYPE
OUTPUT
PWR
DESCRIPTION
Data output
1-8, 10-16, 18-22, 50-54, 56
37, 48
Ground
9, 17, 23, 27, 34, 44, 49, 55
VDDQ
PWR
Output supply voltage, 2.5V nominal
Data input
24, 25, 28-31, 39-43, 46, 47
D (13:1)
CLK
INPUT
INPUT
INPUT
PWR
35
36
Positive master clock input
Negative master clock input
Core supply voltage, 2.5V nominal
Reset (active low)
CLK#
26, 33, 45
38
VDD
RESET#
VREF
INPUT
INPUT
PWR
32
Input reference voltage, 2.5V nominal
Ground (MLF2 package only)
-
Center PAD
1050A—01/07/05
ICSSSTVA16859B
Absolute Maximum Ratings
Notes:
Storage Temperature . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 3.6V
Input Voltage1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to VDD +0.5
Output Voltage1,2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to VDDQ +0.5
Input Clamp Current . . . . . . . . . . . . . . . . . . . . 50 mA
Output Clamp Current . . . . . . . . . . . . . . . . . . . 50 mA
Continuous Output Current. . . . . . . . . . . . . . . 50 mA
VDD, VDDQ or GND Current/Pin . . . . . . . . . . . 100 mA
1. The input and output negative voltage
ratings may be excluded if the input
andoutputclampratingsareobserved.
2. This current will flow only when the
output is in the high state level
V0 >VDDQ
.
3. The package thermal impedance is
calculated in accordance with
JESD 51.
Package Thermal Impedance3 . . . . . . . . . . . . . . . 55°C/W
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of the device at these or any other conditions above those
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Recommended Operating Conditions - DDRI/DDR333 (PC1600, PC2100, PC2700)
DESCRIPTION
PARAMETER
MIN
TYP
MAX
UNITS
Supply Voltage
VDD
2.3
2.5
2.7
I/O Supply Voltage
VDDQ
VREF
2.3
2.5
2.7
Reference Voltage
1.15
1.25
VREF
1.35
Termination Voltage
Input Voltage
VTT
VREF - 0.04
0
VREF + 0.04
VDDQ
VI
VIH (DC)
VIH (AC)
VIL (DC)
VIL (DC)
VIH
DC Input High Voltage
AC Input High Voltage
DC Input Low Voltage
AC Input Low Voltage
Input High Voltage Level
Input Low Voltage Level
Common mode Input Range
Differential Input Voltage
VREF + 0.15
VREF + 0.31
Data Inputs
V
VREF - 0.15
VREF - 0.31
1.7
RESET#
VIL
0.7
VICR
0.97
0.36
1.53
CLK, CLK#
VID
Cross Point Voltage of Differential Clock
Pair
VIX
(VDDQ/2) - 0.2
(VDDQ/2) + 0.2
High-Level Output Current
Low-Level Output Current
Operating Free-Air Temperature
IOH
IOL
TA
-16
16
70
mA
°C
0
1Guaranteed by design, not 100% tested in production.
1050A—01/07/05
ICSSSTVA16859B
Recommended Operating Conditions - DDRI-400 (PC3200)
DESCRIPTION
PARAMETER
MIN
TYP
2.6
MAX
2.7
UNITS
Supply Voltage
VDD
2.5
I/O Supply Voltage
VDDQ
VREF
2.5
2.6
2.7
Reference Voltage
1.25
1.3
1.35
Termination Voltage
Input Voltage
VTT
VREF - 0.04
0
VREF
VREF + 0.04
VDDQ
VI
VIH (DC)
VIH (AC)
VIL (DC)
VIL (DC)
VIH
DC Input High Voltage
AC Input High Voltage
DC Input Low Voltage
AC Input Low Voltage
Input High Voltage Level
Input Low Voltage Level
Common mode Input Range
Differential Input Voltage
VREF + 0.15
VREF + 0.31
Data Inputs
V
VREF - 0.15
VREF - 0.31
1.7
RESET#
VIL
0.7
VICR
0.97
0.36
1.53
CLK, CLK#
VID
Cross Point Voltage of Differential Clock
Pair
VIX
(VDDQ/2) - 0.2
(VDDQ/2) + 0.2
High-Level Output Current
Low-Level Output Current
Operating Free-Air Temperature
IOH
IOL
TA
-16
16
70
mA
°C
0
1Guaranteed by design, not 100% tested in production.
1050A—01/07/05
ICSSSTVA16859B
DC Electrical Characteristics - DDRI/DDR333 (PC1600, PC2100, PC2700)
TA = 0 - 70°C; VDD = 2.5 +/-0.2V, VDDQ=2.5 +/-0.2V; (unless otherwise stated)
CONDITIONS
VDDQ
2.3V
SYMBOL
VIK
PARAMETERS
MIN
TYP
MAX
-1.2
UNITS
V
II = -18mA
VDDQ
0.2
1.95
-
IOH = -100µA
2.3V-2.7V
VOH
I
OH = -8mA
2.3V
2.3V-2.7V
2.3V
IOL = 100µA
0.2
0.35
5
VOL
II
IOL = 8mA
VI = VDD or GND
RESET# = GND
VI = VIH(AC) or VIL(AC)
All Inputs
Standby (Static)
2.7V
µA
µA
0.01
,
IDD
Operating (Static)
TBD
TBD
mA
RESET# = VDD
RESET# = VDD
,
VI
Dynamic operating
(clock only)
= VIH(AC) or VIL(AC), CLK
µ/clock MHz
and CLK# switching 50%
duty cycle.
IO = 0
2.7V
RESET# = VDD
,
VI
IDDD
= VIH(AC) or VIL (AC), CLK
Dynamic Operating
(per each data input)
µA/ clock
MHz/data
and CLK# switching 50%
duty cycle. One data input
switching at half clock
TBD
frequency, 50% duty cycle
I
OH = -16mA
rOH
rOL
Output High
Output Low
[rOH - rOL] each
2.3V-2.7V
2.3V-2.7V
7
7
13.5
13
20
20
Ω
Ω
IOL = 16mA
IO = 20mA, TA = 25° C
rO(D)
2.5V
2.5V
4
Ω
separate bit
Data Inputs
CLK and CLK#
VI = VREF 350mV
VICR = 1.25V, VI(PP) = 360mV
2.5
2.5
3.5
3.5
Ci
pF
Notes:
1 - Guaranteed by design, not 100% tested in production.
1050A—01/07/05
ICSSSTVA16859B
DC Electrical Characteristics - DDRI-400 (PC3200)
TA = 0 - 70°C; VDD = 2.5 +/-0.2V, VDDQ=2.5 +/-0.2V; (unless otherwise stated)
CONDITIONS
VDDQ
2.5V
SYMBOL
VIK
PARAMETERS
MIN
TYP
MAX
-1.2
UNITS
V
II = -18mA
VDDQ
0.2
1.95
-
I
OH = -100µA
2.5V-2.7V
VOH
IOH = -8mA
2.7V
2.5V-2.7V
2.5V
IOL = 100µA
0.2
0.35
5
VOL
II
IOL = 8mA
VI = VDD or GND
RESET# = GND
VI = VIH(AC) or VIL(AC)
All Inputs
Standby (Static)
2.7V
µA
µA
0.01
,
IDD
Operating (Static)
TBD
TBD
mA
RESET# = VDD
RESET# = VDD
,
VI
Dynamic operating
(clock only)
= VIH(AC) or VIL(AC), CLK
µ/clock MHz
and CLK# switching 50%
duty cycle.
IO = 0
2.7V
RESET# = VDD
= VIH(AC) or VIL (AC), CLK
,
VI
IDDD
Dynamic Operating
(per each data input)
µA/ clock
MHz/data
and CLK# switching 50%
duty cycle. One data input
switching at half clock
TBD
frequency, 50% duty cycle
I
OH = -16mA
rOH
rOL
Output High
Output Low
[rOH - rOL] each
separate bit
Data Inputs
2.5V-2.7V
2.5V-2.7V
7
7
13.5
13
20
20
Ω
Ω
IOL = 16mA
IO = 20mA, TA = 25° C
rO(D)
2.6V
2.6V
4
Ω
VI = VREF 350mV
VICR = 1.25V, VI(PP) = 360mV
2.5
2.5
3.5
3.5
Ci
pF
CLK and CLK#
Notes:
1 - Guaranteed by design, not 100% tested in production.
1050A—01/07/05
ICSSSTVA16859B
Timing Requirements1
(over recommended operating free-air temperature range, unless otherwise noted)
V
DDQ = 2.5V 0.2V
MIN
SYMBOL
PARAMETERS
UNITS
MAX
fclock
tSL
Clock frequency
270
4
MHz
V/ns
ns
ns
ns
Output slew rate
1
Setup time, fast slew rate 2 & 4
Setup time, slow slew rate 3 & 4
Hold time, fast slew rate 2 & 4
Hold time, slow slew rate 3 & 4
0.4
0.6
0.4
0.5
↑ ↓
Data before CLK , CLK#
tS
↑ ↓
Data after CLK , CLK#
Th
ns
1 - Guaranteed by design, not 100% tested in production.
Notes:
2 - For data signal input slew rate of ≥ 1V/ns.
3 - For data signal input slew rate of ≥ 0.5V/ns and < 1V/ns.
4 - CLK, CLK# signals input slew rate of ≥ 1V/ns.
Switching Characteristics - DDRI/DDR333 (PC1600, PC2100, PC2700)
(over recommended operating free-air temperature range, unless otherwise noted) (see Figure 1)
From
(Input)
To
(Output)
VDD = 2.5V 0.2V
SYMBOL
fmax
UNITS
MIN
210
1.6
TYP
MAX
MHz
ns
ns
CLK, CLK# (TSSOP)
CLK, CLK# (VFQFN[MLF2])
RESET#
Q
Q
Q
2.1
2.1
2.6
2.6
3.5
tPD
1.6
tphl
ns
Switching Characteristics - DDRI-400 (PC3200)
(over recommended operating free-air temperature range, unless otherwise noted) (see Figure 1)
From
(Input)
To
(Output)
VDD = 2.6V 0.1V
SYMBOL
UNITS
MIN
210
1.1
TYP
MAX
fmax
tPD
tPDSS
tPD
MHz
ns
ns
ns
ns
Q
Q
Q
Q
1.65
1.9
(VFQFN[MLF2])
CLK, CLK# (TSSOP)
RESET#
1.1
1.6
1.85
3.5
tphl
1050A—01/07/05
ICSSSTVA16859B
VDD
1kΩ
From Output
Under Test
Test point
1kΩ
CL = 30 pF
(see Note 1)
Load Circuit
LVCMOS
RESET#
Input
VDDQ
0 V
tact
IDDH
V
DDQ/2
VDDQ/2
VI(pp)
Timing
Input
VICR
VICR
tinact
tPHL
tPHL
IDD
(see note 2)
90%
10%
VOH
VOL
IDDL
VTT
VTT
Voltage and Current Waveforms
Inputs Active and Inactive Times
Output
Voltage Waveforms - Propagation Delay Times
tw
VIH
VIL
Input
VREF
VREF
Voltage Waveforms - Pulse Duration
LVCMOS
RESET#
Input
VIH
VIL
VI(pp)
VDD/2
Timing
Input
VICR
tPHL
VOH
VOL
Output
th
tS
VTT
Voltage Waveforms - Propagation Delay Times
VIH
VIL
VREF
Input
VREF
Voltage Waveforms - Setup and Hold Times
Figure 1 - Parameter Measurement Information (V
= 2.5V 0.2V)
DDQ
Notes: 1. CL incluces probe and jig capacitance.
2. IDD tested with clock and data inputs held at VDDQ or GND, and IO = 0 mA.
3. All input pulses are supplied by generators having the following characteristics: PRR @10 MHz,
Zo=50Ω, input slew rate = 1 V/ns 20% (unless otherwise specified).
4. The outputs are measured one at a time with one transition per measurement.
5. VTT = VREF = VDDQ/2
6. VIH = VREF + 310mV (AC voltage levels) for differential inputs. VIH = VDDQ for LVCMOS input.
7. VIL = VREF - 310mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS input.
8. tPLH and tPHL are the same as tpd
1050A—01/07/05
ICSSSTVA16859B
c
In Millimeters
In Inches
N
SYMBOL
COMMON DIMENSIONS COMMON DIMENSIONS
MIN
--
0.05
0.80
0.17
0.09
MAX
1.20
0.15
1.05
0.27
0.20
MIN
--
.002
.032
.007
.0035
MAX
.047
.006
.041
.011
.008
L
A
A1
A2
b
E1
E
INDEX
AREA
c
D
E
SEE VARIATIONS
8.10 BASIC
SEE VARIATIONS
0.319 BASIC
1
2
E1
e
6.00
6.20
.236
0.020 BASIC
.244
a
D
0.50 BASIC
L
0.45
0.75
.018
.030
N
SEE VARIATIONS
SEE VARIATIONS
0°
--
8°
0.10
0°
--
8°
.004
α
aaa
A
A2
A1
VARIATIONS
- CC --
D mm.
D (inch)
N
e
SEATING
PLANE
MIN
MAX
17.10
MIN
.665
MAX
.673
b
64
16.90
aaa
C
Ref erence Doc.: JEDEC Publication 95, M O-153
10 - 0 0 3 9
6.10 mm. Body, 0.50 mm. pitch TSSOP
(0.020 mil)
(240 mil)
Ordering Information
ICSSSTVA16859BG(LF)-T
Example:
ICS XXXX y G (LF) - T
Designation for tape and reel packaging
Lead Free (optional)
Package Type
G = TSSOP
Revision Designator
DeviceType (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
1050A—01/07/05
ICSSSTVA16859B
Symbol
Common Dimensions
A
A1
A2
A3
D
-
0.00
-
0.85
1.00
0.05
0.80
0.01
0.65
0.20 BSC
8.00 BSC
7.75 BSC
8.00 BSC
7.75 BSC
D1
E
56 pin MLF2
E1
Θ
12
P
0.24
0.13
0.42
0.17
0.60
0.23
R
Pitch Varation D
e
N
0.50 BSC
56
Nd
Ne
L
14
14
0.30
0.18
0.00
4.35
5.05
0.40
0.23
0.20
4.50
5.20
0.50
0.30
0.45
4.65
5.35
Ordering Information
b
Q
ICSSSTVA16859BK(LF)-T
Example:
D2
E2
ICS XXXX y K (LF) - T
Designation for tape and reel packaging
Lead Free (optional)
Package Type
K = MLF
Revision Designator
DeviceType (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
1050A—01/07/05
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Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
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