IS42LS32400A-7BI_技术文档

IS42S81600A, IS42LS81600A

IS42S16800A, IS42LS16800A

IS42S32400A, IS42LS32400A

®

ISSI

16Meg x 8, 8Meg x16 & 4Meg x 32

128-MBIT SYNCHRONOUS DRAM

ADVANCED INFORMATION

AUGUST 2002

OVERVIEW

FEATURES

ISSI's 128Mb Synchronous DRAM achieves high-speed

data transfer using pipeline architecture. All inputs and

outputs signals refer to the rising edge of the clock

input.The 128Mb SDARM is organized as follows.

• Clock frequency: 133 100, MHz

• Fully synchronous; all signals referenced to a

positive clock edge

• Internal bank for hiding row access/precharge

• Power supply

V^DD

VDDQ

IS42LS81600A

IS42S81600A

4M x8x4 Banks

54pin TSOPII

IS42LS16800A

IS42S16800A

IS42LS32400A

IS42S32400A

IS42LS81600A

IS42LS16800A

2.5V 1.8V (2.5V tolerant)

2M x16x4 Banks 2M x16x4 Banks

IS42LS32400A

IS42S81600A

2.5V 1.8V (2.5V tolerant)

3.3V 3.3V

54ballFBGA

90ballFBGA

86pin TSOPII

54 pin TSOPII

IS42S16800A

IS42S32400A

3.3V 3.3V

• LVTTL interface

• Programmable burst length

– (1, 2, 4, 8, full page)

KEY TIMING PARAMETERS

• Programmable burst sequence:

Sequential/Interleave

Parameter

-7

-10 Unit

Clk Cycle Time

CAS Latency = 3

CAS Latency = 2

• Extended Mode Register

7

10

ns

• Programmable Power Reduction Feature by

partial array activation during Self-Refresh

Clk Frequency

CAS Latency = 3

CAS Latency = 2

133

100

Mhz

• Auto Refresh (CBR)

• Temp. Compensated Self Refresh.

• Self Refresh with programmable refresh periods

• 4096 refresh cycles every 64 ms

Access Time from Clock

CAS Latency = 3

5.4

6

7

9

ns

CAS Latency = 2

Row to Column Delay Time (tRCD)

Row Precharge Tim (tRP)

15

18

ns

• Random column address every clock cycle

• Programmable CAS latency (2, 3 clocks)

• Burst read/write and burst read/single write

operations capability

• Burst termination by burst stop and precharge

command

• Industrial Temperature Availability

time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are

advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

ADVANCEDINFORMATION,Rev. 00A

1

08/01/02

®

IS42S81600A, IS42S16800A, IS42S32400A

IS42LS81600A, IS42LS16800A, IS42LS32400A

ISSI

DEVICE OVERVIEW

to hide precharge time and the capability to randomly

changecolumnaddressesoneachclockcycleduringburst

access.

The 128Mb SDRAM is a high speed CMOS, dynamic

random-access memory designed to operate in 2.5V VDD

and1.8VVDDQ or 3.3VDD and3.3VVDDQ memorysystems

containing 134,217 ,728 bits. Internally configured as a

quad-bank DRAM with a synchronous interface. Each

16,777,216-bit bank is organized as 4,096 rows by 256

columns by 16 bits.

A self-timed row precharge initiated at the end of the burst

sequence is available with the AUTO PRECHARGE func-

tionenabled. Prechargeonebankwhileaccessingoneofthe

otherthreebankswillhidetheprechargecyclesandprovide

seamless,high-speed,random-accessoperation.

The128MbSDRAMincludesanAUTOREFRESHMODE,

and a power-saving, power-down mode. All signals are

registeredonthepositiveedgeoftheclocksignal,CLK. All

inputs and outputs are LVTTL compatible.

SDRAMreadandwriteaccessesareburstorientedstartingat

aselectedlocationandcontinuingforaprogrammednum-

ber of locations in a programmed sequence. The registra-

tionofanACTIVEcommandbeginsaccesses, followedby

a READ or WRITE command. The ACTIVE command in

conjunction with address bits registered are used to select

the bank and row to be accessed (BA0, BA1 select the

bank; A0-A11 select the row). The READ or WRITE

commands in conjunction with address bits registered are

used to select the starting column location for the burst

access.

Only partials of the memory array can be selected for Self-

Refresh and the refresh period during Self-Refresh is

progammable in 4 steps which drastically reduces the self

refresh current, depending on the case temperature of the

components in the system application.

The 128Mb SDRAM has the ability to synchronously burst

data at a high data rate with automatic column-address

generation,theabilitytointerleavebetweeninternalbanks

ProgrammableREADorWRITEburstlengthsconsistof1,

2, 4 and 8 locations or full page, with a burst terminate

option.

FUNCTIONAL BLOCK DIAGRAM

CLK

CKE

CS

RAS

CAS

WE

DQM

DATA IN

BUFFER

COMMAND

DECODER

&

CLOCK

GENERATOR

16

REFRESH

CONTROLLER

MODE

REGISTER

I/O 0-15

A11

11

Vcc/Vcc

Q

SELF

DATA OUT

BUFFER

REFRESH

GND/GNDQ

A10

CONTROLLER

16

A9

A8

A7

A6

REFRESH

COUNTER

A5

A4

4096

A3

A2

A1

A0

BA0

BA1

4096

MEMORY CELL

ARRAY

4096

11

BANK 0

ROW

ADDRESS

LATCH

ROW

ADDRESS

BUFFER

11

SENSE AMP I/O GATE

256K

(x 16)

COLUMN

ADDRESS LATCH

BANK CONTROL LOGIC

8

BURST COUNTER

COLUMN DECODER

COLUMN

ADDRESS BUFFER

8

2

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

ADVANCEDINFORMATION Rev. 00A

06/01/02

®

IS42S81600A, IS42S16800A, IS42S32400A

IS42LS81600A, IS42LS16800A, IS42LS32400A

ISSI

PIN CONFIGURATIONS

54 pin TSOP - Type II for x8

V

DD

1

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

VSS

I/O0

2

I/O7

V

DD

Q

3

VSSQ

NC

4

NC

I/O6

I/O1

5

V

SS

Q

6

VDDQ

NC

I/O2

7

NC

I/O5

8

V

DD

Q

9

VSSQ

NC

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

NC

I/O4

I/O3

V

SS

Q

VDDQ

NC

V

DD

NC

WE

V

SS

NC

DQM

CLK

CKE

NC

A11

A9

CAS

RAS

CS

BA0

BA1

A10

A0

A8

A7

A1

A6

A2

A5

A3

A4

V

DD

VSS

PIN DESCRIPTIONS

A0-A11

A0-A8, A10

BA0, BA1

I/O0 to I/O7

CLK

Row Address Input

WE

WriteEnable

Column Address Input

Bank Select Address

Data I/O

DQM

VDD

x 8 Lower Bye, Input/Output Mask

Power

Vss

VDDQ

VssQ

NC

Ground

System Clock Input

Clock Enable

Power Supply for I/O Pin

Ground for I/O Pin

NoConnection

CKE

CS

Chip Select

RAS

RowAddressStrobeCommand

ColumnAddressStrobeCommand

CAS

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

ADVANCEDINFORMATION Rev. 00A

3

06/01/02

®

IS42S81600A, IS42S16800A, IS42S32400A

IS42LS81600A, IS42LS16800A, IS42LS32400A

ISSI

PIN CONFIGURATIONS

54-Ball FBGA for x16

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

Vss

I/O14

I/O12

I/O10

I/O8

I/O15

I/O13

I/O11

I/O9

NC

VssQ

VDDQ

VssQ

VDDQ

Vss

VDDQ

VssQ

VDDQ

VssQ

VDD

CAS

BA0

I/O0

I/O2

I/O4

I/O6

LDQM

RAS

BA1

A1

VDD

I/O1

I/O3

I/O5

I/O7

WE

UDQM

NC/A12

A8

CLK

A11

A7

CKE

A9

G

H

J

CS

A6

A0

A10

Vss

A5

A4

A3

A2

PIN DESCRIPTIONS

A0-A11

A0-A8, A10

BA0, BA1

DQ0 to DQ15

CLK

Row Address Input

Column Address Input

Bank Select Address

Data I/O

WE

WriteEnable

LDQM

UDQM

VDD

x16 Lower Bye, Input/Output Mask

x16 Upper Bye, Input/Output Mask

Power

System Clock Input

Clock Enable

Vss

Ground

CKE

VDDQ

VssQ

NC

Power Supply for I/O Pin

Ground for I/O Pin

CS

Chip Select

RAS

RowAddressStrobeCommand

ColumnAddressStrobeCommand

NoConnection

CAS

4

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

ADVANCEDINFORMATION Rev. 00A

06/01/02

®

IS42S81600A, IS42S16800A, IS42S32400A

IS42LS81600A, IS42LS16800A, IS42LS32400A

ISSI

PIN CONFIGURATIONS

54 pin TSOP - Type II for x16

V

DD

1

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

VSS

I/O0

2

I/O15

V

DD

Q

3

VSSQ

I/O1

I/O2

4

I/O14

I/O13

5

V

SS

Q

6

VDDQ

I/O3

I/O4

7

I/O12

I/O11

8

V

DD

Q

9

VSSQ

I/O5

I/O6

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

I/O10

I/O9

V

SS

Q

VDDQ

I/O7

I/O8

V

DD

VSS

LDQM

WE

CAS

RAS

CS

NC

UDQM

CLK

CKE

NC

A11

A9

BA0

BA1

A10

A0

A8

A7

A1

A6

A2

A5

A3

A4

V

DD

VSS

PIN DESCRIPTIONS

A0-A11

A0-A8, A10

BA0, BA1

I/O0 to I/O15

CLK

Row Address Input

WE

WriteEnable

Column Address Input

Bank Select Address

Data I/O

LDQM

UDQM

VDD

x16 Lower Bye, Input/Output Mask

x16 Upper Bye, Input/Output Mask

Power

System Clock Input

Clock Enable

Vss

Ground

CKE

VDDQ

VssQ

NC

Power Supply for I/O Pin

Ground for I/O Pin

CS

Chip Select

RAS

RowAddressStrobeCommand

ColumnAddressStrobeCommand

NoConnection

CAS

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

ADVANCEDINFORMATION Rev. 00A

5

06/01/02

®

IS42S81600A, IS42S16800A, IS42S32400A

IS42LS81600A, IS42LS16800A, IS42LS32400A

ISSI

PIN CONFIGURATIONS

90-Ball FBGA for x32

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

I/O26

I/O28

VssQ

VDDQ

Vss

I/O24

VDDQ

I/O27

I/O29

I/O31

DQM3

A5

Vss

VssQ

I/O25

I/O30

NC

VDD

VDDQ

I/O22

I/O17

NC

I/O23

Vss

I/O21

I/O19

VDDQ

Vss

I/O20

I/O18

I/O16

DQM2

A0

A3

A2

VDD

A1

G

H

J

A4

A6

A10

A7

A8

NC

NC/A12

BA0

BA1

CS

A11

CLK

CKE

NC

A9

RAS

K

L

DQM1

VDDQ

VssQ

I/O11

I/O13

NC

CAS

VDD

I/O6

WE

DQM0

VssQ

VDDQ

I/O4

I/O8

Vss

I/O7

I/O5

I/O3

VssQ

I/O0

M

N

P

R

I/O10

I/O12

VDDQ

I/O15

I/O9

I/O14

VssQ

Vss

I/O1

VDDQ

VDD

I/O2

PIN DESCRIPTIONS

WE

WriteEnable

A0-A11

A0-A8, A10

BA0, BA1

I/O0 to I/O31

CLK

Row Address Input

Column Address Input

Bank Select Address

Data I/O

DQM0-DQM3

VDD

x32 Input/Output Mask

Power

Vss

Ground

VDDQ

Power Supply for I/O Pin

Ground for I/O Pin

NoConnection

System Clock Input

Clock Enable

VssQ

CKE

NC

CS

Chip Select

RAS

RowAddressStrobeCommand

ColumnAddressStrobeCommand

CAS

6

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

ADVANCEDINFORMATION Rev. 00A

06/01/02

®

IS42S81600A, IS42S16800A, IS42S32400A

IS42LS81600A, IS42LS16800A, IS42LS32400A

ISSI

PIN CONFIGURATIONS

86 pin TSOP - Type II for x32

V

DD

1

86

85

84

83

82

81

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

VSS

I/O0

2

I/O15

V

DD

Q

3

VSSQ

I/O1

I/O2

4

I/O14

I/O13

5

V

SS

Q

6

VDDQ

I/O3

I/O4

7

I/O12

I/O11

8

V

DD

Q

9

VSSQ

I/O5

I/O6

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

I/O10

I/O9

V

SS

Q

VDDQ

I/O7

NC

I/O8

NC

V

DD

VSS

DQM0

WE

DQM1

NC

CAS

RAS

CS

NC

CLK

CKE

A9

A11

BA0

BA1

A10

A0

A8

A7

A6

A5

A1

A4

A2

A3

DQM2

DQM3

VDD

VSS

NC

I/O16

I/O31

V

SS

Q

VDDQ

I/O17

I/O18

I/O30

I/O29

V

DD

Q

VSSQ

I/O19

I/O20

I/O28

I/O27

V

SS

Q

VDDQ

I/O21

I/O22

I/O26

I/O25

V

DD

Q

VSSQ

I/O23

I/O24

V

DD

VSS

PIN DESCRIPTIONS

A0-A11

A0-A8, A10

BA0, BA1

I/O0 to I/O31

CLK

Row Address Input

WE

WriteEnable

Column Address Input

Bank Select Address

Data I/O

DQM0-DQM3

VDD

x32 Input/Output Mask

Power

Vss

Ground

System Clock Input

Clock Enable

VDDQ

Power Supply for I/O Pin

Ground for I/O Pin

NoConnection

CKE

VssQ

NC

CS

Chip Select

RAS

RowAddressStrobeCommand

ColumnAddressStrobeCommand

CAS

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

ADVANCEDINFORMATION Rev. 00A

7

06/01/02

®

IS42S81600A, IS42S16800A, IS42S32400A

IS42LS81600A, IS42LS16800A, IS42LS32400A

ISSI

PIN FUNCTIONS

Symbol

Type

Function (In Detail)

A0-A11

Input Pin

AddressInputs:A0-A11aresampledduringtheACTIVE

command(row-addressA0-A11)andREAD/WRITEcommand(A0-A7

with A10 defining auto precharge) to select one location out of the memory array

intherespectivebank.A10issampledduringaPRECHARGEcommandtodetermineif

all banks are to be precharged (A10 HIGH) or bank selected by

BA0, BA1 (LOW). The address inputs also provide the op-code during a LOAD MODE

REGISTERcommand.

BA0, BA1

CAS

Input Pin

BankSelectAddress:BA0andBA1defineswhichbanktheACTIVE, READ, WRITEor

PRECHARGEcommandisbeingapplied.

CAS, inconjunctionwiththeRASand WE, formsthedevicecommand. Seethe

"CommandTruthTable"fordetailsondevicecommands.

CKE

TheCKEinputdetermineswhethertheCLKinputisenabled. Thenextrisingedgeofthe

CLKsignalwillbevalidwhenisCKEHIGHandinvalidwhenLOW. WhenCKEisLOW,

the device will be in either power-down mode, clock suspend mode, or self refresh

mode. CKE is an asynchronous input.

CLK

Input Pin

CLK is the master clock input for this device. Except for CKE, all inputs to this device

areacquiredinsynchronizationwiththerisingedgeofthispin.

CS

TheCSinputdetermineswhethercommandinputisenabledwithinthedevice.

Command input is enabled whenCSisLOW, anddisabledwithCSisHIGH. Thedevice

remains in the previous state when CS is HIGH.

I/O0 to

I/O32

I/O Pin

I/O0 to I/O32 are I/O pins. I/O through these pins can be controlled in byte units

using the LDQM and UDQM pins.

LDQM,

UDQM

Input Pin

LDQM and UDQM control the lower and upper bytes of the I/O buffers. In read

mode, LDQM and UDQM control the output buffer. When LDQM or UDQM is LOW, the

correspondingbufferbyteisenabled, andwhenHIGH, disabled. Theoutputsgotothe

HIGH impedance state when LDQM/UDQM is HIGH. This function corresponds to OE

inconventionalDRAMs. Inwritemode, LDQMandUDQMcontroltheinputbuffer.

When LDQM or UDQM is LOW, the corresponding buffer byte is enabled, and data can

be written to the device. When LDQM or UDQM is HIGH, input data is masked and

cannot be written to the device.

DQM0-DQM3

DQM

Input Pin

RAS

RAS,inconjunctionwithCASandWE,formsthedevicecommand.Seethe"Command

TruthTable"itemfordetailsondevicecommands.

WE

Input Pin

WE,inconjunctionwithRASandCAS,formsthedevicecommand.Seethe"Command

TruthTable"itemfordetailsondevicecommands.

VDDQ

VDD

Power Supply Pin

VDDQ istheoutputbufferpowersupply.

VDD isthedeviceinternalpowersupply.

VSSQ istheoutputbufferground.

VSSQ

VSS

VSS isthedeviceinternalground.

8

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

ADVANCEDINFORMATION Rev. 00A

06/01/02

®

IS42S81600A, IS42S16800A, IS42S32400A

IS42LS81600A, IS42LS16800A, IS42LS32400A

ISSI

GENERAL DESCRIPTION

READ

The READ command selects the bank from BA0, BA1

inputs and starts a burst read access to an active row.

Inputs A0-A7 provides the starting column location. When

A10 is HIGH, this command functions as an AUTO

PRECHARGE command. When the auto precharge is

selected, therowbeingaccessedwillbeprechargedatthe

end of the READ burst. The row will remain open for

subsequent accesses when AUTO PRECHARGE is not

selected. DQ’s read data is subject to the logic level on the

DQM inputs two clocks earlier. When a given DQM signal

wasregisteredHIGH,thecorrespondingDQ’swillbeHigh-

Z two clocks later. DQ’s will provide valid data when the

DQM signal was registered LOW.

PRECHARGEfunctioninconjunctionwithaspecificREAD

orWRITEcommand. ForeachindividualREADorWRITE

command, auto precharge is either enabled or disabled.

AUTO PRECHARGE does not apply except in full-page

burstmode.UponcompletionoftheREADorWRITEburst,

a precharge of the bank/row that is addressed is automati-

callyperformed.

AUTO REFRESH COMMAND

This command executes the AUTO REFRESH operation.

The row address and bank to be refreshed are automatically

generatedduringthisoperation. Thestipulatedperiod(tRC)is

required for a single refresh operation, and no other com-

mandscanbeexecutedduringthisperiod. Thiscommandis

executed at least 4096 times for every 64ms. During an

AUTOREFRESHcommand,addressbitsare“Don’tCare”.

This command corresponds to CBR Auto-refresh.

WRITE

A burst write access to an active row is initiated with the

WRITE command. BA0, BA1 inputs selects the bank, and

the starting column location is provided by inputs A0-A7.

WhetherornotAUTO-PRECHARGEisusedisdetermined

by A10.

BURST TERMINATE

TheBURSTTERMINATEcommandforciblyterminatesthe

burst read and write operations by truncating either fixed-

length or full-page bursts and the most recently registered

READ or WRITE command prior to the BURST TERMI-

NATE.

Therowbeingaccessedwillbeprechargedattheendofthe

WRITE burst, if AUTO PRECHARGE is selected. If AUTO

PRECHARGE is not selected, the row will remain open for

subsequent accesses.

Amemoryarrayiswrittenwithcorrespondinginputdataon

DQ’sandDQMinputlogiclevelappearingatthesametime.

Data will be written to memory when DQM signal is LOW.

When DQM is HIGH, the corresponding data inputs will be

ignored, and a WRITE will not be executed to that byte/

column location.

COMMAND INHIBIT

COMMAND INHIBIT prevents new commands from being

executed. Operations in progress are not affected, apart

from whether the CLK signal is enabled

NO OPERATION

When CS is low, the NOP command prevents unwanted

commandsfrombeingregisteredduringidleorwaitstates.

PRECHARGE

ThePRECHARGEcommandisusedtodeactivatetheopen

row in a particular bank or the open row in all banks. BA0,

BA1canbeusedtoselectwhichbankisprechargedorthey

aretreatedas“Don’tCare”. A10determinedwhetheroneor

all banks are precharged. After executing this command,

the next command for the selected banks(s) is executed

afterpassageoftheperiodt_RP, whichistheperiodrequired

for bank precharging. Once a bank has been precharged,

itisintheidlestateandmustbeactivatedpriortoanyREAD

or WRITE commands being issued to that bank.

LOAD MODE REGISTER

During the LOAD MODE REGISTER command the mode

registerisloadedfromA0-A11. Thiscommandcanonlybe

issued when all banks are idle.

EXTENDED MODE REGISTER

The extended mode register defines low power functions.

During this command A0-A11 are data input pins. After

power on, the extended mode register set command must

be executed to fix low power functions. During tRSC

following this command, they can not accept any other

command.

AUTO PRECHARGE

TheAUTOPRECHARGEfunctionensuresthattheprecharge

is initiated at the earliest valid stage within a burst. This

functionallowsforindividual-bankprechargewithoutrequir-

ing an explicit command. A10 to enables the AUTO

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

ADVANCEDINFORMATION Rev. 00A

9

06/01/02

®

IS42S81600A, IS42S16800A, IS42S32400A

IS42LS81600A, IS42LS16800A, IS42LS32400A

ISSI

GENERAL DESCRIPTION Continued:

The extended mode register has four fields:

Options:A11-A7

Drive Strength: A6-A5

TemperatureCompensatedselfRefresh:A4-A3

Partial Array Self Refresh: A2-A0

Following extended mode register programming, no com-

mand can be issued before at least 2 CLK have elapsed.

ACTIVE COMMAND

When the ACTIVE COMMAND is activated, BA0, BA1

inputs selects a bank to be accessed, and the address

inputs on A0-A11 selects the row. Until a PRECHARGE

command is issued to the bank, the row remains open for

accesses.

10

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

ADVANCEDINFORMATION Rev. 00A

06/01/02

®

IS42S81600A, IS42S16800A, IS42S32400A

IS42LS81600A, IS42LS16800A, IS42LS32400A

ISSI

COMMAND TRUTH TABLE

CKE

A11

Function Symbol

Device deselect

Nooperation

Burst stop

n – 1

H

n

×

L

H

×

CS

H

L

RAS

×

CAS

WE

BA1

×

BA0

×

A10

A9 - A0

×

H

×

H

L

H

L

×

L

H

L

H

L

×

H

×

L

×

V

×

Read

H

L

V

×

V

×

Readwithautoprecharge

Write

H

L

H

L

H

L

Write with auto precharge

Bank activate

H

L

H

V

L

H

L

H

L

Precharge select bank

Precharge all banks

Mode register set

Extended mode reg set

H

L

H

L

H

L

×

H

×

L

V

H

×

L

H

L

Note: H=VIH, L=VIL x= VIH or VIL, V = Valid Data.

DQM TRUTH TABLE

CKE

DQM

U

Function Symbol

n-1

H

n

×

L

Data write / output enable

L

Data mask / output disable

H

×

L

Upper byte write enable / output enable

Lower byte write enable / output enable

Upper byte write inhibit / output disable

Lower byte write inhibit / output disable

H

L

H

×

H

×

H

×

Note: H=V^IH, L=VIL x= VIH or VIL, V = Valid Data.

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

ADVANCEDINFORMATION Rev. 00A

11

06/01/02

®

IS42S81600A, IS42S16800A, IS42S32400A

IS42LS81600A, IS42LS16800A, IS42LS32400A

ISSI

CKE TRUTH TABLE

CKE

CurrentState/Function

n – 1 n

CS

×

RAS

CAS WE

Address

Activating Clock suspend mode entry

Any Clock suspend mode

Clock suspend mode exit

Auto refresh command Idle

Self refresh entry Idle

H

L

×

L

×

H

×

L

×

L

H

L

×

H

L

×

L

×

Power down entry Idle

H

L

H

×

H

×

H

×

Deeppowerdownentry

Self refresh exit

H

L

H

L

×

L

H

L

H

×

H

×

H

×

Power down exit

L

H

L

H

×

H

×

H

×

Deeppowerdownexit

L

H

×

Note: H=VIH, L=VIL x= VIH or VIL, V = Valid Data.

12

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

ADVANCEDINFORMATION Rev. 00A

06/01/02

®

IS42S81600A, IS42S16800A, IS42S32400A

IS42LS81600A, IS42LS16800A, IS42LS32400A

ISSI

FUNCTIONAL TRUTH TABLE

CS

H

L

RAS CAS

WE

Address

Command

DESL

Action

Nop

Idle

X

H

L

X

H

L

H

L

X

NOP

Nop

L

X

BST

Nop

L

H

L

BA, CA, A10

A, CA, A10

BA, RA

A, A10

X

READ/READA

WRIT/WRITA

ACT

ILLEGAL ⁽²⁾

ILLEGAL⁽²⁾

L

H

L

H

L

Row activating

L

PRE/PALL

REF

Nop

L

H

L

Auto refresh

L

OC, BA1=L

OC, BA1=H

X

MRS

Mode register set

L

EMRS

Extended mode register set

Row Active

H

L

X

H

L

X

H

L

X

H

L

DESL

Nop

X

NOP

L

X

BST

(3)

L

H

L

BA, CA, A10

BA, RA

BA, A10

X

READ/READA

WRIT/WRITA

ACT

Begin read

(3)

L

Begin write

L

H

L

H

L

ILLEGAL ⁽²⁾

Precharge/Precharge all banks⁽

ILLEGAL

L

PRE/PALL

REF

L

H

L

OC, BA

X

MRS/EMRS

DESL

ILLEGAL

Read

H

X

Continue burst to end to

Row active

L

H

X

NOP

Continue burst to end Row

Row active

L

H

L

X

BST

Burst stop Row active

Terminate burst,

begin new read

H

BA, CA, A10

READ/READA

(5)

L

H

L

BA, CA, A10

WRIT/WRITA

Terminate burst,

begin write

(5, 6)

L

H

L

BA, RA

ACT

ILLEGAL ⁽²⁾

BA, A10

PRE/PALL

Terminate burst

Precharging

L

H

L

X

L

X

H

L

X

REF

ILLEGAL

OC, BA

X

MRS/EMRS

DESL

Write

X

Continue burst to end

Write recovering

L

H

X

NOP

Continue burst to end

Write recovering

L

H

L

X

BST

Burst stop Row active

H

BA, CA, A10

READ/READA

Terminate burst, start read :

Determine AP ^{(5, 6)}

L

H

L

BA, CA, A10

WRIT/WRITA

Terminate burst, new write :

Determine AP ⁽⁵⁾

L

H

L

H

L

BA,

RA ACT

PRE/PALL

REF

ILLEGAL ⁽²⁾

(7)

BA, A10

X

Terminate burst Precharging

ILLEGAL

H

L

OC, BA

MRS/EMRS

ILLEGAL

Note: H=VIH, L=VIL x= VIH or VIL, V = Valid Data, BA= Bank Address, CA+Column Address, RA=Row Address, OC= Op-Code

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

ADVANCEDINFORMATION Rev. 00A

13

06/01/02

®

IS42S81600A, IS42S16800A, IS42S32400A

IS42LS81600A, IS42LS16800A, IS42LS32400A

ISSI

FUNCTIONAL TRUTH TABLE Continued:

CS

RAS CAS

WE

Address

Command

Action

Read with auto

Precharging

H

×

DESL

Continue burst to end -

Precharge

L

H

x

NOP

Continue burst to end -

Precharging

L

H

L

H

L

×

BST

ILLEGAL

H

L

BA, CA, A10

BA, RA

BA, A10

×

READ/READA

WRIT/WRITA

ACT

ILLEGAL ⁽²⁾

ILLEGAL

L

H

L

H

L

PRE/PALL

REF

L

H

L

OC, BA

×

MRS/EMRS

DESL

ILLEGAL

Write with Auto

Precharge

×

Continue burst to end -Write

recovering with auto precharge

L

H

×

NOP

Continue burst to end -Write

recoveringwith auto precharge

L

H

L

H

L

H

L

H

L

×

BST

ILLEGAL

H

L

BA, CA, A10

READ/READA

WRIT/WRITA

ILLEGAL⁽²⁾

ILLEGAL ⁽²⁾

L

BA, CA, A10

H

L

H

L

BA, RA

L

BA, A10

PRE/PALL

REF

ILLEGAL ⁽²⁾

L

H

L

×

ILLEGAL

L

OC, BA

MRS/EMRS

DESL

ILLEGAL

Precharging

×

H

L

×

H

L

×

H

L

×

Nop Enter idle after tRP

ILLEGAL

ILLEGAL ⁽²⁾

×

NOP

×

BST

H

L

BA, CA, A10

BA, RA

BA, A10

×

READ/READA

WRIT/WRITA

ACT I

L

H

L

H

L

LLEGAL⁽²⁾

L

PRE/PALL

REF

Nop Enter idle after tRP

ILLEGAL

L

H

L

OC, BA

×

MRS/EMRS

DESL

ILLEGAL

Row Activating

×

H

L

×

H

L

×

H

L

Nop Enter bank active after tRCD

ILLEGAL

ILLEGAL ⁽²⁾

ILLEGAL ^(2,8)

ILLEGAL ⁽²⁾

×

NOP

×

BST

H

L

BA, CA, A10

BA, RA

BA, A10

×

READ/READA

WRIT/WRITA

ACT

L

H

L

H

L

PRE/PALL

REF

L

H

L

ILLEGAL

L

OC, BA

MRS/EMRS

ILLEGAL

Note: H=VIH, L=VIL x= VIH or VIL, V = Valid Data, BA= Bank Address, CA+Column Address, RA=Row Address, OC= Op-Code

14

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

ADVANCEDINFORMATION Rev. 00A

06/01/02

®

IS42S81600A, IS42S16800A, IS42S32400A

IS42LS81600A, IS42LS16800A, IS42LS32400A

ISSI

FUNCTIONAL TRUTH TABLE Continued:

CS

H

L

H

L

H

L

H

L

RAS CAS

WE

Address

Command

DESL

Action

Write Recovering

×

H

L

×

H

L

×

Nop Enter row active after tDPL

Begin read ⁽⁶⁾

H

L

×

NOP

×

BST

H

L

BA, CA, A10

READ/READA

WRIT/WRITA

ACT

L

BA, CA, A10

Begin new write

ILLEGAL ⁽²⁾

H

L

H

L

BA, RA

L

BA, A10

PRE/PALL

REF

L

H

L

×

ILLEGAL

L

OC, BA

MRS/EMRS

DESL

ILLEGAL

Write Recovering

with Auto

×

H

L

×

H

L

×

H

L

×

Nop Enter precharge after tDPL

Nop Enter row active after tDPL

ILLEGAL

ILLEGAL ^{(2, 6)}

ILLEGAL ⁽²⁾

×

NOP

Precharge

×

BST

H

L

BA, CA, A10

READ/READA

WRIT/WRITA

ACT

L

BA, CA, A10

H

L

H

L

BA, RA

L

BA, A10

PRE/PALL

REF

ILLEGAL ⁽²⁾

L

H

L

×

ILLEGAL

L

OC, BA

MRS/EMRS

DESL

ILLEGAL

Refresh

×

H

L

×

H

L

×

H

L

×

Enter idle after tRC1

Nop Enter idle after tRC1

ILLEGAL

×

NOP

×

BST

H

L

BA, CA, A10

BA, RA

BA, A10

×

EAD/READA

WRIT/WRITA

ACT

L

ILLEGAL

H

L

H

L

ILLEGAL

L

PRE/PALL

REF

ILLEGAL

L

H

L

ILLEGAL

L

OC, BA

×

MRS/EMRS

DESL

ILLEGAL

Mode Register

Accessing

×

H

L

×

H

L

×

H

L

Nop Enter idle after tRSC

ILLEGAL

×

NOP

×

BST

H

L

BA, CA, A10

BA, RA

BA, A10

×

READ/READA

WRIT/WRITA

ACT

L

ILLEGAL

H

L

H

L

ILLEGAL

L

PRE/PALL

REF

ILLEGAL

L

H

L

ILLEGAL

L

OC, BA

MRS/EMRS

ILLEGAL

Note: H=VIH, L=VIL x= VIH or VIL, V = Valid Data, BA= Bank Address, CA+Column Address, RA=Row Address, OC= Op-Code

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

ADVANCEDINFORMATION Rev. 00A

15

06/01/02

®

IS42S81600A, IS42S16800A, IS42S32400A

IS42LS81600A, IS42LS16800A, IS42LS32400A

ISSI

FUNCTIONAL TRUTH TABLE Continued:

Notes:

1. All entries assume that CKE is active (CKEn-1=CKEn=H).

2. Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BA), depending on the

state of that bank.

3. Illegal if tRCD is not satisfied.

4. Illegal if tRAS is not satisfied.

5. Must satisfy burst interrupt condition.

6. Must satisfy bus contention, bus turn around, and/or write recovery requirements.

7. Must mask preceding data which don’t satisfy tDPL.

8. Illegal if tRRD is not satisfied.

16

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

ADVANCEDINFORMATION Rev. 00A

06/01/02

®

IS42S81600A, IS42S16800A, IS42S32400A

IS42LS81600A, IS42LS16800A, IS42LS32400A

ISSI

STATE DIAGRAM

Extended

Mode

Register

Set

Self

Refresh

SELF

EMRS

SELF exit

REF

Mode

Register

Set

MRS

CBR (Auto)

Refresh

IDLE

CKE

DPD

DPD Exit

CKE

Deep

Power

Down

ACT

Power

Down

CKE

Active

Power

Down

Row

Active

CKE

BST

Write

BST

Read

Auto Precharge

Read with

Write

Read

Write with

Read

CKE

Auto Precharge

WRITE

SUSPEND

READ

SUSPEND

READ

WRITE

Write

CKE

RRE (Precharge term

CKE

READA

SUSPEND

WRITEA

SUSPEND

WRITEA

READA

CKE

ination)

PRE (Precharge termination)

Precharge

POWER

ON

Precharge

Automatic sequence

Manual Input

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

ADVANCEDINFORMATION Rev. 00A

17

06/01/02

®

IS42S81600A, IS42S16800A, IS42S32400A

IS42LS81600A, IS42LS16800A, IS42LS32400A

ISSI

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

Symbol

Parameters

Rating

Unit

VDD MAX

Maximum Supply Voltage

–0.5 to +3.6

–0.5 to +4.6

V

VDDQMAX

+4.6

Maximum Supply Voltage for Output Buffer

V

–0.5 to +3.6 –0.5 to

VIN

InputVoltage

–0.5 to +3.6

–0.5 to +4.6

V

VOUT

PD MAX

ICS

OutputVoltage

–0.5 to +3.6

–0.5 to +4.6

AllowablePowerDissipation

OutputShortedCurrent

1

W

50

mA

°C

T^OPR

OperatingTemperature

Com.

Ind.

0 to +70

–40 to +85

0 to +70

–40 to +85

TSTG

StorageTemperature

–55 to +125

°C

Notes:

1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to

the device. This is a stress rating only and functional operation of the device at these or any other condi-

tions above those indicated in the operational sections of this specification is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect reliability.

2. All voltages are referenced to Vss.

DC RECOMMENDED OPERATING CONDITIONS⁽²⁾(At TA = 0 to +70°C)

42LSxxxxxx

Typ.

42Sxxxxxx

Typ.

Symbol

Parameter

Min.

Max.

Min.

Max.

Unit

VDD

SupplyVoltage

2.3

2.5

2.0

2.7

2.5

3.0

2.0

-0.3

3.3

3.6

V

VDDQ

I/O Supply Voltage

Input High Voltage

Input Low Voltage

1.65

(1)

VIH

0.8xVDDQ

-0.3

—

VDDQ + 0.3

+0.3

—

VDDQ + 0.3

+0.8

(2)

VIL

Note:

1. V^IH(max) = VDDQ +1.5V (PULSE WIDTH < 5NS).

2. VIL (min) = -1.5V (PULSE WIDTH < 5NS).

CAPACITANCE CHARACTERISTICS^(1,2)(At TA = 0 to +25°C, Vdd = VddQ= 3.3 ± 0.3V, f = 1 MHz)

Symbol

Parameter

Typ.

Max.

Unit

CIN1

CIN2

CI/O

Input Capacitance: A0-A11, BA0, BA1

—

3.5

3.8

6.5

pF

Input Capacitance: (CLK, CKE, CS, RAS, CAS, WE, LDQM, UDQM)

DataInput/OutputCapacitance:I/O0-I/O15

pss.

18

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

ADVANCEDINFORMATION Rev. 00A

06/01/02

®

IS42S81600A, IS42S16800A, IS42S32400A

IS42LS81600A, IS42LS16800A, IS42LS32400A

ISSI

DC ELECTRICAL CHARACTERISTICS (Recommended Operation Conditions unless otherwise noted.)

Symbol Parameter

TestCondition

Speed

Min.

Max.

Unit

IIL

InputLeakageCurrent

0V≤VIN ≤VDD,withpinsotherthan

–5

5

µA

thetestedpinat0V

I

OL

OH

OL

OutputLeakageCurrent

OutputHighVoltageLevel

OutputLowVoltageLevel

OperatingCurrent^(1,2)

Outputisdisabled,0V≤VOUT ≤VDD

–5

2.4

—

5

µA

V

IOUT =–2mA

—

0.4

V

IOUT=+2mA

V

IDD1

OneBankOperation,

BurstLength=1

CASlatency=3

Com.

Ind.

Com.

Ind.

-7

-10

—

120

140

110

120

mA

tRC ≥tRC (min.)

IOUT=0mA

I

DD2P

PrechargeStandbyCurrent

(InPower-DownMode)

CKE≤VIL

(

MAX

)

t

CK =tCK

(MIN

)

Com.

Ind.

Com.

Ind.

—

1

.6

mA

IDD2PS

tCK =∞

I

DD2N

PrechargeStandbyCurrent

(InNonPower-DownMode)

CKE≥VIH

CKE≤VIL

(

MIN

)

t

CK =tCK

(

MIN

)

—

11

5

7

mA

IDD2NS

tCK =∞

Com.

Ind.

IDD3P

ActiveStandbyCurrent

(InPower-DownMode)

(MAX

)

tCK =tCK

(MIN

Com.

Ind.

Com.

Ind.

—

4

6

3

5

mA

Ind.

IDD3PS

tCK =∞

I

DD3N

ActiveStandbyCurrent

(InNonPower-DownMode)

CKE≥VIH

(MIN

)

t

CK =tCK

(MIN

)

—

28

17

20

mA

IDD3NS

tCK =∞

Com.

Ind.

IDD4

OperatingCurrent

(InBurstMode)⁽¹⁾

t

CK =tCK

(

MIN

)

CASlatency=3

CASlatency=2

IOUT=0mA

Com.

Ind.

Com.

Ind.

-7

-10

—

120

140

110

120

mA

Com.

Ind.

Com.

Ind.

-7

-10

—

90

110

80

mA

100

Notes:

1. These are the values at the minimum cycle time. Since the currents are transient, these values decrease as the cycle time

increases. Also note that a bypass capacitor of at least 0.01 µF should be inserted between Vdd and Vss for each memory

chip to suppress power supply voltage noise (voltage drops) due to these transient currents.

2. Idd1 and Idd4 depend on the output load. The maximum values for Idd1 and Idd4 are obtained with the output open state.

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

ADVANCEDINFORMATION Rev. 00A

19

06/01/02

®

IS42S81600A, IS42S16800A, IS42S32400A

IS42LS81600A, IS42LS16800A, IS42LS32400A

ISSI

DC ELECTRICAL CHARACTERISTICS (Recommended Operation Conditions unless otherwise noted.)

Symbol Parameter

TestCondition

Speed

Min.

Max.

Unit

IDD5

Auto-RefreshCurrent

tRC =tRC

(MIN)

CASlatency=3

CASlatency=2

Com.

Ind.

Com.

Ind.

-7

-10

—

330

350

300

330

mA

Com.

Ind.

Com.

Ind.

-7

-10

—

330

350

300

330

mA

IDD6

Self-RefreshCurrent

PASR=000(full)

CKE≤0.2V,tCSR =00

ts<70^OC

—

0.35

0.25

0.18

0.12

0.09

mA

PASR=001(2BK)

PASR=010(1BK)

PASR=101(1/2BK)

PASR=110(1/4BK)

IDD6

Self-RefreshCurrent

PASR=000(full)

CKE≤0.2V,,tCSR =01

ts<45^OC

—

0.20

0.15

0.10

0.08

0.07

mA

PASR=001(2BK)

PASR=010(1BK)

PASR=101(1/2BK)

PASR=110(1/4BK)

IDD6

Self-RefreshCurrent

PASR=000(full)

CKE≤0.2V,,tCSR =11

ts<85^OC

—

0.60

0.50

0.43

0.37

0.34

mA

PASR=001(2BK)

PASR=010(1BK)

PASR=101(1/2BK)

PASR=110(1/4BK)

IDD7

StandbyCurrent in

CKE≤0.2V

—

10

µA

DeepPowerDownMode

20

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

ADVANCEDINFORMATION Rev. 00A

06/01/02

®

IS42S81600A, IS42S16800A, IS42S32400A

IS42LS81600A, IS42LS16800A, IS42LS32400A

ISSI

(1,2,3)

AC ELECTRICAL CHARACTERISTICS

-7

-10

Min.

Symbol Parameter

Min.

Max.

Max

Units

t^CK3

tCK2

Clock Cycle Time

CAS Latency = 3

CAS Latency = 2

7

10

—

10

—

ns

t^AC3

tAC2

Access Time From CLK⁽⁴⁾

CAS Latency = 3

CAS Latency = 2

—

5.4

6

—

7

9

ns

tCHI

tCL

CLK HIGH Level Width

CLK LOW Level Width

Output Data Hold Time

2.5

—

3.5

—

ns

t^OH3

tOH2

CAS Latency = 3

CAS Latency = 2

2.5

—

2.5

—

ns

tLZ

Output LOW Impedance Time

0

—

0

—

ns

t^HZ3

tHZ2

Output HIGH Impedance Time⁽⁵⁾CAS Latency = 3

CAS Latency = 2

—

6

—

7

9

ns

tDS

Input Data Setup Time

1.5

0.8

.5

—

0.8

2.0

1

—

1

ns

—

tDH

Input Data Hold Time

tAS

Address Setup Time

2.0

1

tAH

Address Hold Time

0.8

1.5

0.8

tCKS

tCKH

tCKA

tCS

CKE Setup Time

2.0

1

CKE Hold Time

CKE to CLK Recovery Delay Time

Command Setup Time (CS, RAS, CAS, WE, DQM)

Command Hold Time (CS, RAS, CAS, WE, DQM)

1CLK+3

1.5

1CLK+3

2.0

—

tCH

ns

tRC

Command Period (REF to REF / ACT to ACT)

Command Period (ACT to PRE)

63

37

—

120,000

—

70

44

—

120,000

—

ns

tRAS

tRP

Command Period (PRE to ACT)

15

18

tRCD

tRRD

tDPL3

Active Command To Read / Write Command Delay Time

Command Period (ACT [0] to ACT[1])

15

—

18

—

14

—

15

—

Input Data To Precharge

Command Delay time

CAS Latency = 3

2CLK

—

2CLK

—

tDPL2

tDAL3

CAS Latency = 2

2CLK

—

2CLK

—

ns

Input Data To Active / Refresh CAS Latency = 3

Command Delay time (During Auto-Precharge)

CAS Latency = 2

CLK+tRP

2CLK+tRP

tDAL2

tT

2CLK+tRP

0.5

—

30

64

2CLK+tRP

0.5

—

30

64

ns

Transition Time

tREF

Refresh Cycle Time (4096)

—

ms

Notes:

1. When power is first applied, memory operation should be started 100 µs after Vdd and Vdd^Qreach their stipulated voltages.

Also note that the power-on sequence must be executed before starting memory operation.

2. Measured with t^T= 1 ns.

3. The reference level is 0.9V when measuring input signal timing. Rise and fall times are measured between V^IH(min.) and VIL

(max.).

4. Access time is measured at 0.9V with the load shown in the figure below.

5. The time t^HZ(max.) is defined as the time required for the output voltage to transition by ± 200 mV from VOH (min.) or VOL (max.)

when the output is in the high impedance state.

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IS42S81600A, IS42S16800A, IS42S32400A

IS42LS81600A, IS42LS16800A, IS42LS32400A

ISSI

OPERATING FREQUENCY / LATENCY RELATIONSHIPS

SYMBOL PARAMETER

-7

7

-10.

UNITS

ns

—

Clock Cycle Time

10

100

1

—

OperatingFrequency

133

1

MHz

tCCD

tCKED

tPED

tDQD

tDQM

tDQZ

tDWD

tDAL

tDPL

tBDL

tCDL

tRDL

t^MRD

READ/WRITE command to READ/WRITE command

CKE to clock disable or power-down entry mode

CKE to clock enable or power-down exit setup mode

DQM to input data delay

cycle

1

0

DQM to data mask during WRITEs

DQM to data high-impedance during READs

WRITE command to input data delay

Data-in to ACTIVE command

0

2

0

5

4

Data-intoPRECHARGEcommand

Last data-in to burst STOP command

Last data-in to new READ/WRITE command

Last data-in to PRECHARGE command

2

1

2

LOAD MODE REGISTER command

to ACTIVE or REFRESH command

2

tROH

Data-outtohigh-impedancefrom

PRECHARGEcommand

CL = 3

CL = 2

3

2

3

2

cycle

22

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®

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IS42LS81600A, IS42LS16800A, IS42LS32400A

ISSI

AC TEST CONDITIONS

Input Load

Output Load

t

CK

t

CHI

t

CL

1.6V

Vddq

0.9V

0.2V

CLK

350Ω

Z = 50Ω

t

CS

t

CH

Output

30 pF

1.6V

0.9V

350Ω

INPUT

0.2V

t

AC

t

OH

OUTPUT

0.9V

AC TEST CONDITIONS

Parameter

Unit

AC High Level Input Voltage/Low Level Input Voltage

Input Rise and Fall Times

1.6V to 0.2V

1 ns

Input Timing Reference Level

0.9V

OutputTimingMeasurementReferenceLevel

0.9V

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ADVANCEDINFORMATION Rev. 00A

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®

IS42S81600A, IS42S16800A, IS42S32400A

IS42LS81600A, IS42LS16800A, IS42LS32400A

ISSI

Initialization

FUNCTIONAL DESCRIPTION

SDRAMs must be powered up and initialized in a

predefinedmanner.

The128MbSDRAMsarequad-bankDRAMswhichoperate

at 2.5V or 3.3V and include a synchronous interface (all

signals are registered on the positive edge of the clock

signal,CLK).Eachofthe16,777,216-bitbanksisorganized

as 4,096 rows by 256 columns by 16 bits.

The128MSDRAMisinitializedafterthepowerisappliedto

VDD and Vddq (simultaneously) and the clock is stable.

A 200µs delay is required prior to issuing any command

other than a COMMAND INHIBIT or aNOP. The COMMAND

INHIBITorNOPmaybeappliedduringthe100usperiodand

should continue at least through the end of the period.

Read and write accesses to the SDRAM are burst oriented;

accesses start at a selected location and continue for a

programmed number of locations in a programmed

sequence. Accesses begin with the registration of an AC-

TIVEcommandwhichisthenfollowedbyaREADorWRITE

command. The address bits registered coincident with the

ACTIVE command are used to select the bank and row to

With at least one COMMAND INHIBIT or NOP command

havingbeenapplied,aPRECHARGEcommandshouldbe

appliedoncethe100µsdelayhasbeensatisfied. Allbanks

mustbeprecharged. Thiswillleaveallbanksinanidlestate

wheretwoAUTOREFRESHcyclesmustbeperformed. After

theAUTOREFRESHcyclesarecomplete,theSRDRAMisthen

readyformoderegisterprogramming.

beaccessed(BA0andBA1selectthebank,A0-A11selecttherow)

.

Theaddressbits(A0-A7)registeredcoincidentwiththeREAD

orWRITEcommandareusedtoselectthestartingcolumn

location for the burst access.

Themoderegisterandextendedmoderegistersshouldbe

loadedpriortoapplyinganyoperationalcommandbecause

it will power up in an unknown state.

Prior to normal operation, the SDRAM must be initialized.

The following sections provide detailed information covering

device initialization, register definition, command

descriptions and device operation.

24

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IS42LS81600A, IS42LS16800A, IS42LS32400A

ISSI

INITIALIZE AND LOAD MODE REGISTER

T0

T1

Tn+1

tCH

To+1

tCL

Tp+1

Tp+2

Tp+3

tCK

CLK

CKE

tCKS tCKH

tCMH tCMS

PRECHARGE

tCMH tCMS

AUTO

Load MODE

REGISTER

COMMAND

NOP

ACTIVE

REFRESH

DQM/

DQML, DQMH

tAS tAH

A0-A9, A11

A10

ROW

BANK

CODE

tAS tAH

ALL BANKS

CODE

SINGLE BANK

ALL BANKS

BA0, BA1

DQ

T

tRP

tRFC

tMRD

Power-up: V^CC

and CLK stable all banks

Precharge AUTO REFRESH

AUTO REFRESH

Program MODE REGISTER^{(2, 3, 4)}

DON'T CARE

T = 100µs Min.

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IS42LS81600A, IS42LS16800A, IS42LS32400A

ISSI

AUTO-REFRESH CYCLE

T0

T1

T2

Tn+1

To+1

t

CK

t

CL

t

CH

CLK

CKE

t

CKS CKH

t

CMS

t

CMH

Auto

Refresh

Auto

COMMAND

PRECHARGE

NOP

ACTIVE

Refresh

DQM/

DQML, DQMH

A0-A9, A11

A10

ROW

BANK

ALL BANKS

SINGLE BANK

BANK^(s)

BA0, BA1

DQ

t

AS

t

AH

High-Z

t

RP

DON'T CARE

CAS latency = 2, 3

26

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ADVANCEDINFORMATION Rev. 00A

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®

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IS42LS81600A, IS42LS16800A, IS42LS32400A

ISSI

SELF-REFRESH CYCLE

T0

T1

T2

Tn+1

To+1

To+2

t

CK

t

CH

t

CL

CLK

CKE

t

CKS

t

CKH

t

CKS

≥ tRAS

t

CKS

t

CMS

t

CMH

Auto

COMMAND

PRECHARGE

NOP

Refresh

DQM/

DQML, DQMH

A0-A9, A11

A10

ALL BANKS

SINGLE BANK

t

AS

t

AH

BA0, BA1

DQ

BANK

High-Z

t

XSR

t

RP

Precharge all

active banks

Enter self

refresh mode

CLK stable prior to exiting

self refresh mode

Exit self refresh mode

(Restart refresh time base)

DON'T CARE

CAS latency = 2, 3

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IS42S81600A, IS42S16800A, IS42S32400A

IS42LS81600A, IS42LS16800A, IS42LS32400A

ISSI

EXTENDED MODE REGISTER SET

CLK

CKE

H

tRSC

2 CLK (min)

CS

RAS

CAS

WE

BA0

BA1

A10

Address Key

ADD

DQM

Hi-Z

DQ

DON'T CARE

Extended

Mode

Precharge

All Banks

Command

Activated

Command

is valid

Register Set

Command

28

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®

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IS42LS81600A, IS42LS16800A, IS42LS32400A

ISSI

REGISTER DEFINITION

Mode Register

Mode register bits M0-M2 specify the burst length, M3

specifiesthetypeofburst(sequentialorinterleaved), M4-M6

specify the CAS latency, M7 and M8 specify the operating

mode, M9 specifies the WRITE burst mode, and M10 and

M11 are reserved for future use.

The mode register is used to define the specific mode of

operation of the SDRAM. This definition includes the

selection of a burst length, a burst type, a CAS\ latency, an

operatingmodeandawriteburstmode,asshowninMODE

REGISTERDEFINITION.

The mode register must be loaded when all banks are idle,

and the controller must wait the specified time before

initiatingthesubsequentoperation.Violatingeitherofthese

requirements will result in unspecified operation.

The mode register is programmed via the LOAD MODE

REGISTER command and will retain the stored information

until it is programmed again or the device loses power.

MODE REGISTER DEFINITION

Address Bus

A11 A10 A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

Mode Register (Mx)

Reserved⁽¹⁾

Burst Length

M2 M1 M0

M3=0

M3=1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

4

8

1

2

4

8

Reserved Reserved

Full Page Reserved

Burst Type

M3

Type

0

1

Sequential

Interleaved

Latency Mode

M6 M5 M4

CAS Latency

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Reserved

2

3

Reserved

Operating Mode

M8 M7 M6-M0 Mode

0

Defined Standard Operation

All Other States Reserved

—

Write Burst Mode

M9

0

Mode

Programmed Burst Length

Single Location Access

1. To ensure compatibility with future devices,

should program M11, M10 = "0, 0"

1

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IS42S81600A, IS42S16800A, IS42S32400A

IS42LS81600A, IS42LS16800A, IS42LS32400A

ISSI

BURST LENGTH

ReadandwriteaccessestotheSDRAMareburstoriented,

with the burst length being programmable, as shown in

MODE REGISTER DEFINITION. The burst length deter-

mines the maximum number of column locations that can

be accessed for a given READ or WRITE command. Burst

lengths of 1, 2, 4 or 8 locations are available for both the

sequential and the interleaved burst types, and a full-page

burstisavailableforthesequentialtype.Thefull-pageburst

is used in conjunction with the BURST TERMINATE com-

mand to generate arbitrary burst lengths.

ing that the burst will wrap within the block if a boundary is

reached. The block is uniquely selected by A1-A7 (x16)

whentheburstlengthissettotwo;byA2-A7(x16)whenthe

burstlengthissettofour;andbyA3-A7(x16)whentheburst

length is set to eight. The remaining (least significant)

address bit(s) is (are) used to select the starting location

withintheblock.Full-pageburstswrapwithinthepageifthe

boundaryisreached.

Burst Type

Accesses within a given burst may be programmed to be

either sequential or interleaved; this is referred to as the

burst type and is selected via bit M3.

Reservedstatesshouldnotbeused,asunknownoperation

or incompatibility with future versions may result.

When a READ or WRITE command is issued, a block of

columnsequaltotheburstlengthiseffectivelyselected.All

accesses for that burst take place within this block, mean-

Theorderingofaccesseswithinaburstisdeterminedbythe

burstlength,thebursttypeandthestartingcolumnaddress,

as shown in BURST DEFINITION table.

BURST DEFINITION

Burst

StartingColumn

Address

OrderofAccessesWithinaBurst

Length

Type=Sequential

Type=Interleaved

A0

2

4

0

1

0-1

1-0

0-1

1-0

A1

0

A0

0

0-1-2-3

1-2-3-0

2-3-0-1

3-0-1-2

0-1-2-3

1-0-3-2

2-3-0-1

3-2-1-0

0

1

0

1

A2

A1

0

A0

0

0-1-2-3-4-5-6-7

1-2-3-4-5-6-7-0

2-3-4-5-6-7-0-1

3-4-5-6-7-0-1-2

4-5-6-7-0-1-2-3

5-6-7-0-1-2-3-4

6-7-0-1-2-3-4-5

7-0-1-2-3-4-5-6

0-1-2-3-4-5-6-7

1-0-3-2-5-4-7-6

2-3-0-1-6-7-4-5

3-2-1-0-7-6-5-4

4-5-6-7-0-1-2-3

5-4-7-6-1-0-3-2

6-7-4-5-2-3-0-1

7-6-5-4-3-2-1-0

NotSupported

0

1

0

1

0

8

0

1

0

1

0

1

0

1

Full

Page

(y)

n=A0-A7

Cn, Cn + 1, Cn + 2

Cn + 3, Cn + 4...

…Cn-1,

(location0-y)

Cn…

30

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®

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IS42LS81600A, IS42LS16800A, IS42LS32400A

ISSI

CAS Latency

The CAS latency is the delay, in clock cycles, between the

registration of a READ command and the availability of the

first piece of output data. The latency can be set to two or

three clocks.

reserved for future use and/or test modes. The programmed

burst length applies to both READ and WRITE bursts.

Test modes and reserved states should not be used

because unknown operation or incompatibility with future

versions may result.

If a READ command is registered at clock edge n, and the

latencyism clocks, thedatawillbeavailablebyclockedge

n+m.TheDQswillstartdrivingasaresultoftheclockedge

one cycle earlier (n + m - 1), and provided that the relevant

access times are met, the data will be valid by clock edge

n + m. For example, assuming that the clock cycle time is

such that all relevant access times are met, if a READ

commandisregisteredatT0andthelatencyisprogrammed

totwoclocks,theDQswillstartdrivingafterT1andthedata

willbevalidbyT2,asshowninCASLatencydiagrams.The

AllowableOperatingFrequencytableindicatestheoperat-

ing frequencies at which each CAS latency setting can be

used.

Write Burst Mode

When M9 = 0, the burst length programmed via M0-M2

appliestobothREADandWRITEbursts;whenM9=1, the

programmedburstlengthappliestoREADbursts,butwrite

accesses are single-location (nonburst) accesses.

CAS Latency

Allowable Operating Frequency (MHz)

Speed

7.5

CAS Latency = 2

CAS Latency = 3

Reservedstatesshouldnotbeusedasunknownoperationor

incompatibility with future versions may result.

100

75

133

100

10

Operating Mode

ThenormaloperatingmodeisselectedbysettingM7andM8

to zero; the other combinations of values for M7 and M8 are

CAS LATENCY

T0

T1

T2

T3

CLK

READ

NOP

COMMAND

DQ

t

AC

DOUT

t

LZ

t

OH

CAS Latency - 2

T0

T1

T2

T3

T4

CLK

READ

NOP

COMMAND

DQ

t

AC

DOUT

t

LZ

t

OH

CAS Latency - 3

DON'T CARE

UNDEFINED

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®

IS42S81600A, IS42S16800A, IS42S32400A

IS42LS81600A, IS42LS16800A, IS42LS32400A

ISSI

ACTIVATING SPECIFIC ROW WITHIN SPE-

CIFIC BANK

CHIP OPERATION

BANK/ROW ACTIVATION

BeforeanyREADorWRITEcommandscanbeissuedtoa

bankwithintheSDRAM,arowinthatbankmustbe“opened.”

This is accomplished via the ACTIVE command, which

selects both the bank and the row to be activated (see

Activating Specific Row Within Specific Bank).

CLK

HIGH

CKE

CS

After opening a row (issuing an ACTIVE command), a

READ or WRITE command may be issued to that row,

subject to the tRCD specification. Minimum tRCD should be

dividedbytheclockperiodandroundeduptothenextwhole

number to determine the earliest clock edge after the

ACTIVE command on which a READ or WRITE command

can be entered. For example, a tRCD specification of 20ns

with a 125 MHz clock (8ns period) results in 2.5 clocks,

rounded to 3. This is reflected in the following example,

which covers any case where 2 < [tRCD (MIN)/tCK] ≤ 3. (The

sameprocedureisusedtoconvertotherspecificationlimits

from time units to clock cycles).

RAS

CAS

WE

A0-A11

BA0, BA1

ROW ADDRESS

BANK ADDRESS

A subsequent ACTIVE command to a different row in the

samebankcanonlybeissuedafterthepreviousactiverow

hasbeen“closed”(precharged).Theminimumtimeinterval

betweensuccessiveACTIVEcommandstothesamebank

is defined by tRC.

A subsequent ACTIVE command to another bank can be

issuedwhilethefirstbankisbeingaccessed, whichresults

in a reduction of total row-access overhead. The minimum

time interval between successive ACTIVE commands to

different banks is defined by tRRD.

EXAMPLE: MEETING TRCD (MIN) WHEN 2 < [TRCD (MIN)/TCK] ≤ 3

T0

T1

T2

T3

T4

CLK

READ or

WRITE

ACTIVE

NOP

COMMAND

tRCD

DON'T CARE

32

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IS42LS81600A, IS42LS16800A, IS42LS32400A

ISSI

READS

READ COMMAND

READburstsareinitiatedwithaREADcommand,asshown

in the READ COMMAND diagram.

CLK

CKE

Thestartingcolumnandbankaddressesareprovidedwiththe

READ command, and auto precharge is either enabled or

disabledforthatburstaccess.Ifautoprechargeisenabled,the

row being accessed is precharged at the completion of the

burst.ForthegenericREADcommandsusedinthefollowing

illustrations, auto precharge is disabled.

HIGH

CS

During READ bursts, the valid data-out element from the

startingcolumnaddresswillbeavailablefollowingtheCAS

latencyaftertheREADcommand. Eachsubsequent data-

outelementwillbevalidbythenextpositiveclockedge.The

CAS Latency diagram shows general timing

for each possible CAS latency setting.

RAS

CAS

WE

Upon completion of a burst, assuming no other commands

havebeeninitiated,theDQswillgoHigh-Z.Afull-pageburst

will continue until terminated. (At the end of the page, it will

wrap to column 0 and continue.)

COLUMN ADDRESS

AUTO PRECHARGE

A0-A7

A8, A9, A11

A10

Data from any READ burst may be truncated with a subse-

quentREADcommand, anddatafromafixed-lengthREAD

burst may be immediately followed by data from a READ

command. In either case, a continuous flow of data can be

maintained.Thefirstdataelementfromthenewburstfollows

eitherthelastelementofacompletedburstorthelastdesired

data element of a longer burst which is being truncated.

NO PRECHARGE

BANK ADDRESS

BA0, BA1

ThenewREADcommandshouldbeissuedxcyclesbefore

the clock edge at which the last desired data element is

valid, where x equals the CAS latency minus one. This is

shown in Consecutive READ Bursts for CAS latencies of

twoandthree;dataelementn+3iseitherthelastofaburst

of four or the last desired of a longer burst. The 64Mb

SDRAM uses a pipelined architecture and therefore does

not require the 2n rule associated with a prefetch architec-

ture. AREADcommandcanbeinitiatedonanyclockcycle

following a previous READ command. Full-speed random

readaccessescanbeperformedtothesamebank,asshown

in Random READ Accesses, or each subsequent READ

may be performed to a different bank.

The DQM input is used to avoid I/O contention, as shown

in Figures RW1 and RW2. The DQM signal must be

asserted (HIGH) at least two clocks prior to the WRITE

command(DQMlatencyistwoclocksforoutputbuffers)to

suppress data-out from the READ. Once the WRITE com-

mandisregistered,theDQswillgoHigh-Z(orremainHigh-

Z), regardless of the state of the DQM signal, provided the

DQM was active on the clock just prior to the WRITE

command that truncated the READ command. If not, the

second WRITE will be an invalid WRITE. For example, if

DQMwasLOWduringT4inFigureRW2,thentheWRITEs

at T5 and T7 would be valid, while the WRITE at T6 would

be invalid.

Data from any READ burst may be truncated with a

subsequent WRITE command, and data from a fixed-length

READ burst may be immediately followed by data from a

WRITE command (subject to bus turnaround limitations).

The WRITE burst may be initiated on the clock edge

immediatelyfollowingthelast(orlastdesired)dataelement

from the READ burst, provided that I/O contention can be

avoided. In a given system design, there may be a possi-

bility that the device driving the input data will go Low-Z

before the SDRAM DQs go High-Z. In this case, at least a

single-cycledelayshouldoccurbetweenthelastreaddata

and the WRITE command.

The DQM signal must be de-asserted prior to the WRITE

command (DQM latency is zero clocks for input buffers) to

ensure that the written data is not masked. Figure RW1

shows the case where the clock frequency allows for bus

contention to be avoided without adding a NOP cycle, and

Figure RW2 shows the case where the additional NOP is

needed.

Afixed-lengthREADburstmaybefollowedby, ortruncated

with, aPRECHARGEcommandtothesamebank(provided

that auto precharge was not activated), and a full-page burst

may be truncated with a PRECHARGE command to the

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IS42LS81600A, IS42LS16800A, IS42LS32400A

ISSI

samebank.ThePRECHARGEcommandshouldbeissued

xcyclesbeforetheclockedgeatwhichthelastdesireddata

elementisvalid,wherexequalstheCASlatencyminusone.

ThisisshownintheREADtoPRECHARGEdiagramforeach

possible CAS latency; data elementn + 3 is either the last of

a burst of four or the last desired of a longer burst. Following

thePRECHARGEcommand,asubsequentcommandtothe

same bank cannot be issued until t^RPis met. Note that part

of the row precharge time is hidden during the access of the

last data element(s).

In the case of a fixed-length burst being executed to

completion, a PRECHARGE command issued at the opti-

mum time (as described above) provides the same opera-

tion that would result from the same fixed-length burst with

auto precharge. The disadvantage of the PRECHARGE

commandisthatitrequiresthatthecommandandaddress

buses be available at the appropriate time to issue the

command;theadvantageofthePRECHARGEcommandis

that it can be used to truncate fixed-length or full-page

bursts.

Full-page READ bursts can be truncated with the BURST

TERMINATE command, and fixed-length READ bursts

may be truncated with a BURST TERMINATE command,

providedthatautoprechargewasnotactivated.TheBURST

TERMINATE command should be issued x cycles before

the clock edge at which the last desired data element is

valid, where x equals the CAS latency minus one. This is

shown in the READ Burst Termination diagram for each

possibleCASlatency;dataelementn+3isthelastdesired

data element of a longer burst.

34

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ADVANCEDINFORMATION Rev. 00A

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®

IS42S81600A, IS42S16800A, IS42S32400A

IS42LS81600A, IS42LS16800A, IS42LS32400A

ISSI

RW1 - READ TO WRITE

T0

T1

T2

T3

T4

CLK

DQM

COMMAND

ADDRESS

DQ

READ

NOP

WRITE

BANK,

COL n

BANK,

COL b

t

HZ

DOUT

n

DIN

b

t

DS

DON'T CARE

RW2 - READ TO WRITE WITH EXTRA CLOCK CYCLE

T0

T1

T2

T3

T4

T5

CLK

DQM

COMMAND

ADDRESS

DQ

READ

NOP

WRITE

BANK,

COL b

BANK,

COL n

t

HZ

DOUT

n

DIN

b

t

DS

DON'T CARE

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IS42S81600A, IS42S16800A, IS42S32400A

IS42LS81600A, IS42LS16800A, IS42LS32400A

ISSI

CONSECUTIVE READ BURSTS

T0

T1

T2

T3

T4

T5

T6

CLK

COMMAND

ADDRESS

DQ

READ

NOP

READ

NOP

x=1 cycle

BANK,

COL n

BANK,

COL b

DOUT

n

DOUT n+1

DOUT n+2

DOUT n+3

DOUT

b

CAS Latency - 2

DON'T CARE

T0

T1

T2

T3

T4

T5

T6

T7

CLK

COMMAND

READ

NOP

READ

NOP

x = 2 cycles

BANK,

COL n

BANK,

COL b

ADDRESS

DQ

DOUT n

DOUT n+1

DOUT n+2

DOUT n+3

DOUT b

CAS Latency - 3

DON'T CARE

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®

IS42S81600A, IS42S16800A, IS42S32400A

IS42LS81600A, IS42LS16800A, IS42LS32400A

ISSI

RANDOM READ ACCESSES

T0

T1

T2

T3

T4

T5

CLK

COMMAND

ADDRESS

DQ

READ

NOP

BANK,

COL n

BANK,

COL b

BANK,

COL m

BANK,

COL x

DOUT

n

DOUT

b

DOUT

m

DOUT

x

CAS Latency - 2

DON'T CARE

T0

T1

T2

T3

T4

T5

T6

CLK

COMMAND

ADDRESS

DQ

READ

NOP

BANK,

COL n

BANK,

COL b

BANK,

COL m

BANK,

COL x

DOUT

n

DOUT

b

DOUT

m

DOUT

x

CAS Latency - 3

DON'T CARE

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IS42S81600A, IS42S16800A, IS42S32400A

IS42LS81600A, IS42LS16800A, IS42LS32400A

ISSI

RW1 - READ TO WRITE

T0

T1

T2

T3

T4

CLK

DQM

COMMAND

ADDRESS

DQ

READ

NOP

WRITE

BANK,

COL n

BANK,

COL b

t

HZ

DOUT

n

DIN

b

t

DS

DON'T CARE

RW2 - READ TO WRITE WITH EXTRA CLOCK CYCLE

T0

T1

T2

T3

T4

T5

CLK

DQM

COMMAND

ADDRESS

DQ

READ

NOP

WRITE

BANK,

COL b

BANK,

COL n

t

HZ

DOUT

n

DIN

b

t

DS

DON'T CARE

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IS42S81600A, IS42S16800A, IS42S32400A

IS42LS81600A, IS42LS16800A, IS42LS32400A

ISSI

READ BURST TERMINATION

T0

T1

T2

T3

T4

T5

T6

CLK

COMMAND

ADDRESS

DQ

BURST

TERMINATE

READ

NOP

x = 1 cycle

BANK a,

COL n

DOUT

n

DOUT n+1

DOUT n+2

DOUT n+3

CAS Latency - 2

DON'T CARE

T0

T1

T2

T3

T4

T5

T6

T7

CLK

COMMAND

ADDRESS

DQ

BURST

TERMINATE

READ

NOP

x = 2 cycles

NOP

BANK,

COL n

DOUT

n

DOUT n+1

DOUT n+2

DOUT n+3

CAS Latency - 3

DON'T CARE

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IS42S81600A, IS42S16800A, IS42S32400A

IS42LS81600A, IS42LS16800A, IS42LS32400A

ISSI

ALTERNATING BANK READ ACCESSES

T0

T1

T2

T3

T4

T5

T6

T7

T8

t

CK

t

CL

tCH

CLK

CKE

t

CKS tCKH

t

CMS

tCMH

COMMAND

ACTIVE

NOP

READ

NOP

ACTIVE

NOP

READ

NOP

ACTIVE

t

CMS tCMH

DQM/

DQML, DQMH

t

AS

tAH

COLUMN m⁽²⁾

ROW

COLUMN b⁽²⁾

ROW

A0-A9, A11

A10

ROW

AS

t

AH

ENABLE AUTO PRECHARGE

ROW

AS

tAH

BANK 0

BANK 3

BANK 0

BA0, BA1

BANK 0

t

LZ

t

OH

t

OH

t

OH

t

OH

t

OH

DQ

DOUT

m

D

OUT m+

1

DOUT m+

2

DOUT m+

3

DOUT

b

t

AC

t

AC

t

AC

t

AC

t

AC

t

AC

t

RCD - BANK 0

RRD

CAS Latency - BANK 0

t

RP - BANK 0

tRCD - BANK 0

t

RCD - BANK 3

CAS Latency - BANK 3

RAS - BANK 0

RC - BANK 0

DON'T CARE

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IS42LS81600A, IS42LS16800A, IS42LS32400A

ISSI

READ - FULL-PAGE BURST

T0

T1

T2

T3

T4

T5

T6

Tn+1

Tn+2

Tn+3

Tn+4

t

CK

t

CL

tCH

CLK

CKE

t

CKS tCKH

t

CMS

t

CMH

COMMAND

ACTIVE

NOP

READ

CMS CMH

NOP

BURST TERM

NOP

t

DQM/

DQML, DQMH

t

AS

tAH

COLUMN m⁽²⁾

A0-A9, A11

A10

ROW

AS

t

AH

ROW

AS

t

AH

BA0, BA1

BANK

t

AC

t

AC

t

AC

t

AC

t

AC

t

AC

tHZ

D

OUT

m

D

OUT m+

1

D

OUT m+

2

D

OUT m-

1

D

OUT

m

D

OUT m+

1

DQ

t

LZ

t

OH

t

OH

t

OH

t

OH

t

OH

tOH

t

RCD

CAS Latency

each row (x4) has

1,024 locations

DON'T CARE

UNDEFINED

Full page Full-page burst not self-terminating.

completion Use BURST TERMINATE command.

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ADVANCEDINFORMATION Rev. 00A

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®

IS42S81600A, IS42S16800A, IS42S32400A

IS42LS81600A, IS42LS16800A, IS42LS32400A

ISSI

READ - DQM OPERATION

T0

T1

T2

T3

T4

T5

T6

T7

T8

t

CK

t

CL

tCH

CLK

CKE

t

CKS tCKH

t

CMS tCMH

COMMAND

ACTIVE

NOP

READ

NOP

t

CMS

t

CMH

DQM/

DQML, DQMH

t

AS

tAH

COLUMN m⁽²⁾

A0-A9, A11

A10

ROW

AS

t

AH

ENABLE AUTO PRECHARGE

ROW

DISABLE AUTO PRECHARGE

AS

t

AH

BA0, BA1

BANK

t

OH

t

OH

tOH

t

AC

tAC

D

OUT

m

D

OUT m+

2

D

OUT m+

3

DQ

t

LZ

tLZ

t

HZ

t

AC

t

HZ

DON'T CARE

UNDEFINED

t

RCD

CAS Latency

42

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IS42S81600A, IS42S16800A, IS42S32400A

IS42LS81600A, IS42LS16800A, IS42LS32400A

ISSI

READ to PRECHARGE

T0

T1

T2

T3

T4

T5

T6

T7

CLK

COMMAND

ADDRESS

DQ

t

RP

PRECHARGE

READ

NOP

ACTIVE

x = 1 cycle

BANK a,

COL n

BANK

(a or all)

BANK a,

ROW

DOUT

n

DOUT n+1

DOUT n+2

DOUT n+3

CAS Latency - 2

DON'T CARE

T0

T1

T2

T3

T4

T5

T6

T7

CLK

COMMAND

ADDRESS

DQ

t

RP

PRECHARGE

READ

NOP

x = 2 cycles

NOP

ACTIVE

BANK,

COL n

BANK,

COL b

BANK a,

ROW

DOUT

n

DOUT n+1

D

OUT n+2

DOUT n+3

CAS Latency - 3

DON'T CARE

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ADVANCEDINFORMATION Rev. 00A

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IS42S81600A, IS42S16800A, IS42S32400A

IS42LS81600A, IS42LS16800A, IS42LS32400A

ISSI

WRITES

An example is shown in WRITE to WRITE diagram. Data n

+ 1 is either the last of a burst of two or the last desired of

a longer burst. The 128Mb SDRAM uses a pipelined

architecture and therefore does not require the 2n rule

associated with a prefetch architecture. A WRITE command

can be initiated on any clock cycle following a previous

WRITEcommand.Full-speedrandomwriteaccesseswithin

a page can be performed to the same bank, as shown in

Random WRITE Cycles, or each subsequent WRITE may

be performed to a different bank.

WRITE bursts are initiated with a WRITE command, as

showninWRITECommanddiagram.

WRITE COMMAND

CLK

HIGH

CKE

Data for any WRITE burst may be truncated with a subse-

quentREADcommand, anddataforafixed-length WRITE

burst may be immediately followed by a subsequent READ

command. Once the READ com mand is registered, the

data inputs will be ignored, and WRITEs will not be ex-

ecuted. An example is shown in WRITE to READ. Data n +

1 is either the last of a burst of two or the last desired of a

longerburst.

CS

RAS

CAS

WE

Dataforafixed-lengthWRITEburstmaybefollowed by,or

truncatedwith,aPRECHARGEcommandtothesamebank

(providedthatautoprechargewasnotactivated),andafull-

page WRITE burst may be truncated with a PRECHARGE

commandtothesamebank.ThePRECHARGEcommand

should be issued t^WRafter the clock edge at which the last

desiredinputdataelementisregistered.Theautoprecharge

mode requires a tWR of at least one clock plus time,

regardless of frequency. In addition, when truncating a

WRITE burst, the DQM signal must be used to mask input

datafortheclockedgepriorto,andtheclockedgecoincident

with,thePRECHARGEcommand.Anexampleisshowninthe

WRITEtoPRECHARGEdiagram.Datan+1iseitherthelast

ofaburstoftwoorthelastdesiredofalongerburst.Following

thePRECHARGEcommand,asubsequentcommandtothe

same bank cannot be issued until tRP is met.

COLUMN ADDRESS

AUTO PRECHARGE

A0-A7

A8, A9, A11

A10

NO PRECHARGE

BANK ADDRESS

BA0, BA1

The starting column and bank addresses are provided with

theWRITEcommand,andautoprechargeiseitherenabled

ordisabledforthataccess. Ifautoprechargeisenabled, the

row being accessed is precharged at the completion of the

burst. For the generic WRITE commands used in the

following illustrations, auto precharge is disabled.

In the case of a fixed-length burst being executed to comple-

tion,aPRECHARGEcommandissuedattheoptimumtime(as

describedabove)providesthesameoperationthatwouldresult

from the same fixed-length burst with auto precharge. The

disadvantageofthePRECHARGEcommandisthatitrequires

that the command and address buses be available at the

appropriatetimetoissuethecommand;theadvantageofthe

PRECHARGE command is that it can be used to truncate

fixed-length or full-page bursts.

During WRITE bursts, the first valid data-in element will be

registeredcoincidentwiththeWRITEcommand. Subsequent

dataelementswillberegisteredoneachsuccessivepositive

clockedge.Uponcompletionofafixed-lengthburst,assum-

ing no other commands have been initiated, the DQs will

remain High-Z and any additional input data will be ignored

(see WRITE Burst). A full-page burst will continue until

terminated. (At the end of the page, it will wrap to column 0

andcontinue.)

Fixed-length or full-page WRITE bursts can be truncated

withtheBURSTTERMINATEcommand.Whentruncating

a WRITE burst, the input data applied coincident with the

BURST TERMINATE command will be ignored. The last

datawritten(providedthatDQMisLOWatthattime)willbe

the input data applied one clock previous to the BURST

TERMINATE command. This is shown in WRITE Burst

Termination, where data n is the last desired data element

of a longer burst.

Data for any WRITE burst may be truncated with a subse-

quent WRITE command, and data for a fixed-length WRITE

burst may be immediately followed by data for a WRITE

command. The new WRITE command can be issued on any

clock following the previous WRITE command, and the data

providedcoincidentwiththenewcommandappliestothenew

command.

44

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ADVANCEDINFORMATION Rev. 00A

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IS42S81600A, IS42S16800A, IS42S32400A

IS42LS81600A, IS42LS16800A, IS42LS32400A

ISSI

WRITE BURST

T0

T1

T2

T3

CLK

COMMAND

ADDRESS

DQ

WRITE

NOP

BANK,

COL n

DIN

n

DIN n+1

DON'T CARE

WRITE TO WRITE

T0

T1

T2

CLK

COMMAND

ADDRESS

DQ

WRITE

NOP

WRITE

BANK,

COL n

BANK,

COL b

DIN

n

DIN n+1

DIN b

DON'T CARE

RANDOM WRITE CYCLES

T0

T1

T2

T3

CLK

COMMAND

ADDRESS

DQ

WRITE

BANK,

COL n

BANK,

COL b

BANK,

COL m

BANK,

COL x

DIN

n

DIN

b

DIN

m

DIN x

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IS42S81600A, IS42S16800A, IS42S32400A

IS42LS81600A, IS42LS16800A, IS42LS32400A

ISSI

WRITE TO READ

T0

T1

T2

T3

T4

T5

CLK

COMMAND

ADDRESS

DQ

WRITE

NOP

READ

NOP

BANK,

COL n

BANK,

COL b

DIN

n

DIN n+1

D

OUT

b

DOUT b+1

Latency = 2

DON'T CARE

WRITE TO PRECHARGE (TWR @ TCK ≥ 15NS)

T0

T1

T2

T3

T4

T5

T6

CLK

DQM

tRP

PRECHARGE

COMMAND

ADDRESS

DQ

WRITE

NOP

ACTIVE

NOP

BANK a,

COL n

BANK

(a or all)

BANK a,

ROW

tWR

DIN n+1

DIN n

DON'T CARE

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IS42S81600A, IS42S16800A, IS42S32400A

IS42LS81600A, IS42LS16800A, IS42LS32400A

ISSI

WRITE to PRECHARGE (tWR @ tCK < 15ns)

T0

T1

T2

T3

T4

T5

T6

CLK

DQM

tRP

PRECHARGE

COMMAND

ADDRESS

DQ

WRITE

NOP

ACTIVE

NOP

BANK a,

COL n

BANK

(a or all)

BANK a,

ROW

tWR

DIN

n

DIN n+1

DON'T CARE

WRITE Burst Termination

T0

T1

T2

CLK

BURST

TERMINATE

ADDRESS

DQ

WRITE

COMMAND

BANK,

COL n

(ADDRESS)

DIN

n

(DATA)

DON'T CARE

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IS42LS81600A, IS42LS16800A, IS42LS32400A

ISSI

WRITE - FULL PAGE BURST

T0

T1

T2

T3

T4

T5

Tn+1

Tn+2

t

CK

t

CL

t

CH

CLK

CKE

t

CKS CKH

t

CMS

t

CMH

COMMAND

ACTIVE

NOP

WRITE

NOP

BURST TERM

NOP

t

CMS

t

CMH

DQM/

DQML, DQMH

t

AS

t

AH

COLUMN m⁽²⁾

A0-A9, A11

A10

ROW

AS

t

AH

ROW

AS

t

AH

BA0, BA1

BANK

t

DS

t

DH

t

DS

t

DH

t

DS

t

DH

t

DS

t

DH

t

DS

t

DH

t

DS

t

DH

DIN

m

DIN m+

1

DIN m+

2

DIN m+

3

DIN m-1

DQ

t

RCD

Full page completed

DON'T CARE

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ADVANCEDINFORMATION Rev. 00A

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IS42S81600A, IS42S16800A, IS42S32400A

IS42LS81600A, IS42LS16800A, IS42LS32400A

ISSI

WRITE - DQM OPERATIOON

T0

T1

T2

T3

T4

T5

T6

T7

t

CK

t

CL

t

CH

CLK

CKE

t

CKS CKH

t

CMS

t

CMH

COMMAND

ACTIVE

NOP

WRITE

NOP

t

CMS

t

CMH

DQM/

DQML, DQMH

t

AS

t

AH

COLUMN m⁽²⁾

A0-A9, A11

A10

ROW

AS

t

AH

ENABLE AUTO PRECHARGE

ROW

DISABLE AUTO PRECHARGE

AS

t

AH

BA0, BA1

BANK

t

DS

t

DH

t

DS

t

DH

t

DS

t

DH

DIN

m

D

IN m+

2

DIN m+3

DQ

t

RCD

DON'T CARE

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ADVANCEDINFORMATION Rev. 00A

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®

IS42S81600A, IS42S16800A, IS42S32400A

IS42LS81600A, IS42LS16800A, IS42LS32400A

ISSI

ALTERNATING BANK WRITE ACCESS

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

t

CK

t

CL

tCH

CLK

CKE

t

CKS tCKH

t

CMS

tCMH

COMMAND

ACTIVE

NOP

WRITE

NOP

ACTIVE

NOP

WRITE

NOP

ACTIVE

t

CMS tCMH

DQM/

DQML, DQMH

t

AS

tAH

COLUMN m⁽²⁾

ROW

COLUMN b⁽²⁾

ROW

A0-A9, A11

A10

ROW

AS

t

AH

ENABLE AUTO PRECHARGE

ROW

AS

tAH

BANK 0

BANK 1

BANK 0

BA0, BA1

BANK 0

t

DS

t

DH

t

DS

t

DH

t

DS

t

DH

t

DS

t

DH

t

DS

t

DH

t

DS

t

DH

t

DS

tDH

t

DS

tDH

DQ

DIN

m

D

IN m+

1

DIN m+

2

DIN m+

3

DIN

b

D

IN b+

1

DIN b+

2

DIN b+3

t

RCD - BANK 0

RRD

t

WR - BANK 0

t

RP - BANK 0

t

RCD - BANK 0

t

RCD - BANK 1

tWR - BANK 1

RAS - BANK 0

RC - BANK 0

DON'T CARE

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ADVANCEDINFORMATION Rev. 00A

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IS42S81600A, IS42S16800A, IS42S32400A

IS42LS81600A, IS42LS16800A, IS42LS32400A

ISSI

CLOCK SUSPEND

Any command or data present on the input pins at the time

of a suspended internal clock edge is ignored; any data

presentontheDQpinsremainsdriven;andburstcounters

are not incremented, as long as the clock is suspended.

(Seefollowingexamples.)

Clock suspend mode occurs when a column access/burst

is in progress and CKE is registered LOW. In the clock

suspend mode, the internal clock is deactivated, “freezing”

the synchronous logic.

For each positive clock edge on which CKE is sampled

LOW, the next internal positive clock edge is suspended.

ClocksuspendmodeisexitedbyregisteringCKEHIGH;the

internal clock and related operation will resume on the

subsequent positive clock edge.

Clock Suspend During WRITE Burst

T0

T1

T2

T3

T4

T5

CLK

CKE

INTERNAL

CLOCK

COMMAND

ADDRESS

DQ

NOP

WRITE

NOP

BANK a,

COL n

DIN

n

DIN n+1

DIN n+2

DON'T CARE

Clock Suspend During READ Burst

T0

T1

T2

T3

T4

T5

T6

CLK

CKE

INTERNAL

CLOCK

COMMAND

ADDRESS

DQ

READ

NOP

BANK a,

COL n

Qn

Qn+1

Qn+2

Qn+3

DON'T CARE

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ADVANCEDINFORMATION Rev. 00A

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®

IS42S81600A, IS42S16800A, IS42S32400A

IS42LS81600A, IS42LS16800A, IS42LS32400A

ISSI

CLOCK SUSPEND MODE

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

t

CK

t

CL

t

CH

CLK

CKE

t

CKS

t

CKH

t

CKS CKH

t

CMS

t

CMH

COMMAND

READ

NOP

WRITE

NOP

t

CMS

t

CMH

DQM/

DQML, DQMH

t

AS

t

AH

COLUMN n⁽²⁾

A0-A9, A11

A10

COLUMN m⁽²⁾

t

AS

t

AH

t

AS

t

AH

BA0, BA1

BANK

t

DS

t

DH

t

AC

t

AC

t

HZ

DQ

DOUT

m

DOUT m+1

DOUT

e

DOUT e+1

t

LZ

t

OH

DON'T CARE

UNDEFINED

CAS latency = 2, burst length = 2

52

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ADVANCEDINFORMATION Rev. 00A

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®

IS42S81600A, IS42S16800A, IS42S32400A

IS42LS81600A, IS42LS16800A, IS42LS32400A

ISSI

PRECHARGE

PRECHARGE Command

The PRECHARGE command (see figure) is used to deac-

tivatetheopenrowinaparticularbankortheopenrowinall

banks. The bank(s) will be available for a subsequent row

access some specified time (tRP) after the PRECHARGE

command is issued. Input A10 determines whether one or

all banks are to be precharged, and in the case where only

one bank is to be precharged, inputs BA0, BA1 select the

bank. When all banks are to be precharged, inputs BA0,

BA1 are treated as “Don’t Care.” Once a bank has been

precharged,itisintheidlestateandmustbeactivatedprior

to any READ or WRITE commands being issued to that

bank.

CLK

HIGH

CKE

CS

RAS

CAS

WE

POWER-DOWN

Power-down occurs if CKE is registered LOW coincident

with a NOP or COMMAND INHIBIT when no accesses are

in progress. If power-down occurs when all banks are idle,

thismodeisreferredtoasprechargepower-down;ifpower-

down occurs when there is a row active in either bank, this

modeisreferredtoasactivepower-down.Enteringpower-

down deactivates the input and output buffers, excluding

CKE, for maximum power savings while in standby. The

devicemaynotremaininthepower-downstatelongerthan

the refresh period (64ms) since no refresh operations are

performed in this mode.

A0-A9, A11

ALL BANKS

A10

BANK SELECT

BANK ADDRESS

BA0, BA1

The power-down state is exited by registering a NOP or

COMMAND INHIBIT and CKE HIGH at the desired clock

edge (meeting tCKS). See figure below.

POWER-DOWN

CLK

t

CKS

≥ t^CKS

CKE

COMMAND

NOP

ACTIVE

t

RCD

RAS

RC

All banks idle

Input buffers gated off

Enter power-down mode

Exit power-down mode

less than 64ms

DON'T CARE

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

ADVANCEDINFORMATION Rev. 00A

53

06/01/02

®

IS42S81600A, IS42S16800A, IS42S32400A

IS42LS81600A, IS42LS16800A, IS42LS32400A

ISSI

POWER-DOWN MODE CYCLE

T0

T1

T2

Tn+1

Tn+2

t

CK

t

CL

t

CH

CLK

CKE

t

CKS

t

CKH

t

CKS

t

CKS

t

CMS

t

CMH

COMMAND

PRECHARGE

NOP

ACTIVE

DQM/

DQML, DQMH

A0-A9, A11

A10

ROW

ALL BANKS

SINGLE BANK

t

AS

t

AH

BA0, BA1

DQ

BANK

High-Z

Two clock cycles

Input buffers gated

All banks idle

off while in

Precharge all

active banks

All banks idle, enter

power-down mode

DON'T CARE

Exit power-down mode

CAS latency = 2, 3

54

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

ADVANCEDINFORMATION Rev. 00A

06/01/02

®

IS42S81600A, IS42S16800A, IS42S32400A

IS42LS81600A, IS42LS16800A, IS42LS32400A

ISSI

BURST READ/SINGLE WRITE

Four cases where CONCURRENT AUTO PRECHARGE

occurs are defined below.

The burst read/single write mode is entered by programming

the write burst mode bit (M9) in the mode register to a logic 1.

In this mode, all WRITE commands result in the access of a

single column location (burst of one), regardless of the

programmed burst length. READ commands access

columns according to the programmed burst length and

sequence, just as in the normal mode of operation (M9 = 0).

READ with Auto Precharge

1. Interrupted by a READ (with or without auto precharge):

AREADtobankmwillinterruptaREADonbankn, CAS

latency later. The PRECHARGE to bank n will begin

when the READ to bank m is registered.

CONCURRENT AUTO PRECHARGE

2.InterruptedbyaWRITE(withorwithoutautoprecharge):

AWRITEtobankmwillinterruptaREADonbanknwhen

registered. DQM should be used two clocks prior to the

WRITE command to prevent bus contention. The

PRECHARGE to bank n will begin when the WRITE to

bank m is registered.

An access command (READ or WRITE) to another bank

while an access command with auto precharge enabled is

executing is not allowed by SDRAMs, unless the SDRAM

supports CONCURRENT AUTO PRECHARGE. ISSI

SDRAMs support CONCURRENT AUTO PRECHARGE.

READ With Auto Precharge interrupted by a READ

T0

T1

T2

T3

T4

T5

T6

T7

CLK

READ - AP

BANK n

READ - AP

BANK m

NOP

Idle

COMMAND

BANK n

Page Active

READ with Burst of 4

Page Active

Interrupt Burst, Precharge

tRP - BANK n

tRP - BANK m

Internal States

BANK m

READ with Burst of 4

Precharge

BANK n,

COL a

BANK m,

COL b

ADDRESS

DQ

DOUT

a

DOUT a+1

DOUT

b

DOUT b+1

CAS Latency - 3 (BANK n)

CAS Latency - 3 (BANK m)

DON'T CARE

READ With Auto Precharge interrupted by a WRITE

T0

T1

T2

T3

T4

T5

T6

T7

CLK

WRITE - AP

BANK n

WRITE - AP

BANK m

COMMAND

NOP

Idle

BANK n

READ with Burst of 4

Page Active

Interrupt Burst, Precharge

Page Active

t

RP - BANK n

tRP - BANK m

Internal States

BANK m

WRITE with Burst of 4

Write-Back

BANK n,

COL a

BANK m,

COL b

ADDRESS

DQM

DQ

DOUT

a

DIN

b

DIN b+1

DIN b+2

DIN b+3

CAS Latency - 3 (BANK n)

DON'T CARE

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

ADVANCEDINFORMATION Rev. 00A

55

06/01/02

®

IS42S81600A, IS42S16800A, IS42S32400A

IS42LS81600A, IS42LS16800A, IS42LS32400A

ISSI

WRITE with Auto Precharge

4.InterruptedbyaWRITE(withorwithoutautoprecharge):

WRITE to bank m will interrupt a WRITE on bank n when

3. Interrupted by a READ (with or without auto precharge):

AREADtobankmwillinterruptaWRITEonbanknwhen

registered,withthedata-outappearing(CASlatency) later.

The PRECHARGE to bank n will begin after t^WRis met,

wheretWR beginswhentheREADtobankmisregistered.

ThelastvalidWRITEtobanknwillbedata-inregisteredone

clock prior to the READ to bank m.

A

registered.ThePRECHARGEtobanknwillbeginaftertWR

is met, where tWR begins when the WRITE to bank m is

registered.ThelastvaliddataWRITEtobanknwillbedata

registered one clock prior to a WRITE to bank m.

WRITE With Auto Precharge interrupted by a READ

T0

T1

T2

T3

T4

T5

T6

T7

CLK

COMMAND

BANK n

WRITE - AP

BANK n

READ - AP

BANK m

NOP

Page Active

WRITE with Burst of 4 Interrupt Burst, Write-Back

WR - BANK n

Precharge

t

tRP - BANK n

Internal States

t

RP - BANK m

BANK m

Page Active

READ with Burst of 4

Precharge

BANK n,

COL a

BANK m,

COL b

ADDRESS

DQ

DIN

a

DIN a+1

DOUT

b

DOUT b+1

CAS Latency - 3 (BANK m)

DON'T CARE

WRITE With Auto Precharge interrupted by a WRITE

T0

T1

T2

T3

T4

T5

T6

T7

CLK

COMMAND

BANK n

WRITE - AP

BANK n

WRITE - AP

BANK m

NOP

Page Active

WRITE with Burst of 4

Interrupt Burst, Write-Back

WR - BANK n

Precharge

t

RP - BANK n

Internal States

t

RP - BANK m

BANK m

Page Active

WRITE with Burst of 4

Write-Back

BANK n,

COL a

BANK m,

COL b

ADDRESS

DQ

DIN

a

DIN a+1

DIN a+2

D

IN

b

DIN b+1

DIN b+2

DIN b+3

DON'T CARE

56

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

ADVANCEDINFORMATION Rev. 00A

06/01/02

®

IS42S81600A, IS42S16800A, IS42S32400A

IS42LS81600A, IS42LS16800A, IS42LS32400A

ISSI

SINGLE READ WITH AUTO PRECHARGE

T0

T1

T2

T3

T4

T5

T6

T7

T8

t

CK

t

CL

tCH

CLK

CKE

t

CKS tCKH

t

CMS

tCMH

COMMAND

ACTIVE

NOP

READ

NOP

ACTIVE

NOP

t

CMS

t

CMH

DQM/

DQML, DQMH

t

AS

tAH

COLUMN m⁽²⁾

A0-A9, A11

A10

ROW

BANK

AS

t

AH

ENABLE AUTO PRECHARGE

ROW

AS

t

AH

BA0, BA1

BANK

t

OH

t

AC

DOUT m

DQ

t

HZ

DON'T CARE

UNDEFINED

t

RCD

RAS

RC

CAS Latency

t

RP

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

ADVANCEDINFORMATION Rev. 00A

57

06/01/02

®

IS42S81600A, IS42S16800A, IS42S32400A

IS42LS81600A, IS42LS16800A, IS42LS32400A

ISSI

READ WITH AUTO PRECHARGE

T0

T1

T2

T3

T4

T5

T6

T7

T8

t

CK

t

CL

tCH

CLK

CKE

t

CKS tCKH

t

CMS tCMH

COMMAND

ACTIVE

NOP

READ

NOP

ACTIVE

t

CMS

t

CMH

DQM/

DQML, DQMH

t

AS

tAH

COLUMN m⁽²⁾

A0-A9, A11

A10

ROW

BANK

AS

t

AH

ENABLE AUTO PRECHARGE

ROW

AS

t

AH

BA0, BA1

DQ

BANK

t

AC

t

AC

t

AC

t

AC

tHZ

DOUT

m

D

OUT m+1

D

OUT m+2

D

OUT m+3

t

LZ

t

OH

t

OH

t

OH

tOH

t

RCD

RAS

RC

CAS Latency

DON'T CARE

UNDEFINED

t

RP

58

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

ADVANCEDINFORMATION Rev. 00A

06/01/02

®

IS42S81600A, IS42S16800A, IS42S32400A

IS42LS81600A, IS42LS16800A, IS42LS32400A

ISSI

SINGLE READ WITHOUT AUTO PRECHARGE

T0

T1

T2

T3

T4

T5

T6

T7

T8

t

CK

t

CL

t

CH

CLK

CKE

t

CKS CKH

t

CMS

t

CMH

COMMAND

ACTIVE

NOP

READ

NOP

PRECHARGE

NOP

ACTIVE

NOP

t

CMS

t

CMH

DQM/

DQML, DQMH

t

AS

t

AH

COLUMN m⁽²⁾

A0-A9, A11

A10

ROW

BANK

AS

t

AH

ALL BANKS

ROW

SINGLE BANK

BANK

AS

t

AH

DISABLE AUTO PRECHARGE

BA0, BA1

DQ

BANK

t

OH

t

AC

D

OUT

m

t

LZ

t

HZ

DON'T CARE

UNDEFINED

t

RCD

RAS

RC

CAS Latency

t

RP

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

ADVANCEDINFORMATION Rev. 00A

59

06/01/02

®

IS42S81600A, IS42S16800A, IS42S32400A

IS42LS81600A, IS42LS16800A, IS42LS32400A

ISSI

READ WITHOUT AUTO PRECHARGE

T0

T1

T2

T3

T4

T5

T6

T7

T8

t

CK

t

CL

tCH

CLK

CKE

t

CKS tCKH

t

CMS tCMH

COMMAND

ACTIVE

NOP

READ

NOP

PRECHARGE

NOP

ACTIVE

t

CMS

t

CMH

DQM/

DQML, DQMH

t

AS

tAH

COLUMN m⁽²⁾

A0-A9, A11

A10

ROW

BANK

AS

t

AH

ALL BANKS

ROW

AS

t

AH

DISABLE AUTO PRECHARGE

SINGLE BANK

BANK

BA0, BA1

DQ

BANK

t

AC

t

AC

t

AC

t

AC

tHZ

DOUT

m

D

OUT m+1

DOUT m+2

D

OUT m+3

t

LZ

t

OH

t

OH

t

OH

tOH

tRCD

tRAS

t

RC

CAS Latency

DON'T CARE

UNDEFINED

t

RP

60

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

ADVANCEDINFORMATION Rev. 00A

06/01/02

®

IS42S81600A, IS42S16800A, IS42S32400A

IS42LS81600A, IS42LS16800A, IS42LS32400A

ISSI

SINGLE READ WITH AUTO PRECHARGE

T0

T1

T2

T3

T4

T5

T6

T7

T8

t

CK

t

CL

tCH

CLK

CKE

t

CKS tCKH

t

CMS

tCMH

COMMAND

ACTIVE

NOP

READ

NOP

ACTIVE

NOP

t

CMS

t

CMH

DQM/

DQML, DQMH

t

AS

tAH

COLUMN m⁽²⁾

A0-A9, A11

A10

ROW

BANK

AS

t

AH

ENABLE AUTO PRECHARGE

ROW

AS

t

AH

BA0, BA1

BANK

t

OH

t

AC

DOUT m

DQ

t

HZ

DON'T CARE

UNDEFINED

t

RCD

RAS

RC

CAS Latency

t

RP

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

ADVANCEDINFORMATION Rev. 00A

61

06/01/02

®

IS42S81600A, IS42S16800A, IS42S32400A

IS42LS81600A, IS42LS16800A, IS42LS32400A

ISSI

SINGLE WRITE - WITHOUT AUTO PRECHARGE

T0

T1

T2

T3

T4

T5

T6

T7

T8

tCK

tCL

tCH

CLK

CKE

tCKS tCKH

tCMS tCMH

NOP⁽⁴⁾

PRECHARGE

NOP

ACTIVE

NOP

COMMAND

ACTIVE

NOP

WRITE

t^CMStCMH

DQM/

DQML, DQMH

tAS tAH

COLUMN m⁽³⁾

ROW

A0-A9, A11

A10

ROW

tAS tAH

ALL BANKS

ROW

SINGLE BANK

tAS tAH

DISABLE AUTO PRECHARGE

BA0, BA1

BANK

tDS tDH

DQ

D^INm

tRCD

tWR⁽³⁾

tRP

tRAS

tRC

DON'T CARE

62

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

ADVANCEDINFORMATION Rev. 00A

06/01/02

®

IS42S81600A, IS42S16800A, IS42S32400A

IS42LS81600A, IS42LS16800A, IS42LS32400A

ISSI

WRITE - WITHOUT AUTO PRECHARGE

T0

T1

T2

T3

T4

T5

T6

T7

T8

t

CK

t

CL

tCH

CLK

CKE

t

CKS tCKH

t

CMS tCMH

COMMAND

ACTIVE

NOP

WRITE

NOP

PRECHARGE

NOP

ACTIVE

t

CMS tCMH

DQM/

DQML, DQMH

t

AS

tAH

COLUMN m⁽³⁾

ROW

BANK

A0-A9, A11

A10

ROW

AS

t

AH

ALL BANKS

ROW

AS

t

AH

SINGLE BANK

BANK

DISABLE AUTO PRECHARGE

BANK

BA0, BA1

BANK

t

DS

t

DH

t

DS

t

DH

t

DS

tDH

t

DS

tDH

DQ

DIN

m

D

IN m+

1

DIN m+

2

DIN m+3

t

RCD

RAS

RC

t

WR⁽²⁾

t

RP

DON'T CARE

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

ADVANCEDINFORMATION Rev. 00A

63

06/01/02

®

IS42S81600A, IS42S16800A, IS42S32400A

IS42LS81600A, IS42LS16800A, IS42LS32400A

ISSI

WRITE - WITH AUTO PRECHARGE

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

t

CK

t

CL

tCH

CLK

CKE

t

CKS tCKH

t

CMS

tCMH

COMMAND

ACTIVE

NOP

WRITE

NOP

ACTIVE

t

CMS tCMH

DQM/

DQML, DQMH

t

AS

tAH

COLUMN m⁽²⁾

ROW

BANK

A0-A9, A11

A10

ROW

AS

t

AH

ENABLE AUTO PRECHARGE

ROW

AS

t

AH

BA0, BA1

BANK

t

DS

t

DH

t

DS

t

DH

t

DS

tDH

t

DS

tDH

DQ

DIN

m

DIN m+

1

DIN m+

2

DIN m+3

t

RCD

RAS

RC

t

WR

tRP

DON'T CARE

64

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

ADVANCEDINFORMATION Rev. 00A

06/01/02

®

IS42S81600A, IS42S16800A, IS42S32400A

IS42LS81600A, IS42LS16800A, IS42LS32400A

ISSI

ORDERING INFORMATION - VDD = 2.5V

Commercial Range: 0°C to 70°C

Frequency

133 MHz

100 MHz

Speed(ns) Order Part No.

Package

7

IS42LS81600A-7T

54pin TSOPII

10

IS42LS81600A-10T 54pin TSOPII

Frequency

Speed(ns) Order Part No.

Package

143 MHz

7

IS42LS16800A-7B

54 pin BGA

IS42LS16800A-7T 54 Pin TSOPII

IS42LS16800A-10B 54 pin BGA

IS42LS16800A-10T 54 Pin TSOPII

100 MHz

10

Frequency

Speed(ns) Order Part No.

Package

133 MHz

7

IS42LS32400A-7B

90 pin BGA

IS42LS32400A-7T 86-Pin TSOPII

IS42LS32400A-10B 90 pin BGA

IS42LS32400A-10T 86-Pin TSOPII

100 MHz

10

ORDERING INFORMATION - VDD = 2.5V

Industrial Range: -40°C to 85°C

Frequency

133 MHz

100 MHz

Speed(ns) Order Part No.

Package

7

IS42LS81600A-7TI 54pin TSOPII

IS42LS81600A-10TI 54pin TSOPII

10

Frequency

Speed(ns) Order Part No.

Package

133 MHz

7

IS42LS16800A-7BI

54 pin BGA

IS42LS16800A-7TI 54 Pin TSOPII

100 MHz

10

IS42LS16800A-10BI 54 pin BGA

IS42LS16800A-10TI 54 Pin TSOPII

Frequency

Speed(ns) Order Part No.

Package

133 MHz

7

IS42LS32400A-7BI

90 pin BGA

IS42LS32400A-7TI 86-Pin TSOPII

100 MHz

10

IS42LS32400A-10BI 90 pin BGA

IS42LS32400A-10TI 86-Pin TSOPII

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

ADVANCEDINFORMATION Rev. 00A

65

06/01/02

®

IS42S81600A, IS42S16800A, IS42S32400A

IS42LS81600A, IS42LS16800A, IS42LS32400A

ISSI

ORDERING INFORMATION - VDD = 3.3V

Commercial Range: 0°C to 70°C

Frequency

133 MHz

100 MHz

Speed(ns) Order Part No.

Package

7

IS42S81600A-7T

IS42S81600A-10T

54pin TSOPII

10

Frequency

Speed(ns) Order Part No.

Package

133 MHz

7

IS42S16800A-7B

IS42S16800A-7T

54 pin BGA

54 Pin TSOPII

100 MHz

10

IS42S16800A-10B

54 pin BGA

IS42S16800A-10T 54 Pin TSOPII

Frequency

Speed(ns) Order Part No.

Package

133 MHz

7

IS42S32400A-7B

IS42S32400A-7T

90 pin BGA

86-Pin TSOPII

100 MHz

10

IS42S32400A-10B

90 pin BGA

IS42S32400A-10T 86-Pin TSOPII

ORDERING INFORMATION - VDD = 3.3V

Industrial Range: -40°C to 85°C

Frequency

133 MHz

100 MHz

Speed(ns) Order Part No.

Package

7

IS42S81600A-7TI

54pin TSOPII

10

IS42S81600A-10TI 54pin TSOPII

Frequency

Speed(ns) Order Part No.

Package

133 MHz

7

IS42S16800A-7BI

IS42S16800A-7TI

54 pin BGA

54 Pin TSOPII

100 MHz

10

IS42S16800A-10BI

54 pin BGA

IS42S16800A-10TI 54 Pin TSOPII

Frequency

Speed(ns) Order Part No.

Package

133 MHz

7

IS42S32400A-7BI

IS42S32400A-7TI

90 pin BGA

86-Pin TSOPII

100 MHz

10

IS42S32400A-10BI

90 pin BGA

IS42S32400A-10TI 86-Pin TSOPII

66

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

ADVANCEDINFORMATION Rev. 00A

06/01/02


型号：	IS42LS32400A-7BI
厂家：	INTEGRATED CIRCUIT SOLUTION INC
描述：	16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM 16兆×8 ， 8Meg X16和4Meg ×32 128兆位同步DRAM 内存集成电路动态存储器
文件：	总66页 (文件大小：553K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IS42LS32400A-7BI [ICSI]

相关型号：

IS42LS32400A-7T

IS42LS32400A-7TI

IS42LS32400AL-10BI

IS42LS32400AL-10BL

IS42LS32400AL-10T

IS42LS32400AL-7B

IS42LS32400AL-7BI

IS42LS32400AL-7TI

IS42LS32400AL-7TL

IS42LS32400AL-7TLI

IS42LS81600A

IS42LS81600A-10T