M1010-01I155.5200 [ICSI]
VCSO BASED CLOCK JITTER ATTENUATOR; VCSO基于时钟抖动衰减器
| 型号： | M1010-01I155.5200 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | VCSO BASED CLOCK JITTER ATTENUATOR |
| 文件： | 总8页 (文件大小：355K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
P r e l i m i n a r y I n f o r m a t i o n
Integrated
Circuit
Systems, Inc.
M1010-01
VCSO BASED CLOCK JITTER ATTENUATOR
GENERAL DESCRIPTION
PIN ASSIGNMENT (9 x 9 mm SMT)
The M1010-01 is a VCSO (Voltage Controlled SAW
Oscillator) based clock jitter
attenuator PLL designed for clock
jitter attenuation and frequency
translation. The device is ideal for
generating the transmit reference
clock for OC-12 and OC-48 optical
network systems supporting 622 -
FIN_SEL0
SEL0
SEL1
SEL2
NC
VCC
NC
nFOUT
FOUT
GND
NC
28
29
30
31
18
17
16
15
14
13
12
11
10
M1010
2,488 MHz rates. It can serve to jitter attenuate a
stratum reference clock or a recovered clock in loop
timing mode. The M1010-01 module includes a
proprietary SAW (surface acoustic wave) delay line as
part of the VCSO. This results in a high frequency,
high-Q, low phase noise oscillator that assures low
intrinsic output jitter.
32
33
34
35
36
VCC
( T o p V i e w )
DNC
DNC
NC
VCC
GND
DNC
FEATURES
◆ Ideal for OC-12/48 data clock
Figure 1: Pin Assignment
◆ Integrated SAW delay line
Example I/O Clock Frequency Combinations
Using M1010-01-155.5200
◆ Output frequencies from 150 to 175 MHz
(Specify VCSO output frequency at time of order)
Input Reference
Clock
Frequency
Input (Mfin)
Ratio
Output
Clock MHz
◆ Low phase jitter of 0.5 ps rms, typical (12kHz to 20MHz)
◆ LVPECL clock output
(MHz)
8
2
1
19.44
77.76
155.52
◆ Pin-selectable feedback and reference divider ratios,
no programming required
155.52
◆ Scalable dividers provide further adjustment of loop
bandwidth as well as jitter tolerance
Table 1: Example I/O Clock Frequency Combinations
◆ Reference clock inputs support differential LVDS,
LVPECL, as well as single-ended LVCMOS, LVTTL
◆ Single 3.3V power supply
◆ Small 9 x 9 mm SMT (surface mount) package
SIMPLIFIED BLOCK DIAGRAM
Loop
Filter
M1010
DIF_REF0
0
nDIF_REF0
R Div
VCSO
DIF_REF1
1
nDIF_REF1
M Div
Mfin Div
REF_SEL
3
2
FOUT
SEL2:0
Divider LUT
nFOUT
Mfin Divider
LUT
FIN_SEL1:0
Figure 2: Simplified Block Diagram
M1010-01 Datasheet Rev 0.4
Revised 29Sep2003
M1010-01 VCSO Based Clock Jitter Attenuator
Integrated Circuit Systems, Inc. ● Communications Modules ● www.icst.com ● tel (508) 852-5400
M1010-01
Integrated
Circuit
Systems, Inc.
VCSO BASED
C
LOCK
J
ITTER
A
TTENUATOR
P r e l i m i n a r y I n f o r m a t i o n
DETAILED BLOCK DIAGRAM
RLOOP CLOOP
RPOST
External
Loop Filter
Components
CPOST
CPOST
RLOOP CLOOP
nOP_IN OP_OUT
RPOST
M1010
OP_IN
nOP_OUT
nVC
VC
MUX
Phase
Detector
SAW Delay Line
R
IN
DIF_REF0
0
Phase
Locked
Loop
(PLL)
nDIF_REF0
R Div
R
DIF_REF1
nDIF_REF1
IN
Loop Filter
Amplifier
Phase
Shifter
1
VCSO
M Div
Mfin Divider
REF_SEL
SEL2:0
3
2
Divider LUT
FOUT
nFOUT
Mfin Divider
LUT
FIN_SEL1:0
Figure 3: Detailed Block Diagram
PIN DESCRIPTIONS
Number
1, 2, 3, 10, 14, 26
Name
GND
I/O
Ground
Configuration
Description
Power supply ground connections.
4
9
OP_IN
nOP_IN
Input
External loop filter connections.
See Figure 4, External Loop Filter, on pg. 4.
5
8
nOP_OUT
OP_OUT
Output
6
7
nVC
VC
Input
11, 18, 19, 33
VCC
Power
Power supply connection, connect to +3.3V.
12, 13, 17, 25, 32
NC
No internal connection.
15
16
FOUT
nFOUT
Output No internal terminator
Clock output pairs. Differential LVPECL.
1
20
21
nDIF_REF1
DIF_REF1
Internal pull-UP resistor
Input
Internal pull-down resistor
Reference clock input pair.
Differential LVPECL or LVDS.
1
1
Reference clock input selection. LVCMOS/LVTTL:
Logic 1 selects DIF_REF1, nDIF_REF1.
Logic 0 selects DIF_REF0, nDIF_REF0.
22
REF_SEL
Input
Input
Input
Internal pull-down resistor
1
23
24
nDIF_REF0
DIF_REF0
Internal pull-UP resistor
Reference clock input pair.
Differential LVPECL or LVDS.
1
1
Internal pull-down resistor
Input clock frequency selection. LVCMOS/LVTTL.
27
28
FIN_SEL1
FIN_SEL0
Internal pull-down resistor See Table 3, Mfin (Frequency Input) Divider Look-Up Table
(LUT) on pg. 3.
29
30
31
SEL0
SEL1
SEL2
M and R divider value selection. LVCMOS/ LVTTL.
See Table 4, SEL2:0 Look-up Table (LUT) on pg. 3.
1
Input
Internal pull-UP resistor
Do Not Connect.
34, 35, 36
DNC
Table 2: Pin Descriptions
Note 1: For typical values of internal pull-down and pull-up resistors, see “Inputs with Pull-down” and “Inputs with Pull-up”
in Table 8, DC Characteristics, on pg. 6.
M1010-01 Datasheet Rev 0.4
2 of 8
Revised 29Sep2003
Integrated Circuit Systems, Inc. ● Communications Modules ● www.icst.com ● tel (508) 852-5400
M1010-01
Integrated
Circuit
Systems, Inc.
VCSO BASED
C
LOCK
J
ITTER
A
TTENUATOR
P r e l i m i n a r y I n f o r m a t i o n
SEL2:0 Look-up Table (LUT)
PLL DIVIDER LOOK-UP TABLES
The SEL2:0 pins select the feedback and reference
divider values M and R to enable adjustment of loop
bandwidth and jitter tolerance.
Mfin (Frequency Input) Divider Look-Up Table (LUT)
The FIN_SEL1:0 pins select the feedback divider value
(“Mfin”).
SEL2:0
M
R
Description
M1010-01-155.5200
Sample Ref. Freq. (MHz) 1
0 0 0 236 236
FIN_SEL1:0
Mfin Value
0 0 1 79
0 1 0 14
79
14
0
0
1
1
0
1
0
1
8
2
1
x
19.44
77.76
155.52
0 1 1 239 239
Various divider values to adjust bandwidth
and jitter tolerance
Test mode. Do not use.
1 0 0
1 0 1
1 1 0
1 1 1
1
2
4
8
1
2
4
8
Table 3: Mfin (Frequency Input) Divider Look-Up Table (LUT)
Note 1: Example with M1010-01-155.5200.
Table 4: SEL2:0 Look-up Table (LUT)
FUNCTIONAL DESCRIPTION
The M1010-01 is a PLL (Phase Locked Loop) based
clock generator that generates output clocks synchro-
nized to one of two selectable input reference clocks.
The phase detector compares its two inputs. It then
outputs pulses to the loop filter as needed to increase or
decrease the VCSO frequency and thereby match and
lock the divider output’s frequency and phase to those
of the input reference clock.
An internal high "Q" SAW filter provides low jitter signal
performance and controls the output frequency of the
VCSO (Voltage Controlled SAW Oscillator).
Due to the narrow tuning range of the VCSO
(+200ppm), appropriate selection of all of the following
are required for the PLL be able to lock: VCSO center
frequency, input frequency, and divider selections.
A configurable frequency divider (labeled “Mfin Divider”)
provides the division options to accomodate various
reference clock frequencies.
In addition, configurable feedback and reference
dividers (the “M Divider” and “R Divider”) provide divider
value options to enable adjustment of loop bandwidth
and jitter tolerance.
Relationship Among Frequencies and Dividers
The VCSO center frequency must be specified at time
of order. The relationship between the VCSO (Fvcso)
frequency, the Mfin divider, the M divider, the R divider,
and the input reference frequency (Fin) is:
For example, the M1010-01-155.5200 (see “Ordering
Information” on pg. 8) has a 155.52MHz VCSO
frequency:
M
R
---
Fvcso = Fin × Mfin ×
The Mfin feedback divider allows an input frequency to
be the VCSO output frequency divided by 1, 2, or 8.
Therefore, for the base input frequency of 155.52MHz,
the actual input reference clock frequencies can be:
155.52, 77.76, and 19.44MHz. (See Table 3 on pg. 3.)
Clock Output
The M1010-01 provides one differential LVPECL output
pair FOUT. PECL and LVDS product options are
available; consult factory.
The PLL
The PLL uses a phase detector and configurable
dividers to synchronize the output of the VCSO with
selected reference clock.
The “Mfin Divider” and “M Divider” divide the VCSO
frequency, feeding the result into the phase detector.
The selected input reference clock is divided by the “R
Divider”. The result is fed into the other input of the
phase detector.
M1010-01 Datasheet Rev 0.4
3 of 8
Revised 29Sep2003
Integrated Circuit Systems, Inc. ● Communications Modules ● www.icst.com ● tel (508) 852-5400
M1010-01
Integrated
Circuit
Systems, Inc.
VCSO BASED
C
LOCK
J
ITTER
A
TTENUATOR
P r e l i m i n a r y I n f o r m a t i o n
PLL bandwidth is affected by the “M” value and the
“Mfin” value, as well as the VCSO frequency.
External Loop Filter
To provide stable PLL operation, the M1010-01 requires
the use of an external loop filter. This is implemented by
connecting passive external components to the device
as shown in Figure 4 below.
The various SEL1:0 settings can be used to actively
change PLL loop bandwidth in a given application. See
“SEL2:0 Look-up Table (LUT)” on pg. 3.
See Table 5, Example Loop Filter Component
Values for M1010-01-155.5200, on pg. 4.
The M1010-01 utilizes a differential analog signal path
to minimize noise coupling from the system. Because of
this, the loop filter implementation requires two identical
complementary RC filters as shown here.
PLL Simulator Tool Available
A free PC software utility is available on the ICS website
(www.icst.com). The M2000 Timing Modules PLL
Simulator is a downloadable application that simulates
PLL jitter and wander transfer characteristics. This
enables the user to set appropriate external loop
component values in a given application.
RLOOP CLOOP
RPOST
CPOST
CPOST
RLOOP CLOOP
nOP_IN OP_OUT
RPOST
OP_IN
nOP_OUT
nVC
VC
4
9
8
5
6
7
Figure 4: External Loop Filter
1
Example Loop Filter Component Values for M1010-01-155.5200
VCSO Parameters: K
= 200kHz/V, R = 2050k
Ω
, VCSO Bandwidth = 700kHz.
VCO
IN
Device Configuration
Example External Loop Filter Component Value
Nominal Performance Using These Values
FRef
(MHz)
FVCSO Mfin M, R
(MHz)
R loop
C loop
R post
C post PLL Loop Damping
Passband Peak
Value2
Bandwidth Factor Amplitude @ Center
(dB)
0.05
0.04
0.05
0.04
0.04
0.05
0.04
0.05
Freq.
1
2
1
2
8
1
4
8
6.5
6.8
6.5
6.8
6.8
6.3
6.8
6.3
10Hz
118.0kΩ
118.0kΩ
59.0kΩ
59.0kΩ
118.0kΩ
40.2kΩ
59.0kΩ
76.8kΩ
1.0µF
22.0µF
1.0µF
2.2µF
2.2µF
1.0µF
1.0µF
2.0µF
100kΩ 1000pF
200kΩ 1000pF
100kΩ 1000pF
100kΩ 1000pF
200kΩ 1000pF
40.2kΩ 1000pF
100kΩ 1000pF
200kΩ 1000pF
270Hz
134Hz
610Hz
267Hz
134Hz
740Hz
267Hz
180Hz
19.44 155.52
77.76 155.52
8
2
4Hz
20Hz
10Hz
10Hz
20Hz
10Hz
8Hz
155.52 155.52
1
Table 5: Example Loop Filter Component Values for M1010-01-155.5200
Note 1: KVCO , VCSO Bandwidth, M Divider Value, and External Loop Filter Component Values determine Loop Bandwidth, Damping Factor,
and Passband Peaking. For PLL Simulator software, go to www.icst.com.
Note 2: For loop timing applications, the recommended value for the product of “Mfin” x “M” is 8 or higher.
M1010-01 Datasheet Rev 0.4
4 of 8
Revised 29Sep2003
Integrated Circuit Systems, Inc. ● Communications Modules ● www.icst.com ● tel (508) 852-5400
M1010-01
Integrated
Circuit
Systems, Inc.
VCSO BASED
C
LOCK
J
ITTER
A
TTENUATOR
P r e l i m i n a r y I n f o r m a t i o n
1
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter
Rating
Unit
VI
Inputs
-0.5 to VCC +0.5
-0.5 to VCC +0.5
4.6
V
VO
VCC
TS
Outputs
V
V
Power Supply Voltage
Storage Temperature
-45 to +100
oC
Table 6: Absolute Maximum Ratings
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional operation of product at these conditions
or any conditions beyond those listed in Recommended Conditions of Operation, DC Characteristics, or
AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability
.
RECOMMENDED CONDITIONS OF OPERATION
Symbol Parameter
Min
Typ
Max Unit
VCC
Positive Supply Voltage
3.135
3.3
3.465
V
TA
Ambient Operating Temperature
oC
oC
0
Commercial
Industrial
+70
+85
-40
Table 7: Recommended Conditions of Operation
M1010-01 Datasheet Rev 0.4
5 of 8
Revised 29Sep2003
Integrated Circuit Systems, Inc. ● Communications Modules ● www.icst.com ● tel (508) 852-5400
M1010-01
Integrated
Circuit
Systems, Inc.
VCSO BASED
C
LOCK
J
ITTER
A
TTENUATOR
P r e l i m i n a r y I n f o r m a t i o n
ELECTRICAL SPECIFICATIONS
DC Characteristics
Unless stated otherwise, VCC
=
3.3V +
5
%,TA = 0 oC to +70 oC (commercial), FVCSO = FOUT
TA = -40 oC to +85 oC (industrial)
= 150-175MHz, Outputs terminated with 50Ω to VCC - 2V
Symbol Parameter
Power Supply VCC Positive Supply Voltage
ICC
IIH
Min
3.135
Typ
3.3
Max Unit Conditions
3.465
V
162
Power Supply Current
Input High Current
mA
µA
µA
µA
µA
V
DIF_REF0, DIF_REF1
nDIF_REF0, nDIF_REF1
DIF_REF0, DIF_REF1
nDIF_REF0, nDIF_REF1
150
5
Differential
Inputs
-5
-150
0.15
0.5
2
IIL
Input Low Current
VP-P
VCMR
VIH
VIL
CIN
IIH
Peak to Peak Input
Common Mode Input
Input High Voltage
Input Low Voltage
DIF_REF0, nDIF_REF0,
DIF_REF1, nDIF_REF1
V
-
V
cc
LVCMOS /
LVTTL
Inputs
V
+ 0.3 V
cc
REF_SEL,
FIN_SEL1, FIN_SEL0,
SEL2, SEL1, SEL0
0.8
-0.3
V
4
Input Capacitance
Input High Current
Input Low Current
Internal Pull-down Resistor
Input High Current
Input Low Current
Internal Pull-up Resistor
Input Capacitance
pF
VCC = VIN
3.456V
=
Inputs with
Pull-down
150 µA
µA
All Inputs except nDIF_REF1:0,
SEL2:0
IIL
-5
51
51
R
kΩ
pulldown
VCC = 3.456V
VIN = 0 V
Inputs with
Pull-up
IIH
IIL
R
5
µA
µA
kΩ
pF
nDIF_REF1, nDIF_REF0,
SEL2, SEL1, SEL0
-150
pullup
All Inputs
4
All Inputs
CIN
Differential
Outputs
VOH
VOL
VP-P
Output High Voltage
V
- 1.4
- 2.0
V
V
- 1.0 V
- 1.7 V
cc
cc
FOUT, nFOUT
1
Output Low Voltage
V
cc
cc
0.4
0.85
Peak to Peak Output Voltage
V
Table 8: DC Characteristics
Note 1: Single-ended measurement. See Figure 5, Output Rise and Fall Time on pg. 7.
M1010-01 Datasheet Rev 0.4
6 of 8
Revised 29Sep2003
Integrated Circuit Systems, Inc. ● Communications Modules ● www.icst.com ● tel (508) 852-5400
M1010-01
Integrated
Circuit
Systems, Inc.
VCSO BASED
C
LOCK
J
ITTER
A
TTENUATOR
P r e l i m i n a r y I n f o r m a t i o n
ELECTRICAL SPECIFICATIONS (CONTINUED)
AC Characteristics
Unless stated otherwise, VCC
=
3.3V +
5
%,TA = 0 oC to +70 oC (commercial), FVCSO = FOUT
TA = -40 oC to +85 oC (industrial)
= 150-175MHz, Outputs terminated with 50Ωto VCC - 2V
Symbol Parameter
Min
Typ
Max Unit Conditions
18.75
175
DIF_REF0, nDIF_REF0,
DIF_REF1, nDIF_REF1
FIN
Input Frequency
MHz
50
MHz
MHz
FOUT, nFOUT
150
175
FOUT
APR
Output Frequency
VCSO Pull-Range
Commercial
Industrial
±120
±50
±200
±150
200
ppm
ppm
KVCO
RIN
VCO Gain
kHz/V
PLL Loop
Constants
2050
700
Internal Loop Resistor
kΩ
1
BWVCSO VCSO Bandwidth
kHz
Φn
Single Side Band
Phase Noise
1kHz Offset
-72
-94
-123
0.5
0.5
50
dBc/Hz
dBc/Hz
dBc/Hz
ps
Fin=19.44_MHz
Mfin=8,
M=x, R=x
10kHz Offset
PhaseNoise
and Jitter
@155.52MHz
100kHz Offset
J(t)
Jitter (rms)
@155.52MHz
12kHz to 20MHz
50kHz to 80MHz
ps
2
45
55
odc
tR
Output Duty Cycle
%
2
Output Rise Time
for FOUT, nFOUT
325
450
450
500
ps
ps
20% to 80%
20% to 80%
2
Output Fall Time
for FOUT, nFOUT
325
500
tF
Table 9: AC Characteristics
Note 1: Parameters needed for PLL Simulator software; see Table 5, Example Loop Filter Component Values for M1010-01-155.5200 on pg. 4.
Note 2: See Parameter Measurement Information on pg. 7.
PARAMETER MEASUREMENT INFORMATION
Output Rise and Fall Time
Output Duty Cycle
nFOUT
FOUT
80%
80%
VP-P
tPW
(Output Pulse Width)
20%
t
F
20%
Clock Output
t
R
tPERIOD
t
PW
odc =
t
PERIOD
Figure 6: Output Duty Cycle
Figure 5: Output Rise and Fall Time
M1010-01 Datasheet Rev 0.4
7 of 8
Revised 29Sep2003
Integrated Circuit Systems, Inc. ● Communications Modules ● www.icst.com ● tel (508) 852-5400
P r e l i m i n a r y I n f o r m a t i o n
VCSO BASED
M1010-01
Integrated
Circuit
Systems, Inc.
CLOCK
J
ITTER
A
TTENUATOR
DEVICE PACKAGE - 9 x 9mm CERAMIC LEADLESS CHIP CARRIER
Mechanical Dimensions:
Figure 7: Device Package - 9 x 9mm Ceramic Leadless Chip Carrier
ORDERING INFORMATION
VCSO Freq (MHz)
Temperature
Order Part Number
commercial
industrial
M1010-01- 155.5200
155.52
M1010-01
M1010-01- 156.2500
M1010-01 156.2500
I155.5200
commercial
industrial
156.25
I
Table 10: Ordering Information
Consult ICS for the availability of other VCSO frequencies.
Part Number:
M1010-01-xxx.xxxx
Device Number
Temperature
0
to +70 o
C
(commercial)
“I-”==- 40 to +85 o
C (industrial)
VCSO Frequency (MHz)
Consult ICS for available VCSO frequencies
Figure 8: Part Numbering Scheme
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS)
assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would
result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary
environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any
circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or
critical medical instruments.
M1010-01 Datasheet Rev 0.4
8 of 8
Revised 29Sep2003
Integrated Circuit Systems, Inc. ● Communications Modules ● www.icst.com ● tel (508) 852-5400
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