MK2732-05S [ICSI]

Low Phase Noise VCXO+Multiplier; 低相位噪声压控+乘法器
MK2732-05S
型号: MK2732-05S
厂家: INTEGRATED CIRCUIT SOLUTION INC    INTEGRATED CIRCUIT SOLUTION INC
描述:

Low Phase Noise VCXO+Multiplier
低相位噪声压控+乘法器

石英晶振 压控振荡器
文件: 总4页 (文件大小:46K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
MK2732-05  
Low Phase Noise VCXO+Multiplier  
Features  
Description  
The MK2732-05 is a low cost, low jitter, high  
performance VCXO and PLL clock synthesizer  
designed to replace expensive discrete VCXOs  
and multipliers. The on-chip Voltage Controlled  
Crystal Oscillator (VCXO) accepts a 0 to 3 V  
input voltage to cause the output clocks to vary by  
±100 ppm. Using ICS/MicroClock’s patented  
VCXO and analog Phase-Locked Loop (PLL)  
techniques, the device uses an inexpensive 10 MHz  
to 14.318 MHz pullable crystal input to produce  
one or two output clocks.  
• Packaged in 16 pin narrow SOIC  
• Replaces a VCXO and multiplier  
• Uses an inexpensive pullable crystal  
• Output clocks up to 85 MHz  
• On-chip patented VCXO with pull range of  
200 ppm (±100 ppm) minimum  
• VCXO tuning voltage of 0 to 3 V  
• Zero ppm synthesis error in both clocks  
• 25 mA output drive capability at TTL levels  
• Advanced, low power, sub-micron CMOS process  
• 5 V operating voltage for core, ability to run  
output clocks at 3.3V or 5V  
ICS manufactures the largest variety of Set-Top  
Box and multimedia clock synthesizers for all  
applications. Consult ICS to eliminate VCXOs,  
crystals and oscillators from your board.  
Block Diagram  
VDD5  
VDDIO  
3
S2:S0  
Output  
Buffer  
VIN  
CLK1  
CLK2  
PLL/Clock  
Synthesis  
Circuitry  
10-14 MHz X1  
pullable  
crystal  
Voltage  
Controlled  
Crystal  
Output  
Buffer  
Oscillator  
X2  
OE  
MDS 2732-05 D  
1
Revision 122799  
Printed 11/16/00  
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA •95126•(408) 295-9800 tel• www.icst.com  
MK2732-05  
Low Phase Noise VCXO+Multiplier  
Pin Assignment  
Clock Select Table  
S2 S1  
S0  
0
CLK1  
REF/4  
OFF  
OFF  
OFF  
OFF  
OFF  
Test  
CLK2  
REF/2  
x0.666  
x2.6666  
x4  
MK2732-05  
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
16 X2  
15 NC  
14 S1  
X1  
1
2
3
4
5
6
7
8
M
1
VDD5  
0
VDD5  
VIN  
M
1
x1.5  
x1.3333  
Test  
x4  
GND  
13  
12 CLK2  
GND  
GND  
S2  
0
11 VDDIO  
M
1
OFF  
OFF  
OFF  
OFF  
OFF  
x2  
S0  
10  
9
0
x3  
OE  
CLK1  
M
1
x5  
16 pin narrow (150 mil) SOIC  
x6  
0=connect directly to GND, 1=connect directly to  
VDDIO, OFF=output stopped low.  
Pin Descriptions  
Number  
Name  
X1  
Type Description  
1
2, 3  
4
XI  
P
Crystal connection. Connect to a pullable crystal of 10-14.318 MHz.  
Core VDD. Connect to +5V.  
VDD5  
VIN  
GND  
S2  
VI  
P
Voltage Input to VCXO. Zero to 3V signal which controls the frequency of the VCXO.  
Connect to ground.  
5, 6, 13  
7
I
Select input #2. Selects outputs per table above. Do not exceed VDDIO.  
Output Enable. Tri-states outputs when low. Do not exceed VDDIO.  
Clock Output #1 per table above. Amplitude = VDDIO.  
8
OE  
I
9
CLK1  
S0  
O
TI  
P
10  
11  
12  
14  
15  
16  
Select input #0. Selects outputs per table above. Do not exceed VDDIO.  
Input and output VDD. Connect to +3.3V or +5V. Clock amplitude matches this voltage.  
Clock Output #2 per table above. Amplitude = VDDIO.  
VDDIO  
CLK2  
S1  
O
I
Select input #1. Selects outputs per table above. Do not exceed VDDIO.  
Nothing is connected internally to this pin.  
NC  
-
X2  
XO  
Crystal connection. Connect to a pullable crystal of 10-14.318 MHz.  
Key: I = Input with internal pull-up resistor; TI = tri-level input; O = output; P = power supply connection;  
VI = analog voltage input; XI, XO = crystal pins.  
External Components  
The MK2732-05 requires a minimum number of external components for proper operation. Decoupling  
capacitors of 0.1µF should be connected between VDD5 and GND on pins 3 and 5, and VDDIO and  
GND on pins 11 and 13, as close to the MK2732-05 as possible. A series termination resistor of 33 Wmay  
be used for each clock output. The input crystal must be connected as close to the chip as possible. The  
input crystal should be a fundamental mode, parallel resonant, pullable, AT cut. A crystal with 14 pF load  
capacitance is recommended. Consult ICS/MicroClock for recommended suppliers. IMPORTANT -  
consult the application note MAN05 for layout guidelines.  
MDS 2732-05 D  
2
Revision 122799  
Printed 11/16/00  
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA •95126•(408) 295-9800 tel• www.icst.com  
MK2732-05  
Low Phase Noise VCXO+Multiplier  
Electrical Specifications  
Parameter  
Conditions  
Minimum  
Typical  
Maximum Units  
ABSOLUTE MAXIMUM RATINGS (note 1)  
Supply voltage, VDD  
Referenced to GND  
7
VDD+0.5  
70  
V
V
Inputs and Clock Outputs  
Ambient Operating Temperature  
Soldering Temperature  
Storage temperature  
Referenced to GND  
Max of 10 seconds  
-0.5  
0
°C  
°C  
°C  
260  
-65  
150  
DC CHARACTERISTICS (VDD5 = 5.0V unless noted)  
Core Operating Voltage, VDD5  
4.75  
3.15  
3.5  
5.0  
3.3  
2.5  
2.5  
5.25  
V
V
I/O Operating Voltage, VDDIO  
VDD5  
Input High Voltage, VIH, X1 pin only  
Input Low Voltage, VIL, X1 pin only  
V
1.5  
0.8  
0.5  
0.4  
V
Input High Voltage, VIH, binary inputs  
Input Low Voltage, VIL, binary inputs  
Input High Voltage, VIH, trinary input  
Input Low Voltage, VIL, trinary input  
Output High Voltage, VOH  
S2, S1, OE  
S2, S1, OE  
S0, pin 10  
2
V
V
VDDIO-0.5  
2.4  
V
S0, pin 10  
V
IOH=-25mA  
IOL=25mA  
IOH=-8mA  
No Load  
V
Output Low Voltage, VOL  
V
Output High Voltage, VOH, CMOS level  
Operating Supply Current, IDD  
Short Circuit Current  
VDDIO-0.4  
V
19  
±100  
7
mA  
mA  
pF  
ppm  
V
Each output  
S2:S0, OE  
Both clocks  
Input Capacitance  
Frequency synthesis error  
0
3
VIN, VCXO control voltage  
0
AC CHARACTERISTICS (VDD5 = 5.0V unless noted)  
Input Crystal Frequency  
10  
14.31818  
85.9  
1.5  
MH z  
MH z  
ns  
Output Clock Frequency  
2.5  
Output Clock Rise Time  
Output Clock Fall Time  
Output Clock Duty Cycle  
Maximum Absolute Jitter  
Phase Noise, relative to carrier  
Output pullability, note 2  
0.8 to 2.0V  
2.0 to 0.8V  
At VDDIO/2  
1.5  
ns  
40  
60  
%
±100  
-115  
ps  
10 kHz offset  
dBc/Hz  
ppm  
0V £ VIN £ 3V  
±100  
Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged  
exposure to levels above the operating limits but below the Absolute Maximums may affect device reliability.  
2. With an ICS/MicroClock approved pullable crystal.  
Pullable Crystal Specifications:  
Correlation (load) Capacitance  
CO/C1  
14 pF  
240 max  
35 W max  
0 to 70 °C  
±20 ppm  
±50 ppm  
ESR  
Operating Temperature  
Initial Accuracey  
Temperature plus Aging Stability  
MDS 2732-05 D  
3
Revision 122799  
Printed 11/16/00  
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA •95126•(408) 295-9800 tel• www.icst.com  
MK2732-05  
Low Phase Noise VCXO+Multiplier  
Package Outline and Package Dimensions  
(For current dimensional specifications, see JEDEC Publication No. 95.)  
16 pin SOIC narrow  
Inches  
Millimeters  
Symbol  
A
Min  
Max  
Min  
1.35  
0.10  
0.33  
1.91  
9.80  
3.80  
1.27 BSC  
5.80  
0.25  
0.41  
Max  
0.0532 0.0688  
0.0040 0.0098  
0.0130 0.0200  
1.75  
0.24  
0.51  
2.40  
10.00  
4.00  
E
H
A1  
B
C
0.075  
0.098  
D
E
e
0.3859 0.3937  
0.1497 0.1574  
.050 BSC  
H
h
0.2284 0.2440  
0.0099 0.0195  
0.0160 0.0500  
6.20  
0.50  
1.27  
h x 45°  
D
L
A
C
A1  
B
e
L
Ordering Information  
Part/Order Number  
MK2732-05S  
Marking  
Shipping packaging  
tubes  
Package  
Temperature  
0-70 °C  
MK2732-05S  
MK2732-05S  
16 pin SOIC  
16 pin SOIC  
MK2732-05STR  
tape and reel  
0-70 °C  
Revision history:  
Version Revision  
Comments  
Original  
A
B
10308  
12078  
CLK1 and CLK2 functions switched in 000 address, changed from x0.75 to x0.666 in 00M address,  
changed name of VDD3.3 to VDDIO.  
C
D
4289  
Added jitter spec, changed VDD on VIH and VOH to VDDIO, lowered IDD. Added L dimension,  
changed address. Eliminated “Preliminary”.  
Changed to JEDEC dimensions. Changed VDD to ±5%. Added Pullable Crystal Specifications.  
12279  
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its  
use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is  
intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary  
environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does  
not authorize or warrant any ICS product for use in life support devices or critical medical instruments.  
MDS 2732-05 D  
4
Revision 122799  
Printed 11/16/00  
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA •95126•(408) 295-9800 tel• www.icst.com  

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