MK3805RI [ICSI]

Buffer/Clock Driver; 缓冲器/时钟驱动器


型号：	MK3805RI
厂家：	INTEGRATED CIRCUIT SOLUTION INC
描述：	Buffer/Clock Driver 缓冲器/时钟驱动器时钟驱动器逻辑集成电路光电二极管
文件：	总6页 (文件大小：123K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MK3805

Buffer/Clock Driver

Description

Features

The MK3805 is a non-inverting clock driver/buffer

providing two independent banks of four outputs each.

These buffers have a tri-state output enable input

(active low) with 1-input, 5-output configuration per

group. The skew between the outputs of the same

package is 0.5 ns and the skew between the outputs of

different packages is 0.8 ns. The maximum input to

output delay is 4.5 ns.

• Packaged in 20-pin SSOP

• Five outputs for each bank with one clock input

• Two separate banks of five outputs each

• Advanced, low-power, CMOS process

• Ten output clocks

• Two separate inputs

• Industrial temperature range -40°C to +85°C

• Hysteresis on all inputs

Block Diagram

VDD

OEA

INA

OA0-4

OEB

INB

OB0-4

MON

GND

MDS 3805 B

Revision 031104

Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com

MK3805

Buffer/Clock Driver

Pin Assignment

Truth Table

Inputs

Outputs

VCC

OA0

OA1

OA2

GND

OA3

OA4

VCC

OB0

OEA, OEB

INA, INB

OAN, OBN

MON

OB1

OB2

GND

OB3

OB4

MON

OEB

INB

GND

OEA

INA

20 pin (150 mil) SSOP/20 pin (300mil) SOIC

Pin Descriptions

Number

Name

Type

Pin Description

VCC

OA0

OA1

OA2

GND

OA3

OA4

GND

OEA

INA

Power

Connect to +3.3 V

Output Clock output.

Power

Connect to ground.

Output Clock output.

Power

Input

Connect to ground.

Tri state output enable input (active low).

Clock input.

INB

Clock input.

OEB

MON

OB4

OB3

GND

OB2

OB1

OB0

VCC

Tri state output enable input (active low).

Output Monitor output.

Output Clock output.

Power

Connect to ground.

Output Clock output.

Power

Connect to +3.3 V

MDS 3805 B

Revision 031104

Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com

MK3805

Buffer/Clock Driver

External Components

PCB Layout Recommendations

The MK3805 requires a minimum number of external

components for proper operation.

For optimum device performance and lowest output

phase noise, the following guidelines should be

observed.

Decoupling Capacitors

1) The 0.01µF decoupling capacitors should be

mounted on the component side of the board as close

to the VDD pins as possible. No vias should be used

between the decoupling capacitors and VDD pins. The

PCB trace to VDD pin should be kept as short as

possible, as should the PCB trace to the ground via.

Decoupling capacitors of 0.01µF must be connected

between VDD and GND, as close to these pins as

possible. For optimum device performance, the

decoupling capacitors should be mounted on the

component side of the PCB. Avoid the use of vias in the

decoupling circuit.

2) To minimize EMI, the 33Ω series termination resistor

(if needed) should be placed close to the clock output.

Series Termination Resistor

3) An optimum layout is one with all components on the

same side of the board, minimizing vias through the

signal layers. Other signal traces should be routed

away from the MK3805. This includes signal traces just

underneath the device, or on layers adjacent to the

ground plane layer used by the device.

When the PCB trace between the clock outputs and the

loads are over 1 inch, series termination should be

used. To series terminate a 50Ω trace (a commonly

used trace impedance) place a 33Ω resistor in series

with the clock line, as close to the clock output pin as

possible. The nominal impedance of the clock output is

20Ω.

Absolute Maximum Ratings

Stresses above the ratings listed below can cause permanent damage to the MK3805. These ratings,

which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of

the device at these or any other conditions above those indicated in the operational sections of the

specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can

affect product reliability. Electrical parameters are guaranteed only over the recommended operating

temperature range.

Item

Rating

Supply Voltage, VDD

All Inputs and Outputs

7 V

-0.5 V to VDD+0.5 V

-40 to +85°C

-65 to +150°C

125°C

Ambient Operating Temperature

Storage Temperature

Junction Temperature

Soldering Temperature

260°C

MDS 3805 B

Revision 031104

Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com

MK3805

Buffer/Clock Driver

Recommended Operation Conditions

Parameter

Min.

-40

Typ.

Max.

+85

Units

°C

Ambient Operating Temperature

Power Supply Voltage (measured in respect to GND)

+3.13

+3.3

+3.46

DC Electrical Characteristics

Unless stated otherwise, VDD = 3.3 V 5%, Ambient Temperature -40°C to +85°C

Parameter

Symbol

VDD

Conditions

Min.

Typ.

3.3

Max. Units

Operating Voltage

3.13

3.46

Supply Current

IDD

No load, OEA,OEB

GND, fo=10MHz, 50%

duty cycle

3.3

IDD

ICC

No load, OEA,OEB

GND, fo=2.5MHz,

50% duty cycle

1.8

Quiescent Current

Input High Voltage

Input Low Voltage

µA

0.8

Output High Voltage

Output Low Voltage

Short Circuit Current

Input Capacitance

Nominal Output Impedance

Input Hysteresis

= -4 mA

= -12 mA

= 12 mA

VDD-0.4

2.4

0.4

CLK output

Ω

150

MDS 3805 B

Revision 031104

Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com

MK3805

Buffer/Clock Driver

AC Electrical Characteristics

Unless stated otherwise, VDD = 3.3 V 5%, Ambient Temperature -40°C to +85°C

Parameter

Symbol

Conditions

Min.

Typ. Max. Units

Skew between outputs of same

package)

tsk

CL=50 pF, RL=500Ω

0.5

(o)

Skew between outputs of

different packages at same

temp (same transition)

tsk

CL=50 pF, RL=500Ω

0.8

(t)

Propagation Delay INA to OAN

INB to OBN

CL=50 pF, RL=500Ω

1.5

4.5

PLH

PHL

Output Rise Time

0.8 V to 2.0 V

Output Fall Time

2.0 V to 0.8 V

Output Enable Time

OEA to OAN, CL=50 pF, RL=500Ω

OEB to OBN

1.5

6.2

5.0

Output Disable Time

OEA to OAN, CL=50 pF, RL=500Ω

OEB to OBN

Duty Cycle Measured at VDD/2

Operating Frequency

CL=50 pF, RL=500Ω

100

MHz

MDS 3805 B

Revision 031104

Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com

MK3805

Buffer/Clock Driver

Package Outline and Package Dimensions (20-pin SSOP, 150Mil. Body)

Package dimensions are kept current with JEDEC Publication No. 95

Millimeters

Inches

Min

Symbol

Min

Max

1.75

0.25

1.50

0.30

0.25

8.75

6.20

4.00

Max

.069

.010

.059

0.012

.010

.344

.244

.157

1.35

0.10

.053

.0040

0.008

.007

.337

.228

.150

INDEX

AREA

0.20

0.18

8.55

5.80

3.80

1 2

0.635 Basic

0.025 Basic

0.40

0°

1.27

8°

.016

0°

.050

8°

- C -

SEATING

PLANE

.10 (.004)

Ordering Information

Part / Order Number

Marking

Shipping

packaging

Package

Temperature

MK3805RI

Tubes

20-pin SSOP

-40 to +85° C

MK3805RIT

Tape and Reel

While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS)

assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would

result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial

applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary

environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any

circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or

critical medical instruments.

MDS 3805 B

Revision 031104

Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com

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