ICS843001AGT [ICSI]
FEMTO CLOCKS CRYSTAL-TO- 3.3V LVPECL CLOCK GENERATOR; FEMTO CLOCKS CRYSTAL - TO- 3.3V LVPECL时钟发生器
| 型号： | ICS843001AGT |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | FEMTO CLOCKS CRYSTAL-TO- 3.3V LVPECL CLOCK GENERATOR |
| 文件： | 总15页 (文件大小：246K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS843001
Integrated
Circuit
Systems, Inc.
F
EMTO
C
LOCKS™ CRYSTAL
-TO-
3.3V LVPECL CLOCK
GENERATOR
GENERAL DESCRIPTION
FEATURES
The ICS843001 is a Fibre Channel Clock Generator • 1 differential 3.3V LVPECL output
ICS
and a member of the HiPerClocksTM family of high
performance devices from ICS. The ICS843001
uses either a 26.5625MHz or a 23.4375 crystal to
synthesize 106.25MHz, 187.5MHz or 212.5MHz,
• Crystal oscillator interface designed for 23.4375MHz or
26.5625MHz, 18pF parallel resonant crystal
HiPerClockS™
• Selectable 106.25MHz, 187.5MHz or 212.5MHz
output frequency
using the FREQ_SEL pin.The ICS843001 has excellent <1ps
phase jitter performance, over the 637KHz – 10MHz integration
range. The ICS843001 is packaged in a small 8-pin TSSOP,
making it ideal for use in systems with limited board space.
• VCO range: 560MHz - 680MHz
• RMS phase jitter @ 106.255MHz, using a 26.5625MHz crystal
(637KHz - 10MHz): 0.74ps (typical)
• RMS phase noise at 106.25MHz
Phase noise:
Offset
Noise Power
100Hz ............... -95.2 dBc/Hz
1KHz ..............-118.7 dBc/Hz
10KHz ..............-129.1 dBc/Hz
100KHz ..............-129.6 dBc/Hz
• 3.3V operating supply
• -30°C to 85°C ambient operating temperature
FUNCTION TABLE
Inputs
Output Frequencies
Crystal Frequency FREQ_SEL
26.5625MHz
26.5625MHz
23.4375MHz
0
1
1
106.25MHz (Default)
212.5MHz
187.5MHz
BLOCK DIAGRAM
PIN ASSIGNMENT
(Pulldown)
FREQ_SEL
VCCA
VEE
VCC
1
2
3
4
8
7
6
5
Q0
XTAL_OUT
XTAL_IN
nQ0
1
0
÷3
÷6
VCO
XTAL_IN
OSC
XTAL_OUT
nQ0
Q0
FREQ_SEL
Phase
Detector
637.5MHz w/
26.5625MHz Ref.
ICS843001
8-Lead TSSOP
4.40mm x 3.0mm x 0.925mm package body
M = ÷24 (fixed)
G Package
TopView
843001AG
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REV. B OCTOBER 13, 2004
1
ICS843001
Integrated
Circuit
Systems, Inc.
F
EMTO
C
LOCKS™ CRYSTAL
-TO-
3.3V LVPECL CLOCK
GENERATOR
TABLE 1. PIN DESCRIPTIONS
Number
Name
VCCA
VEE
Type
Description
1
2
Power
Power
Analog supply pin.
Negative supply pin.
3,
4
XTAL_OUT,
XTAL_IN
Crystal oscillator interface. XTAL_IN is the input,
XTAL_OUT is the output.
Input
5
6, 7
8
FREQ_SEL
nQ0, Q0
VCC
Input
Output
Power
Pulldown Frequency select pin. LVCMOS/LVTTL interface levels.
Differential clock outputs. LVPECL interface levels.
Core supply pin.
NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical
Maximum Units
Input Capacitance
Input Pulldown Resistor
4
pF
RPULLDOWN
51
KΩ
843001AG
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REV. B OCTOBER 13, 2004
2
ICS843001
Integrated
Circuit
Systems, Inc.
F
EMTO
C
LOCKS™ CRYSTAL
-TO-
3.3V LVPECL CLOCK
GENERATOR
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
CC
Inputs, V
-0.5V to VCC + 0.5V
I
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
PackageThermal Impedance, θ
101.7°C/W (0 mps)
-65°C to 150°C
JA
StorageTemperature, T
STG
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V 5ꢀ, TA = -30°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum Units
VCC
VCCA
ICCA
IEE
Core Supply Voltage
3.465
3.465
12
V
Analog Supply Voltage
Analog Supply Current
Power Supply Current
3.135
3.3
V
included in IEE
mA
mA
93
TABLE 3B. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = 3.3V 5ꢀ, TA = -30°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VIH
VIL
IIH
Input High Voltage
2
VCC + 0.3
0.8
V
V
Input Low Voltage
-0.3
Input High Current FREQ_SEL
Input Low Current FREQ_SEL
VCC = VIN = 3.465V
150
µA
µA
IIL
VCC = 3.465V, VIN = 0V
-5
TABLE 3C. LVPECL DC CHARACTERISTICS, VCC = 3.3V 5ꢀ, TA = -30°C TO 85°C
Symbol
VOH
Parameter
Test Conditions
Minimum
Typical
Maximum Units
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
VCC - 1.4
VCC - 2.0
0.6
VCC - 0.9
VCC - 1.7
1.0
V
V
V
VOL
VSWING
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.
TABLE 4. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
23.4375
Typical Maximum Units
Fundamental
Mode of Oscillation
Frequency
26.5625
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
50
7
pF
843001AG
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REV. B OCTOBER 13, 2004
3
ICS843001
Integrated
Circuit
Systems, Inc.
F
EMTO
C
LOCKS™ CRYSTAL
-TO-
3.3V LVPECL CLOCK
GENERATOR
TABLE 5. AC CHARACTERISTICS, VCC = 3.3V 5ꢀ, TA = -30°C TO 85°C
Symbol Parameter
Test Conditions
FREQ_SEL = 1
Minimum Typical Maximum Units
186.67
93.33
226.66
113.33
MHz
MHz
ps
fOUT
Output Frequency
FREQ_SEL = 0
212.5MHz, (637KHz to 10MHz)
187.5MHz, (1.875MHz to 20MHz)
106.25MHz, (637KHz to 10MHz)
20ꢀ to 80ꢀ
0.67
0.52
0.74
RMS Phase Jitter, (Random);
NOTE 1
tjit(Ø)
ps
ps
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
300
48
600
52
ps
FSEL = 0
ꢀ
FSEL = 1
45
55
ꢀ
NOTE 1: Please refer to Phase Noise Plot.
843001AG
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REV. B OCTOBER 13, 2004
4
ICS843001
Integrated
Circuit
Systems, Inc.
F
EMTO
C
LOCKS™ CRYSTAL
-TO-
3.3V LVPECL CLOCK
GENERATOR
TYPICAL PHASE NOISE AT 106.25MHZ
0
-10
-20
Fibre Channel Filter
-30
-40
106.25MHz
RMS Phase Jitter (Random)
637Khz to 10MHz = 0.74ps (typical)
-50
-60
-70
-80
-90
Raw Phase Noise Data
-100
-110
-120
-130
-140
-150
-160
-170
-180
Phase Noise Result by adding
Fibre Channel Filter to raw data
-190
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
TYPICAL PHASE NOISE AT 212.5MHZ
0
-10
-20
Fibre Channel Filter
-30
-40
-50
212.5MHz
RMS Phase Noise Jitter
637K to 10MHz = 0.67ps (typical)
-60
-70
-80
-90
Raw Phase Noise Data
-100
-110
-120
-130
-140
-150
-160
-170
-180
Phase Noise Result by adding
Fibre Channel Filter to raw data
-190
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
843001AG
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REV. B OCTOBER 13, 2004
5
ICS843001
Integrated
Circuit
Systems, Inc.
F
EMTO
C
LOCKS™ CRYSTAL
-TO-
3.3V LVPECL CLOCK
GENERATOR
TYPICAL PHASE NOISE AT 187.5MHZ
0
-10
-20
10 Gigabit Ethernet Filter
-30
-40
187.5MHz
RMS Phase Noise Jitter
1.875MHz to 20MHz = 0.52ps (typical)
-50
-60
-70
-80
-90
Raw Phase Noise Data
-100
-110
-120
-130
-140
-150
-160
-170
-180
Phase Noise Result by adding
10 Gigabit Ethernet Filter to raw data
-190
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
843001AG
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REV. B OCTOBER 13, 2004
6
ICS843001
Integrated
Circuit
Systems, Inc.
F
EMTO
C
LOCKS™ CRYSTAL
-TO-
3.3V LVPECL CLOCK
GENERATOR
PARAMETER MEASUREMENT INFORMATION
2V
Phase Noise Plot
SCOPE
VCC
Qx
Phase Noise Mask
LVPECL
VEE
nQx
Offset Frequency
f1
f2
-1.3V 0.165V
RMS Jitter = Area Under the Masked Phase Noise Plot
3.3V OUTPUT LOAD AC TEST CIRCUIT
RMS PHASE JITTER
nQ0
80ꢀ
tF
80ꢀ
tR
Q0
VSWING
20ꢀ
Pulse Width
tPERIOD
Clock
Outputs
20ꢀ
tPW
odc =
tPERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
OUTPUT RISE/FALL TIME
843001AG
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REV. B OCTOBER 13, 2004
7
ICS843001
Integrated
Circuit
Systems, Inc.
F
EMTO
CLOCKS™ CRYSTAL- -
TO
3.3V LVPECL CLOCK
GENERATOR
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise.The ICS843001 provides sepa-
rate power supplies to isolate any high switching
noise from the outputs to the internal PLL.VCC, and VCCA should
be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 1 illustrates how
a 10Ω resistor along with a 10µF and a .01µF bypass
capacitor should be connected to each VCCA pin.
3.3V
VCC
.01µF
.01µF
10Ω
VCCA
10µF
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS843001 has been characterized with 18pF parallel allel resonant crystal and were chosen to minimize the ppm er-
resonant crystals. The capacitor values, C1 and C2, shown in ror.The optimum C1 and C2 values can be slightly adjusted for
Figure 2 below were determined using a 26.5625MHz, 18pF par- different board layouts.
XTAL_OUT
C1
33p
X1
18pF Parallel Crystal
XTAL_IN
C2
27p
Figure 2. CRYSTAL INPUt INTERFACE
843001AG
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REV. B OCTOBER 13, 2004
8
ICS843001
Integrated
Circuit
Systems, Inc.
F
EMTO
C
LOCKS™ CRYSTAL
-TO-
3.3V LVPECL CLOCK
GENERATOR
LAYOUT GUIDELINE
Figure 3A shows a schematic example of the ICS843001. An parallel resonant crystal is used.The C1 = 27pF and C2 = 33pF
example of LVEPCL termination is shown in this schematic. are recommended for frequency accuracy.The C1 and C2 val-
Additional LVPECL termination approaches are shown in the ues may be slightly adjusted for optimizing frequency accuracy.
LVPECLTermination Application Note.In this example, an 18pF
VCC
VCCA
VCC
VCC
R2
10
C3
10uF
C4
0.01u
R1
R3
R5
1K
133
133
U1
Zo = 50 Ohm
Zo = 50 Ohm
Q
VCC
1
8
7
6
5
VCCA
VEE
XTAL_OUT
XTAL_IN
VCC
Q0
nQ0
+
-
2
3
4
FREQ_SEL
nQ
C2
33pF
26.5625MHz
18pF
X1
ICS843001
R4
82.5
R6
82.5
C5
0.1u
C1
27pF
FIGURE 3A. ICS843001 SCHEMATIC EXAMPLE
PC BOARD LAYOUT EXAMPLE
Figure 3B shows an example of ICS843001 P.C. board layout.
The crystal X1 footprint shown in this example allows installa-
tion of either surface mount HC49S or through-hole HC49 pack-
age.The footprints of other components in this example are listed
in the Table 6. There should be at least one decoupling capacitor
per power pin.The decoupling capacitors should be located as
close as possible to the power pins. The layout assumes that
the board has clean analog power ground plane.
TABLE 6. FOOTPRINT TABLE
Reference
C1, C2
C3
Size
0402
0805
0603
0603
C4, C5
R2
NOTE: Table 6, lists component
sizes shown in this layout example.
FIGURE 3B. ICS843001 PC BOARD LAYOUT EXAMPLE
843001AG
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REV. B OCTOBER 13, 2004
9
ICS843001
Integrated
Circuit
Systems, Inc.
F
EMTO
C
LOCKS™ CRYSTAL
-TO-
3.3V LVPECL CLOCK
GENERATOR
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS843001.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS843001 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5ꢀ = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 93mA = 322.2mW
Power (outputs)MAX = 30mW/Loaded Output pair
Total Power_MAX (3.465V, with all outputs switching) = 322.2mW + 30mW = 352.2mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device.The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = JunctionTemperature
θJA = Junction-to-AmbientThermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = AmbientTemperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 90.5°C/W perTable 7 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.352W * 90.5°C/W = 116.9°C. This is below the limit of 125°C.
This calculation is only an example.Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 7. THERMAL RESISTANCE θJA FOR 8-PIN TSSOP, FORCED CONVECTION
θJA byVelocity (Meters per Second)
0
1
2.5
89.8°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
101.7°C/W
90.5°C/W
843001AG
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REV. B OCTOBER 13, 2004
10
ICS843001
Integrated
Circuit
Systems, Inc.
F
EMTO
CLOCKS™ CRYSTAL- -
TO
3.3V LVPECL CLOCK
GENERATOR
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 4.
VCC
Q1
VOUT
RL
50
VCC - 2V
FIGURE 4. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage ofV - 2V.
CC
•
•
For logic high, VOUT = V
= V
– 0.9V
OH_MAX
CC_MAX
)
= 0.9V
OH_MAX
(V
- V
CCO_MAX
For logic low, VOUT = V
= V
– 1.7V
OL_MAX
CC_MAX
)
= 1.7V
OL_MAX
(V
- V
CCO_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
))
Pd_H = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
/R ] * (V
- V
) =
OH_MAX
CC_MAX
CC_MAX
OH_MAX
_MAX
OH_MAX
CC_MAX
OH_MAX
CC
L
[(2V - 0.9V)/50Ω] * 0.9V = 19.8mWL
))
Pd_L = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
/R ] * (V
- V
) =
OL_MAX
CC_MAX
CC_MAX
OL_MAX
_MAX
OL_MAX
CC_MAX
OL_MAX
L
CC
L
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
843001AG
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REV. B OCTOBER 13, 2004
11
ICS843001
Integrated
Circuit
Systems, Inc.
F
EMTO
C
LOCKS™ CRYSTAL
-TO-
3.3V LVPECL CLOCK
GENERATOR
RELIABILITY INFORMATION
TABLE 8. θJAVS. AIR FLOW TABLE FOR 8 LEAD TSSOP
θJA byVelocity (Meters Per Second)
0
1
2.5
89.8°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
101.7°C/W
90.5°C/W
TRANSISTOR COUNT
The transistor count for ICS843001 is: 1702
843001AG
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REV. B OCTOBER 13, 2004
12
ICS843001
Integrated
Circuit
Systems, Inc.
F
EMTO
C
LOCKS™ CRYSTAL
-TO-
3.3V LVPECL CLOCK
GENERATOR
PACKAGE OUTLINE - G SUFFIX 8 LEAD TSSOP
TABLE 9. PACKAGE DIMENSIONS
Millimeters
SYMBOL
Minimum
Maximum
N
A
8
--
1.20
0.15
1.05
0.30
0.20
3.10
A1
A2
b
0.05
0.80
0.19
0.09
2.90
c
D
E
6.40 BASIC
0.65 BASIC
E1
e
4.30
4.50
L
0.45
0°
0.75
8°
α
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
843001AG
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REV. B OCTOBER 13, 2004
13
ICS843001
Integrated
Circuit
Systems, Inc.
F
EMTO
CLOCKS™ CRYSTAL- -
TO
3.3V LVPECL CLOCK
GENERATOR
TABLE 10. ORDERING INFORMATION
Part/Order Number
ICS843001AG
Marking
Package
Count
Temperature
-30°C to 85°C
-30°C to 85°C
3001A
3001A
8 lead TSSOP
100 per tube
ICS843001AGT
8 lead TSSOP on Tape and Reel
2500
The aforementioned trademarks, HiPerClockS™ and FemtoClocks™ are a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature, high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
843001AG
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REV. B OCTOBER 13, 2004
14
ICS843001
Integrated
Circuit
Systems, Inc.
F
EMTO
C
LOCKS™ CRYSTAL
-TO-
3.3V LVPECL CLOCK
GENERATOR
REVISION HISTORY SHEET
Description of Change
Rev
A
Table
Page
1
Date
6/1/04
Corrected block diagram.
B
T3A
T10
3
Power Supply DC Characteristics Table- added ICCA spec.
8/23/04
10/13/04
B
14
Ordering Information Table - corrected count from 154 to 100 per tube.
843001AG
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REV. B OCTOBER 13, 2004
15
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