345R-XX [IDT]
Clock Generator, 200MHz, CMOS, PDSO20, 0.150 INCH, SSOP-20;
| 型号： | 345R-XX |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Generator, 200MHz, CMOS, PDSO20, 0.150 INCH, SSOP-20 时钟 光电二极管 外围集成电路 晶体 |
| 文件： | 总9页 (文件大小：220K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
TRIPLE PLL FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER ICS345
Description
Features
The ICS345 field programmable clock synthesizer
generates up to nine high-quality, high-frequency clock
outputs including multiple reference clocks from a
low-frequency crystal or clock input. It is designed to
replace crystals and crystal oscillators in most electronic
systems.
• Packaged as 20-pin SSOP (QSOP)
• Spread spectrum capability
• Eight addressable registers
• Replaces multiple crystals and oscillators
• Output frequencies up to 200 MHz at 3.3 V
• Input crystal frequency of 5 to 27 MHz
• Input clock frequency of 2 to 50 MHz
• Up to nine reference outputs
TM
Using IDT’s VersaClock software to configure PLLs and
outputs, the ICS345 contains a One-Time Programmable
(OTP) ROM to allow field programmability. Programming
features include eight selectable configuration registers, up
to two sets of four low-skew outputs, and optional Spread
Spectrum outputs.
• Up to two sets of four low-skew outputs
• Operating voltages of 3.3 V
• Advanced, low-power CMOS process
Using Phase-Locked Loop (PLL) techniques, the device
runs from a standard fundamental mode, inexpensive
crystal, or clock. It can replace multiple crystals and
oscillators, saving board space and cost.
• For one output clock, use the ICS341. For two output
clocks, see the ICS342. For three output clocks, see the
ICS343. For more than three outputs, see the ICS345 or
ICS348.
• Available in Pb (lead) free packaging
The ICS345 is also available in factory programmed custom
versions for high-volume applications.
NOTE: EOL for non-green parts to occur on
5/13/10 per PDN U-09-01
Block Diagram
3
VDD
PLL1 with
Spread
Spectrum
CLK1
CLK2
CLK3
CLK4
CLK5
CLK6
CLK7
CLK8
CLK9
3
OTP
S2:S0
ROM
with
PLL
Divide
Logic
and
Output
Enable
Control
Values
PLL2
PLL3
Crystal or
clock input
X1/ICLK
Crystal
Oscillator
X2
GND
2
External capacitors are
required with a crystal input.
PDTS
IDT™ / ICS™ TRIPLE PLL FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER 1
ICS345
REV L 092109
ICS345
TRIPLE PLL FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER
EPROM CLOCK SYNTHESIZER
Pin Assignment
X1/ICLK
S0
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
X2
VDD
PDTS
S2
S1
CLK9
VDD
GND
CLK1
CLK2
CLK3
CLK4
VDD
GND
CLK5
CLK6
CLK7
CLK8
20-pin (150 mil) SSOP (QSOP)
Pin Descriptions
Pin
Number
Pin
Name
Pin
Type
Pin Description
1
2
X1/ICLK
S0
XI
Crystal input. Connect this pin to a crystal or external input clock.
Select pin 0. Internal pull-up resistor.
Input
Input
3
S1
Select pin 1. Internal pull-up resistor.
4
CLK9
VDD
GND
CLK1
CLK2
CLK3
CLK4
CLK8
CLK7
CLK6
CLK5
GND
VDD
S2
Output Output clock 9. Weak internal pull-down when tri-state.
Connect to +3.3 V.
Connect to ground.
5
Power
Power
6
7
Output Output clock 1. Weak internal pull-down when tri-state.
Output Output clock 2. Weak internal pull-down when tri-state.
Output Output clock 3. Weak internal pull-down when tri-state.
Output Output clock 4. Weak internal pull-down when tri-state.
Output Output clock 8. Weak internal pull-down when tri-state.
Output Output clock 7. Weak internal pull-down when tri-state.
Output Output clock 6. Weak internal pull-down when tri-state.
Output Output clock 5. Weak internal pull-down when tri-state.
8
9
10
11
12
13
14
15
16
17
Power
Power
Input
Connect to ground.
Connect to +3.3 V.
Select pin 2. Internal pull-up resisitor.
Power-down tri-state. Powers down entire chip and tri-states clock outputs
when low. Internal pull-up resisitor.
18
PDTS
Input
Connect to +3.3 V.
19
20
VDD
X2
Power
XO
Crystal Output. Connect this pin to a crystal. Float for clock input.
IDT™ / ICS™ TRIPLE PLL FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER 2
ICS345
REV L 092109
ICS345
TRIPLE PLL FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER
EPROM CLOCK SYNTHESIZER
they should be separated and away from other traces.
External Components
3) To minimize EMI, the 33Ω series termination resistor (if
Series Termination Resistor
needed) should be placed close to the clock output.
Clock output traces over one inch should use series
termination. To series terminate a 50Ω trace (a commonly
used trace impedance), place a 33Ω resistor in series with
the clock line, as close to the clock output pin as possible.
The nominal impedance of the clock output is 20Ω.
4) An optimum layout is one with all components on the
same side of the board, minimizing vias through other signal
layers.
ICS345 Configuration Capabilities
Decoupling Capacitors
The architecture of the ICS345 allows the user to easily
configure the device to a wide range of output frequencies,
for a given input reference frequency.
As with any high-performance mixed-signal IC, the ICS345
must be isolated from system power supply noise to perform
optimally.
The frequency multiplier PLL provides a high degree of
precision. The M/N values (the multiplier/divide values
available to generate the target VCO frequency) can be set
within the range of M = 1 to 2048 and N = 1 to 1024.
Decoupling capacitors of 0.01µF must be connected
between each VDD and the PCB ground plane.
Crystal Load Capacitors
The device crystal connections should include pads for
small capacitors from X1 to ground and from X2 to ground.
These capacitors are used to adjust the stray capacitance of
the board to match the nominally required crystal load
capacitance. Because load capacitance can only be
increased in this trimming process, it is important to keep
stray capacitance to a minimum by using very short PCB
traces (and no vias) between the crystal and device. Crystal
capacitors must be connected from each of the pins X1 and
X2 to ground.
The ICS345 also provides separate output divide values,
from 2 through 20, to allow the two output clock banks to
support widely differing frequency values from the same
PLL.
Each output frequency can be represented as:
REFFreq
OutputDivide
M
----
--------------------------------------
OutputFreq =
⋅
N
The value (in pF) of these crystal caps should equal (C -6
L
IDT VersaClock Software
pF)*2. In this equation, C = crystal load capacitance in pF.
L
Example: For a crystal with a 16 pF load capacitance, each
crystal capacitor would be 20 pF [(16-6) x 2 = 20].
IDT applies years of PLL optimization experience into a user
friendly software that accepts the user’s target reference
clock and output frequencies and generates the lowest jitter,
lowest power configuration, with only a press of a button.
The user does not need to have prior PLL experience or
determine the optimal VCO frequency to support multiple
output frequencies.
PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
1) Each 0.01µF decoupling capacitor should be mounted on
the component side of the board as close to the VDD pin as
possible. No vias should be used between decoupling
capacitor and VDD pin. The PCB trace to VDD pin should
be kept as short as possible, as should the PCB trace to the
ground via.
VersaClock software quickly evaluates accessible VCO
frequencies with available output divide values and provides
an easy to understand, bar code rating for the target output
frequencies. The user may evaluate output accuracy,
performance trade-off scenarios in seconds.
2) The external crystal should be mounted just next to the
device with short traces. The X1 and X2 traces should not
be routed next to each other with minimum spaces, instead
IDT™ / ICS™ TRIPLE PLL FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER 3
ICS345
REV L 092109
ICS345
TRIPLE PLL FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER
EPROM CLOCK SYNTHESIZER
The ICS345 operates in both center spread and down
spread modes. For center spread, the frequency can be
modulated between 0.125% to 2.0%. For down spread,
the frequency can be modulated between -0.25% to -4.0%.
Spread Spectrum Modulation
The ICS345 utilizes frequency modulation (FM) to distribute
energy over a range of frequencies. By modulating the
output clock frequencies, the device effectively lowers
energy across a broader range of frequencies; thus,
lowering a system’s electromagnetic interference (EMI). The
modulation rate is the time from transitioning from a
minimum frequency to a maximum frequency and then back
to the minimum.
Both output frequency banks will utilize identical spread
spectrum percentage deviations and modulation rates, if a
common VCO frequency can be identified.
Spread Spectrum Modulation Rate
The spread spectrum modulation frequency applied to the
output clock frequency may occur at a variety of rates. For
applications requiring the driving of “down-circuit” PLLs,
Zero Delay Buffers, or those adhering to PCI standards, the
spread spectrum modulation rate should be set to 30-33
kHz. For other applications, a 120 kHz modulation option is
available.
Spread Spectrum Modulation can be applied as either
“center spread” or “down spread”. During center spread
modulation, the deviation from the target frequency is equal
in the positive and negative directions. The effective
average frequency is equal to the target frequency. In
applications where the clock is driving a component with a
maximum frequency rating, down spread should be applied.
In this case, the maximum frequency, including modulation,
is the target frequency. The effective average frequency is
less than the target frequency.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS345. These ratings, which are
standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these
or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical
parameters are guaranteed only over the recommended operating temperature range.
Parameter
Condition
Min.
Typ.
Max.
7
Units
V
Supply Voltage, VDD
Inputs
Referenced to GND
Referenced to GND
Referenced to GND
-0.5
-0.5
-65
VDD+0.5
VDD+0.5
150
V
Clock Outputs
V
Storage Temperature
Soldering Temperature
Junction Temperature
°C
°C
°C
Max 10 seconds
260
125
IDT™ / ICS™ TRIPLE PLL FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER 4
ICS345
REV L 092109
ICS345
TRIPLE PLL FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER
EPROM CLOCK SYNTHESIZER
Recommended Operation Conditions
Parameter
Min.
0
Typ.
Max.
+70
+85
+3.45
4
Units
° C
Ambient Operating Temperature (ICS345RP)
Ambient Operating Temperature (ICS345RIP)
Power Supply Voltage (measured in respect to GND)
Power Supply Ramp Time
-40
° C
+3.15
+3.3
V
ms
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V 5%, Ambient Temperature -40 to +85° C
Parameter
Symbol
VDD
Conditions
Min.
Typ.
Max. Units
Operating Voltage
3.15
3.45
V
Operating Supply Current
Input High Voltage
IDD
Configuration Dependent -
See VersaClock
mA
TM
Estimates
Nine 33.3333 MHz outs,
PDTS = 1, no load, Note 1
23
20
mA
PDTS = 0, no load, Note 1
S2:S0
µA
V
Input High Voltage
V
2
IH
Input Low Voltage
V
S2:S0
0.4
0.4
V
V
V
V
V
V
IL
Input High Voltage, PDTS
Input Low Voltage, PDTS
Input High Voltage
V
VDD-0.5
VDD/2+1
IH
V
IL
V
ICLK
ICLK
IH
Input Low Voltage
V
VDD/2-1
IL
Output High Voltage
(CMOS High)
V
I
= -4 mA
VDD-0.4
2.4
OH
OH
Output High Voltage
Output Low Voltage
Short Circuit Current
V
I
I
= -12 mA
= 12 mA
V
V
OH
OH
V
0.4
OL
OL
I
70
mA
Ω
OS
Nominal Output
Impedance
Z
20
O
Internal Pull-up Resistor
R
S2:S0, PDTS
CLK outputs
250
525
kΩ
kΩ
PUS
Internal Pull-down
Resistor
R
PD
Input Capacitance
C
Inputs
4
pF
IN
Note 1: Example with 25 MHz crystal input with nine outputs of 33.3 MHz, no load, and VDD = 3.3 V.
IDT™ / ICS™ TRIPLE PLL FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER 5
ICS345
REV L 092109
ICS345
TRIPLE PLL FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER
EPROM CLOCK SYNTHESIZER
AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V 5%, Ambient Temperature -40 to +85° C
Parameter
Symbol
Conditions
Fundamental crystal
Input clock
Min.
5
Typ.
Max. Units
Input Frequency
F
27
50
MHz
MHz
MHz
ns
IN
2
Output Frequency
Output Rise Time
Output Fall Time
Duty Cycle
VDD=3.3 V
0.25
200
t
20% to 80%, Note 1
80% to 20%, Note 1
Note 2
1
1
OR
t
ns
OF
40
49-51
0
60
%
Output Frequency Synthesis
Error (Note 4)
Configuration Dependent
ppm
Power-up Time
PLL lock-time from
power-up, Note 3
4
10
2
ms
ms
PDTS goes high until stable
CLK output, Spread
0.2
Spectrum Off, Note 3
PDTS goes high until stable
CLK output, Spread
4
7
ms
Spectrum On, Note 3
One Sigma Clock Period Jitter
Maximum Absolute Jitter
Configuration Dependent
50
ps
ps
t
Deviation from Mean.
+200
ja
Configuration Dependent
Pin-to-Pin Skew
Low Skew Outputs
-250
250
ps
Note 1: Measured with 15 pF load.
Note 2: Duty Cycle is configuration dependent. Most configurations are min 45% / max 55%
Note 3: IDT test mode output occurs for first 170 clock cycles on CLK7 for each PLL powered up. PDTS transition
high on select address change.
Note 4: The actual ppm error will be displayed in the VersaClock software when the programming file is generated
for the customer’s specific configuration. In general, zero ppm error can be achieved, but please note that the
device cannot improve upon the error of the input reference clock. For example, if the input crystal has 25 ppm error,
then the outputs will also have 25 ppm error.
Thermal Characteristics
Parameter
Symbol
Conditions
Min.
Typ. Max. Units
Thermal Resistance Junction to
Ambient
θ
Still air
135
93
° C/W
° C/W
° C/W
° C/W
JA
θ
1 m/s air flow
3 m/s air flow
JA
θ
78
JA
Thermal Resistance Junction to Case
θ
60
JC
IDT™ / ICS™ TRIPLE PLL FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER 6
ICS345
REV L 092109
ICS345
TRIPLE PLL FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER
EPROM CLOCK SYNTHESIZER
Package Outline and Package Dimensions (20-pin SSOP, 150 Mil. Wide Body)
Package dimensions are kept current with JEDEC Publication No. 95
Millimeters
Inches*
20
Symbol
Min
Max
1.75
0.25
1.50
0.30
0.25
8.75
6.20
4.00
Min
Max
A
A1
A2
b
1.35
0.10
--
0.20
0.18
8.55
5.80
3.80
0.053
0.004
--
0.008
0.007
0.337
0.228
0.150
0.069
0.010
0.059
0.012
0.010
0.344
0.244
0.157
E1
E
INDEX
AREA
c
D
E
1
2
E1
e
L
.635 Basic
0.40
.025 Basic
0.016
D
1.27
0.050
α
0°
8°
0°
8°
aaa
--
0.10
--
0.004
A
*For reference only. Controlling dimensions in mm.
A2
A1
c
- C -
e
SEATING
PLANE
b
L
aaa C
IDT™ / ICS™ TRIPLE PLL FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER 7
ICS345
REV L 092109
ICS345
TRIPLE PLL FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER
EPROM CLOCK SYNTHESIZER
Ordering Information
Part / Order Number
345RP*
Marking
ICS345RP
Shipping Packaging
Tubes
Package
Temperature
0 to +70° C
0 to +70° C
-40 to +85° C
-40 to +85° C
0 to +70° C
20-pin SSOP
20-pin SSOP
20-pin SSOP
20-pin SSOP
20-pin SSOP
20-pin SSOP
20-pin SSOP
20-pin SSOP
20-pin SSOP
20-pin SSOP
20-pin SSOP
20-pin SSOP
20-pin SSOP
20-pin SSOP
20-pin SSOP
20-pin SSOP
345RPT*
ICS345RP
Tape and Reel
Tubes
345RIP*
ICS345RIP
345RIPT*
ICS345RIP
Tape and Reel
Tubes
345RPLF
ICS345RPLF
ICS345RPLF
ICS345RIPLF
ICS345RIPLF
ICS345R-XX
ICS345R-XX
ICS345RI-XX
ICS345RI-XX
345R-XXLF
345R-XXLF
345RI-XXLF
345RI-XXLF
345RPLFT
345RIPLF
Tape and Reel
Tubes
0 to +70° C
-40 to +85° C
-40 to +85° C
0 to +70° C
345RIPLFT
345R-XX*
Tape and Reel
Tubes
345R-XXT*
345RI-XX*
345RI-XXT*
345R-XXLF
345R-XXLFT
345RI-XXLF
345RI-XXLFT
Tape and Reel
Tubes
0 to +70° C
-40 to +85° C
-40 to +85° C
0 to +70° C
0 to +70° C
-40 to +85° C
-40 to +85° C
Tape and Reel
Tubes
Tape and Reel
Tubes
Tape and Reel
*NOTE: EOL for non-green parts to occur on 5/13/10 per PDN U-09-01
Parts that are ordered with a “LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant.
The 345R-XX, 345R-XXLF, 345RI-XX, and 345RI-XXLF are factory programmed versions of the 345RP, 345RPLF, 345RIP, and
345RIPLF. A unique “-XX” suffix is assigned by the factory for each custom configuration, and a separate data sheet is kept on
file. For more information on custom part numbers programmed at the factory, please contact your local IDT sales and marketing
representative.
While the information presented herein has been checked for both accuracy and reliability, IDT assumes no responsibility for either its use
or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses
are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended
temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing
by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product
for use in life support devices or critical medical instruments.
IDT™ / ICS™ TRIPLE PLL FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER 8
ICS345
REV L 092109
ICS345
TRIPLE PLL FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER
EPROM CLOCK SYNTHESIZER
Innovate with IDT and accelerate your future networks. Contact:
www.IDT.com
For Sales
800-345-7015
408-284-8200
Fax: 408-284-2775
For Tech Support
www.idt.com/go/clockhelp
Corporate Headquarters
Integrated Device Technology, Inc.
www.idt.com
© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device
Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered
trademarks used to identify products or services of their respective owners.
Printed in USA
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明