5P49V5927_技术文档

Programmable Clock Generator

5P49V5927

DATASHEET

Description

Features

The 5P49V5927 is a programmable clock generator intended

for high performance consumer, networking, industrial,

computing, and data-communications applications.

Configurations may be stored in on-chip One-Time

• Generates up to three independent output frequencies

• High performance, low phase noise PLL, <0.7 ps RMS

typical phase jitter on outputs

2

• Three fractional output dividers (FODs)

Programmable (OTP) memory or changed using I C

interface. This is IDT’s fifth generation of programmable clock

technology (VersaClock 5).

• Independent Spread Spectrum capability on each output

pair

®

• Four banks of internal non-volatile in-system

The frequencies are generated from a single reference clock.

The reference clock can come from one of the two redundant

clock inputs. A glitchless manual switchover function allows

one of the redundant clocks to be selected during normal

operation.

programmable or factory programmable OTP memory

2

• I C serial programming interface

• Seven LVCMOS outputs, including one reference output

• I/O Standards:

Two select pins allow up to 4 different configurations to be

programmed and accessible using processor GPIOs or

bootstrapping. The different selections may be used for

different operating modes (full function, partial function, partial

power-down), regional standards (US, Japan, Europe) or

system production margin testing.

– Single-ended I/Os: 1.8V to 3.3V LVCMOS

• Input frequency ranges:

– LVCMOS Reference Clock Input (XIN/REF) – 1MHz to

200MHz

– LVDS, LVPECL, HCSL Differential Clock Input (CLKIN,

CLKINB) – 1MHz to 200MHz

2

The device may be configured to use one of two I C

addresses to allow multiple devices to be used in a system.

– Crystal frequency range: 8MHz to 40MHz

• Output frequency ranges:

Pin Assignment

– LVCMOS Clock Outputs – 1MHz to 200MHz

• Individually selectable output voltage (1.8V, 2.5V, 3.3V) for

each output pair

• Redundant clock inputs with manual switchover

• Programmable loop bandwidth

• Programmable slew rate control

• Programmable crystal load capacitance

• Individual output enable/disable

• Power-down mode

19

24 23 22 21 20

1

2

V

_DDO2

18

CLKIN

CLKINB

XOUT

OUT3

OUT4

17

16

15

14

• 1.8V, 2.5V or 3.3V core V

, V

DDA

DDD

3

4

EPAD

GND

• Available in 24-pin VFQFPN 4mm x 4mm package

• -40° to +85°C industrial temperature operation

V_DDO

3

XIN/REF

V_DDA

5

6

OUT5

OUT6

13

CLKSEL

8

9

10 11 12

7

24-pin VFQFPN

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Functional Block Diagram

V_DDO

OUT0_SEL_I2CB

_DDO1

0

XIN/REF

XOUT

V

OUT1

OUT2

FOD1

FOD2

FOD3

CLKIN

V

_DDO2

CLKINB

OUT3

OUT4

CLKSEL

SD/OE

PLL

V

_DDO3

OUT5

OUT6

V_DDA

SEL1/SDA

OTP

SEL0/SCL

and

Control Logic

V_DDA

V_DDD

Applications

• Ethernet switch/router

• PCI Express 1.0/2.0/3.0

• Broadcast video/audio timing

• Multi-function printer

• Processor and FPGA clocking

• Any-frequency clock conversion

• MSAN/DSLAM/PON

• Fiber Channel, SAN

• Telecom line cards

• 1 GbE and 10 GbE

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Table 1:Pin Descriptions

Number

Name

Type

Description

Internal

Pull-down

1

CLKIN

Input

Differential clock input. Weak 100kohms internal pull-down.

Internal

Pull-down

2

3

CLKINB

XOUT

Input

Complementary differential clock input. Weak 100kohms internal pull-down.

Crystal Oscillator interface output.

Crystal Oscillator interface input, or single-ended LVCMOS clock input. Ensure that

the input voltage is 1.2V max.Refer to the section “Overdriving the XIN/REF

Interface”.

4

5

XIN/REF

V_DDA

Input

Analog functions power supply pin.Connect to 1.8V to 3.3V. V_DDAand V_DDDshould

have the same voltage applied.

Power

Input clock select. Selects the active input reference source in manual switchover

mode.

Internal

Pull-down

6

CLKSEL

Input

0 = XIN/REF, XOUT (default)

1 = CLKIN, CLKINB

CLKSEL Polarity can be changed by I2C programming as shown in Table 4.

Enables/disables the outputs (OE) or powers down the chip (SD). The SH bit

controls the configuration of the SD/OE pin. The SH bit needs to be high for SD/OE

pin to be configured as SD. The SP bit (0x02) controls the polarity of the signal to be

either active HIGH or LOW only when pin is configured as OE (Default is active

LOW.) Weak internal pull down resistor. When configured as SD, device is shut

down and the single-ended LVCMOS outputs are driven low. When configured as

OE, and outputs are disabled, the outputs can be selected to be tri-stated or driven

high/low, depending on the programming bits as shown in the SD/OE Pin Function

Truth table.

Internal

Pull-down

7

SD/OE

Internal

Configuration select pin, or I²C SDA input as selected by OUT0_SEL_I2CB. Weak

8

9

SEL1/SDA

SEL0/SCL

V_DDA

Input

Pull-down internal pull down resistor.

Internal

Configuration select pin, or I²C SCL input as selected by OUT0_SEL_I2CB. Weak

Pull-down internal pull down resistor.

Analog functions power supply pin.Connect to 1.8V to 3.3V. V_DDAand V_DDDshould

have the same voltage applied.

10

Power

11

12

NC

–

No connect.

Output Clock 6. Please refer to the Output Drivers section for more details. OUT5

and OUT6 are the same frequency.

13

14

15

16

17

18

19

20

OUT6

OUT5

Output

Power

Output

Power

Output

Output Clock 5. Please refer to the Output Drivers section for more details. OUT5

and OUT6 are the same frequency.

Output power supply. Connect to 1.8 to 3.3V. Sets output voltage levels for OUT5

and OUT6.

V_DDO

3

Output Clock 4. Please refer to the Output Drivers section for more details. OUT3

and OUT4 are the same frequency.

OUT4

OUT3

Output Clock 3. Please refer to the Output Drivers section for more details. OUT3

and OUT4 are the same frequency.

Output power supply. Connect to 1.8 to 3.3V. Sets output voltage levels for OUT3

and OUT4.

V_DDO

OUT2

OUT1

2

Output Clock 2. Please refer to the Output Drivers section for more details. OUT1

and OUT2 are the same frequency.

Output Clock 1. Please refer to the Output Drivers section for more details. OUT1

and OUT2 are the same frequency.

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Number

Name

V_DDO

V_DDD

Type

Description

Output power supply. Connect to 1.8 to 3.3V. Sets output voltage levels for OUT1

and OUT2.

21

1

Power

Digital functions power supply pin. Connect to 1.8 to 3.3V. V_DDAand V_DDDshould

have the same voltage applied.

22

23

Power supply pin for OUT0_SEL_I2CB. Connect to 1.8 to 3.3V. Sets output voltage

levels for OUT0.

V_DDO

0

Latched input/LVCMOS Output. At power up, the voltage at the pin

OUT0_SEL_I2CB is latched by the part and used to select the state of pins 8 and 9.

If a weak pull up (10kohms) is placed on OUT0_SEL_I2CB, pins 8 and 9 will be

configured as hardware select pins, SEL1 and SEL0. If a weak pull down (10Kohms)

is placed on OUT0_SEL_I2CB or it is left floating, pins 8 and 9 will act as the SDA

and SCL pins of an I²C interface. After power up, the pin acts as a LVCMOS

reference output.

Input/

Output

Internal

Pull-down

24

OUT0_SEL_I2CB

GND

ePAD

GND

Connect to ground pad.

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PLL Features and Descriptions

If OUT0_SEL_I2CB was 0 at POR, alternate configurations

can only be loaded via the I2C interface.

Spread Spectrum

To help reduce electromagnetic interference (EMI), the

5P49V5927 supports spread spectrum modulation. The

output clock frequencies can be modulated to spread energy

across a broader range of frequencies, lowering system EMI.

The 5P49V5927 implements spread spectrum using the

Fractional-N output divide, to achieve controllable modulation

rate and spreading magnitude. The Spread spectrum can be

applied to any output clock, any clock frequency, and any

spread amount from ±0.25% to ±2.5% center spread and

-0.5% to -5% down spread.

Table 4: Input Clock Select

Input clock select. Selects the active input reference source in

manual switchover mode.

0 = XIN/REF, XOUT (default)

1 = CLKIN, CLKINB

CLKSEL Polarity can be changed by I C programming as

2

shown in Table 4.

PRIMSRC

CLKSEL

Source

XIN/REF

0

1

0

1

0

1

Table 2: Loop Filter

PLL loop bandwidth range depends on the input reference

frequency (Fref) and can be set between the loop bandwidth

range as shown in the table below.

CLKIN, CLKINB

XIN/REF

Input Reference

Frequency–Fref

(MHz)

Loop

Bandwidth

Min (kHz)

Loop

Bandwidth

Max (kHz)

PRIMSRC is bit 1 of Register 0x13.

5

40

126

200

300

1000

Table 3: Configuration Table

This table shows the SEL1, SEL0 settings to select the

configuration stored in OTP. Four configurations can be stored

in OTP. These can be factory programmed or user

programmed.

2

OUT0_SEL_I2CB SEL1 SEL0

@ POR

I C

REG0:7 Config

Access

1

0

1

X

0

1

0

1

X

No

Yes

0

1

0

1

2

3

I2C

defaults

0

X

Yes

0

At power up time, the SEL0 and SEL1 pins must be tied to

either the VDDD/VDDA power supply so that they ramp with

that supply or are tied low (this is the same as floating the

pins). This will cause the register configuration to be loaded

that is selected according to Table 3 above. Providing that

OUT0_SEL_I2CB was 1 at POR and OTP register 0:7=0, after

the first 10mS of operation the levels of the SELx pins can be

changed, either to low or to the same level as VDDD/VDDA.

The SELx pins must be driven with a digital signal of < 300nS

Rise/Fall time and only a single pin can be changed at a time.

After a pin level change, the device must not be interrupted for

at least 1ms so that the new values have time to load and take

effect.

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The capacitance at each crystal pin inside the chip starts at

9pF with setting 000000b and can be increased up to 25pF

with setting 111111b. The step per bit is 0.5pF.

Reference Clock Input Pins and

Selection

The 5P49V5927 supports up to two clock inputs. One input

supports a crystal between XIN and XOUT. XIN can also be

driven from a single ended reference clock. XIN can accept

small amplitude signals like from TCXO or one channel of a

differential clock.

You can write the following equation for this capacitance:

Ci = 9pF + 0.5pF × XTAL[5:0]

The PCB where the IC and the crystal will be assembled adds

some stray capacitance to each crystal pin and more

capacitance can be added to each crystal pin with additional

external capacitors.

The second clock input (CLKIN, CLKINB) is a fully differential

input that only accepts a reference clock. The differential input

accepts differential clocks from all the differential logic types

and can also be driven from a single ended clock on one of the

input pins.

The CLKSEL pin selects the input clock between either

XTAL/REF or (CLKIN, CLKINB).

Either clock input can be set as the primary clock. The primary

clock designation is to establish which is the main reference

clock to the PLL. The non-primary clock is designated as the

secondary clock in case the primary clock goes absent and a

backup is needed. See the previous page for more details

about primary versus secondary clock operation.

The two external reference clocks can be manually selected

using the CLKSEL pin. The SM bits must be set to “0x” for

manual switchover which is detailed in Manual Switchover

Mode section.

You can write the following equations for the total capacitance

at each crystal pin:

Crystal Input (XIN/REF)

C

= Ci + Cs + Ce

1 1 1

XIN

= Ci + Cs + Ce

XOUT

2

The crystal used should be a fundamental mode quartz

crystal; overtone crystals should not be used.

Ci and Ci are the internal, tunable capacitors. Cs and Cs

2

1

2

1

are stray capacitances at each crystal pin and typical values

are between 1pF and 3pF.

A crystal manufacturer will calibrate its crystals to the nominal

frequency with a certain load capacitance value. When the

oscillator load capacitance matches the crystal load

capacitance, the oscillation frequency will be accurate. When

the oscillator load capacitance is lower than the crystal load

capacitance, the oscillation frequency will be higher than

nominal and vice versa so for an accurate oscillation

frequency you need to make sure to match the oscillator load

capacitance with the crystal load capacitance.

Ce and Ce are additional external capacitors that can be

1

2

added to increase the crystal load capacitance beyond the

tuning range of the internal capacitors. However, increasing

the load capacitance reduces the oscillator gain so please

consult the factory when adding Ce and/or Ce to avoid

1

2

crystal startup issues. Ce and Ce can also be used to adjust

1

2

for unpredictable stray capacitance in the PCB.

To set the oscillator load capacitance there are two tuning

capacitors in the IC, one at XIN and one at XOUT. They can

be adjusted independently but commonly the same value is

used for both capacitors. The value of each capacitor is

composed of a fixed capacitance amount plus a variable

capacitance amount set with the XTAL[5:0] register.

Adjustment of the crystal tuning capacitors allows for

maximum flexibility to accommodate crystals from various

manufacturers. The range of tuning capacitor values available

are in accordance with the following table.

The final load capacitance of the crystal:

CL = C

× C

/ (C

+ C

)

XIN

XOUT

XIN

XOUT

For most cases it is recommended to set the value for

capacitors the same at each crystal pin:

C

= C

= Cx → CL = Cx / 2

XIN

XOUT

The complete formula when the capacitance at both crystal

pins is the same:

CL = (9pF + 0.5pF × XTAL[5:0] + Cs + Ce) / 2

XTAL[5:0] Tuning Capacitor Characteristics

Parameter

Bits

Step (pF)

Min (pF)

Max (pF)

XTAL

6

0.5

9

25

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Example 1: The crystal load capacitance is specified as 8pF

and the stray capacitance at each crystal pin is Cs=1.5pF.

Assuming equal capacitance value at XIN and XOUT, the

equation is as follows:

8pF = (9pF + 0.5pF × XTAL[5:0] + 1.5pF) / 2 →

0.5pF × XTAL[5:0] = 5.5pF → XTAL[5:0] = 11 (decimal)

Example 2: The crystal load capacitance is specified as 12pF

and the stray capacitance Cs is unknown. Footprints for

external capacitors Ce are added and a worst case Cs of 5pF

is used. For now we use Cs + Ce = 5pF and the right value for

Ce can be determined later to make 5pF together with Cs.

12pF = (9pF + 0.5pF × XTAL[5:0] + 5pF) / 2 →

XTAL[5:0] = 20 (decimal)

Manual Switchover Mode

When SM[1:0] is “0x”, the redundant inputs are in manual

switchover mode. In this mode, CLKSEL pin is used to switch

between the primary and secondary clock sources. The

primary and secondary clock source setting is determined by

the PRIMSRC bit. During the switchover, no glitches will occur

at the output of the device, although there may be frequency

and phase drift, depending on the exact phase and frequency

relationship between the primary and secondary clocks.

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OTP Interface

Table 5: SD/OE Pin Function Truth Table

The 5P49V5927 can also store its configuration in an internal

OTP. The contents of the device's internal programming

registers can be saved to the OTP by setting burn_start

(W114[3]) to high and can be loaded back to the internal

programming registers by setting usr_rd_start(W114[0]) to

high.

SH bit SP bit OSn bit OEn bit SD/OE

OUTn

0

1

x

0

1

x

0

1

Tri-state²

Output active

Output driven High Low

0

1

0

1

x

0

1

x

0

1

Tri-state²

Output active

Output driven High Low

Output active

2

To initiate a save or restore using I C, only two bytes are

transferred. The Device Address is issued with the read/write

bit set to “0”, followed by the appropriate command code. The

save or restore instruction executes after the STOP condition

is issued by the Master, during which time the 5P49V5927 will

not generate Acknowledge bits. The 5P49V5927 will

1

0

1

x

0

1

0

Tri-state²

Output active

1

0

1

x

0

1

0

Tri-state²

acknowledge the instructions after it has completed execution

Output active

Output driven High Low

Output driven High Low ¹

2

of them. During that time, the I C bus should be interpreted as

busy by all other users of the bus.

1

x

1

On power-up of the 5P49V5927, an automatic restore is

performed to load the OTP contents into the internal

programming registers. The 5P49V5927 will be ready to

accept a programming instruction once it acknowledges its

Note 1 : Global Shutdown

Note 2 : Tri-state regardless of OEn bits

2

Output Divides

7-bit I C address.

2

Each output divide block has a synchronizing POR pulse to

provide startup alignment between outputs divides. This

allows alignment of outputs for low skew performance. This

low skew would also be realized between outputs that are

both integer divides from the VCO frequency. This phase

alignment works when using configuration with SEL1, SEL0.

Availability of Primary and Secondary I C addresses to allow

2

programming for multiple devices in a system. The I C slave

address can be changed from the default 0xD4 to 0xD0 by

programming the I2C_ADDR bit D0. VersaClock 5

2

Programming Guide provides detailed I C programming

guidelines and register map.

2

For I C programming, I C reset is required.

SD/OE Pin Function

An output divide bypass mode (divide by 1) will also be

provided, to allow multiple buffered reference outputs.

The polarity of the SD/OE signal pin can be programmed to be

either active HIGH or LOW with the SP bit (W16[1]). When SP

is “0” (default), the pin becomes active LOW and when SP is

“1”, the pin becomes active HIGH. The SD/OE pin can be

configured as either to shutdown the PLL or to enable/disable

the outputs. The SH bit controls the configuration of the

SD/OE pin The SH bit needs to be high for SD/OE pin to be

configured as SD.

Each of the four output divides are comprised of a 12 bit

integer counter, and a 24 bit fractional counter. The output

divide can operate in integer divide only mode for improved

performance, or utilize the fractional counters to generate a

clock frequency accurate to 50 ppb.

Each of the output divides also have structures capable of

independently generating spread spectrum modulation on the

frequency output.

SP

OUTn

SD/OE Input

The Output Divide also has the capability to apply a spread

modulation to the output frequency. Independent of output

frequency, a triangle wave modulation between 30 and 63kHz

may be generated.

OEn

Global Shutdown

OSn

SH

For all outputs, there is a bypass mode, to allow the output to

behave as a buffered copy of the input.

When configured as SD, device is shut down, the

single-ended LVCMOS outputs are driven low. When

configured as OE, and outputs are disabled, the outputs are

driven high/low.

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Output Skew

Device Start-up & Reset Behavior

For outputs that share a common output divide value, there

will be the ability to skew outputs by quadrature values to

minimize interaction on the PCB. The skew on each output

can be adjusted from 0 to 360 degrees. Skew is adjusted in

units equal to 1/32 of the VCO period. So, for 100 MHz output

and a 2800 MHz VCO, you can select how many 11.161pS

units you want added to your skew (resulting in units of 0.402

degrees). For example, 0, 0.402, 0.804, 1.206, 1.408, and so

on. The granularity of the skew adjustment is always

The 5P49V5927 has an internal power-up reset (POR) circuit.

The POR circuit will remain active for a maximum of 10ms

after device power-up.

Upon internal POR circuit expiring, the device will exit reset

and begin self-configuration.

The device will load internal registers according to Table 3.

Once the full configuration has been loaded, the device will

respond to accesses on the serial port and will attempt to lock

the PLL to the selected source and begin operation.

dependent on the VCO period and the output period.

Output Drivers

Power Up Ramp Sequence

The operating voltage ranges of each output is determined by

VDDA and VDDD must ramp up together. VDDO0~3 must

ramp up before, or concurrently with, VDDA and VDDD. All

power supply pins must be connected to a power rail even if

the output is unused. All power supplies must ramp in a linear

fashion and ramp monotonically.

its independent output power pin (V

have different output voltage levels. Output voltage levels of

1.8V, 2.5V, or 3.3V are supported for LVCMOS.

) and thus each can

DDO

Each output may be enabled or disabled by register bits.

When disabled an output will be in a logic 0 state as

determined by the programming bit table shown on page 6.

VDDO0~3

LVCMOS Operation

Output pairs OUT1 & OUT2; OUT3 & OUT4; OUT5 & OUT6

each operate the frequency as determined by responding

programmed Fractional Output Dividers. All the previously

described configuration and control apply equally to all

outputs. Frequency, phase alignment, voltage levels and

enable / disable status apply to all the OUTx pins. The outputs

can be selected to be phase-aligned with each other or

inverted relative to one another by register programming bits.

Selection of phase-alignment may have negative effects on

the phase noise performance of any part of the device due to

increased simultaneous switching noise within the device.

VDDA

VDDD

Device Hardware Configuration

The 5P49V5927 supports an internal One-Time

Programmable (OTP) memory that can be pre-programmed

at the factory with up to 4 complete device configuration.

These configurations can be over-written using the serial

interface once reset is complete. Any configuration written via

the programming interface needs to be re-written after any

power cycle or reset. Please contact IDT if a specific

factory-programmed configuration is desired.

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2

I C Mode Operation

2

The device acts as a slave device on the I C bus using one of

2

the two I C addresses (0xD0 or 0xD4) to allow multiple

devices to be used in the system. The interface accepts

byte-oriented block write and block read operations. Two

address bytes specify the register address of the byte position

of the first register to write or read. Data bytes (registers) are

accessed in sequential order from the lowest to the highest

byte (most significant bit first). Read and write block transfers

can be stopped after any complete byte transfer. During a

write operation, data will not be moved into the registers until

the STOP bit is received, at which point, all data received in

the block write will be written simultaneously.

2

For full electrical I C compliance, it is recommended to use

external pull-up resistors for SDATA and SCLK. The internal

pull-down resistors have a size of 100k typical.

Current Read

S

Dev Addr + R

A

Data 0

A

Data 1

A

Data n

Data 0

A

Abar

A

P

Sequential Read

S

Dev Addr + W

Reg start Addr

A

Sr

Dev Addr + R

A

Data 1

A

Data n

Abar

P

Sequential Write

S

Dev Addr + W

Data 0

A

Data 1

A

Data n

A

P

S = start

from master to slave

from slave to master

Sr = repeated start

A = acknowledge

Abar= none acknowledge

P = stop

I²C Slave Read and Write Cycle Sequencing

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Table 6:I²C Bus DC Characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

2

Input HIGH Level

For SEL1/SDA pin and

SEL0/SCL pin.

V

0.7xV

5.5

V

IH

DDD

Input LOW Level

For SEL1/SDA pin and

SEL0/SCL pin.

V

GND-0.3

0.3xV

V

IL

DDD

Hysteresis of Inputs

Input Leakage Current

Output LOW Voltage

V

0.05xV

-1

V

µA

V

HYS

DDD

I

30

IN

I_OL= 3 mA

V

0.4

OL

Table 7:I²C Bus AC Characteristics

Symbol

Parameter

Min

10

Typ

Max

Unit

kHz

µs

Serial Clock Frequency (SCL)

F

400

SCLK

Bus free time between STOP and START

Setup Time, START

t

1.3

0.6

0.1

0

BUF

t

µs

SU:START

HD:START

Hold Time, START

t

µs

Setup Time, data input (SDA)

Hold Time, data input (SDA) ¹

Output data valid from clock

Capacitive Load for Each Bus Line

Rise Time, data and clock (SDA, SCL)

Fall Time, data and clock (SDA, SCL)

HIGH Time, clock (SCL)

t

µs

SU:DATA

t

µs

HD:DATA

t

0.9

400

300

µs

OVD

C

pF

ns

B

t

20 + 0.1xC

R

B

t

20 + 0.1xC

ns

F

t

0.6

1.3

0.6

µs

HIGH

LOW Time, clock (SCL)

t

µs

LOW

Setup Time, STOP

t

µs

SU:STOP

Note 1: A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the V_IH(MIN) of the SCL signal) to bridge

the undefined region of the falling edge of SCL.

Note 2: I2C inputs are 5V tolerant.

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Table 8:Absolute Maximum Ratings

Stresses above the ratings listed below can cause permanent damage to the 5P49V5927. These ratings, which are standard values for IDT

commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in

the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect

product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range.

Item

Rating

Supply Voltage, V_DDA,V_DDD,V_DDO

3.465V

Inputs

XIN/REF

CLKIN, CLKINB

Other inputs

0V to 1.2V voltage swing

0V to 1.2V voltage swing single-ended

-0.5V to V_DDD

Outputs, V_DDO(LVCMOS)

Outputs, I_O(SDA)

-0.5V to V_DDO+ 0.5V

10mA

Package Thermal Impedance, _JA

Package Thermal Impedance, _JC

Storage Temperature, T_STG

ESD Human Body Model

Junction Temperature

42C/W (0 mps)

41.8C/W (0 mps)

-65C to 150C

2000V

125°C

Table 9:Recommended Operation Conditions

Symbol

Parameter

Min

1.71

Typ

1.8

2.5

3.3

Max

1.89

Unit

V

Power supply voltage for supporting 1.8V outputs

Power supply voltage for supporting 2.5V outputs

Power supply voltage for supporting 3.3V outputs

Power supply voltage for core logic functions

V

DDOX

2.375

3.135

1.71

2.625

3.465

V

DDD

DDA

Analog power supply voltage. Use filtered analog power

supply.

V

1.71

V

Operating temperature, ambient

T

-40

+85

15

°C

pF

A

Maximum load capacitance (3.3V LVCMOS only)

External reference crystal

C

LOAD_OUT

F

1

40

MHz

IN

External reference clock CLKIN, CLKINB

200

5

Power up time for all V_DDs to reach minimum specified

voltage (power ramps must be monotonic)

t

0.05

ms

PU

Note: V_DDO1, V_DDO2, and V_DDO3 must be powered on either before or simultaneously with V_DDD, V_DDAand V_DDO0.

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Table 10:Input Capacitance, LVCMOS Output Impedance, and Internal Pull-down

Resistance ^(T= +25 °C)

A

Symbol

Parameter

Min

Typ

Max Unit

Input Capacitance (CLKIN, CLKINB, CLKSEL, SD/OE, SEL1/SDA,

SEL0/SCL)

C

3

7

pF

IN

CLKSEL, SD/OE, SEL1/SDA, SEL0/SCL, CLKIN, CLKINB,

OUT0_SEL_I2CB

Pull-down

Resistor

100

300

k

LVCMOS Output Driver Impedance (V_DDO= 1.8V, 2.5V, 3.3V)

Programmable input capacitance at XIN/REF

R

17



OUT

XIN/REF

XOUT

0

8

pF

Programmable input capacitance at XOUT

Table 11:Crystal Characteristics

Parameter

Test Conditions

Min

Typ

Max

Units

Mode of Oscillation

Fundamental

Frequency

8

25

10

40

100

7

MHz



Equivalent Series Resistance (ESR)

Shunt Capacitance

pF

Load Capacitance (C_L) @ <=25MHz

Load Capacitance (C_L) > 25M to 40M

Maximum Crystal Drive Level

6

8

12

8

pF

100

µW

Note: Typical crystal used is FOX 603-25-150. For different reference crystal options please go to www.foxonline.com.

Table 12:DC Electrical Characteristics

Symbol

Parameter

Test Conditions

Min

Typ

Max

Unit

3

Core Supply Current

100 MHz on all outputs,

25 MHz REFCLK

Iddcore

30

34

mA

1,2

Output Buffer Supply Current LVCMOS, 50 MHz, 3.3V V_DDOX,

LVCMOS, 50 MHz, 2.5V V_DDOX,

Iddox

16

14

12

36

27

16

10

18

16

14

42

32

19

14

mA

LVCMOS, 50 MHz, 1.8V V_DDOX,

1,2

LVCMOS, 200 MHz, 3.3V V_DDOX,

LVCMOS, 200 MHz, 2.5V V_DDOX,

LVCMOS, 200 MHz, 1.8V V_DDOX,

SD asserted, I²C Programming

Core Power Down Current

1.Single CMOS driver active.

Iddpd

2.Measured into a 5” 50 Ohm trace with 2 pF load.

3. Iddcore = IddA + IddD, no loads.

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Table 13:Electrical Characteristics – Differential Clock Input Parameters ^1,2(Supply

Voltage V

, V

0 = 3.3V ±5%, 2.5V ±5%, 1.8V ±5%, TA = -40°C to +85°C)

DDO

DDA

DDD

Symbol

Parameter

Test Conditions

Min

0.55

Typ

Max

1.7

0.4

1200

8

Unit

V

Input HIGH Voltage–CLKIN, CLKINB

Input LOW Voltage–CLKIN, CLKINB

Input Amplitude - CLKIN, CLKINB

Input Slew Rate - CLKIN, CLKINB

Input Leakage Low Current

Single-ended input

V

IH

Single-ended input

Peak to Peak value, single-ended

Measured differentially

V_IN= GND

V

GND - 0.3

200

V

IL

SWING

V

mV

V/ns

µA

%

dv/dt

0.4

I

-5

5

IL

Input Leakage High Current

Input Duty Cycle

V_IN= 1.7V

I

20

IH

Measurement from differential

waveform

d

45

55

TIN

1. Guaranteed by design and characterization, not 100% tested in production.

2. Slew rate measured through ±75mV window centered around differential zero.

1

Table 14:DC Electrical Characteristics for 3.3V LVCMOS (V

= 3.3V±5%, TA = -40°C to +85°C)

DDO

Symbol

Parameter

Output HIGH Voltage

Output LOW Voltage

Test Conditions

Min

Typ

Max

Unit

V

I_OH= -15mA

V

2.4

V

DDO

OH

I_OL= 15mA

V

0.4

5

V

OL

Output Leakage Current

(OUT1~2)

Tri-state outputs, V_DDO= 3.465V

I

µA

OZDD

Output Leakage Current

(OUT0)

Tri-state outputs, V_DDO= 3.465V

30

µA

V

OZDD

Input HIGH Voltage

Input LOW Voltage

Input HIGH Voltage

Input LOW Voltage

Single-ended inputs - CLKSEL,

SD/O

V

0.7xVDDD

GND - 0.3

2

V

+ 0.3

DDD

IH

Single-ended inputs, CLKSEL,

SD/OE

V

0.3xVDDD

0 + 0.3

V

IL

Single-ended input

OUT0_SEL_I2CB

V

IH

DDO

Single-ended input

OUT0_SEL_I2CB

V

GND - 0.3

0.4

V

IL

Input HIGH Voltage

Input LOW Voltage

Input Rise/Fall Time

Single-ended input - XIN/REF

V

0.8

1.2

0.4

V

IH

V

GND - 0.3

IL

CLKSEL, SD/OE, SEL1/SDA,

SEL0/SCL

TR/TF

300

nS

1. See “Recommended Operating Conditions” table.

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Table 15:DC Electrical Characteristics for 2.5V LVCMOS (V

= 2.5V±5%, TA = -40°C to +85°C)

DDO

Symbol

Parameter

Output HIGH Voltage

Output LOW Voltage

Test Conditions

Min

Typ

Max

Unit

V

I_OH= -12mA

V

0.7xV

DDO

OH

I_OL= 12mA

V

0.4

5

V

OL

Output Leakage Current

(OUT1~2)

Tri-state outputs, V_DDO= 3.465V

I

µA

OZDD

Output Leakage Current

(OUT0)

Tri-state outputs, V_DDO= 3.465V

30

µA

V

OZDD

Input HIGH Voltage

Input LOW Voltage

Input HIGH Voltage

Input LOW Voltage

Single-ended inputs - CLKSEL,

SD/OE

V

0.7xVDDD

GND - 0.3

1.7

V

+ 0.3

DDD

IH

Single-ended inputs, CLKSEL,

SD/OE

V

0.3xVDDD

0 + 0.3

V

IL

Single-ended input

OUT0_SEL_I2CB

V

IH

DDO

Single-ended input

OUT0_SEL_I2CB

V

GND - 0.3

0.4

V

IL

Input HIGH Voltage

Input LOW Voltage

Input Rise/Fall Time

Single-ended input - XIN/REF

V

0.8

1.2

0.4

V

IH

V

GND - 0.3

IL

CLKSEL, SD/OE, SEL1/SDA,

SEL0/SCL

TR/TF

300

nS

Table 16:DC Electrical Characteristics for 1.8V LVCMOS ^(V

= 1.8V±5%, TA = -40°C to +85°C)

DDO

Symbol

Parameter

Output HIGH Voltage

Output LOW Voltage

Test Conditions

Min

Typ

Max

Unit

V

IOH = -8mA

V

0.7 xV

V

DDO

OH

DDO

IOL = 8mA

V

0.25 x V

5

V

OL

DDO

Output Leakage Current

(OUT1~2)

Tri-state outputs, V_DDO= 3.465V

I

µA

OZDD

Output Leakage Current

(OUT0)

Tri-state outputs, V_DDO= 3.465V

30

µA

V

OZDD

Input HIGH Voltage

Input LOW Voltage

Input HIGH Voltage

Input LOW Voltage

Single-ended inputs - CLKSEL,

SD/OE

V

0.7 * V

V

+ 0.3

DDD

IH

DDD

Single-ended inputs, CLKSEL,

SD/OE

V

GND - 0.3

0.65 * V

0.3 * V

V

IL

DDD

Single-ended input

OUT0_SEL_I2CB

V

0

V 0 + 0.3

DDO

V

IH

DDO

Single-ended input

OUT0_SEL_I2CB

V

GND - 0.3

0.4

V

IL

Input HIGH Voltage

Input LOW Voltage

Input Rise/Fall Time

Single-ended input - XIN/REF

V

0.8

1.2

0.4

300

V

IH

V

GND - 0.3

IL

CLKSEL, SD/OE, SEL1/SDA,

SEL0/SCL

TR/TF

nS

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Table 17:AC Timing Electrical Characteristics

(V_DDO= 3.3V+5% or 2.5V+5% or 1.8V ±5%, TA = -40°C to +85°C)

(Spread Spectrum Generation = OFF)

Symbol

Parameter

Test Conditions

Min. Typ. Max. Units

1

Input Frequency

Input frequency limit (XIN)

f

8

1

40

200

2900

150

0.9

MHz

%

IN

Input frequency limit (REF)

Input frequency limit (CLKIN, CLKINB)

Single ended clock output limit (LVCMOS)

VCO operating frequency range

PFD operating frequency range

Input frequency = 25MHz

1

Output Frequency

VCO Frequency

PFD Frequency

Loop Bandwidth

Input Duty Cycle

Output Duty Cycle

f

1

OUT

f

2600

VCO

1

f

1

PFD

f

0.06

45

BW

Duty Cycle

t2

50

55

5

Measured at VDD/2, all outputs except

Reference output OUT0, VDDOX= 2.5V or 3.3V

t3

45

55

%

Measured at VDD/2, all outputs except

Reference output OUT0, VDDOX=1.8V

40

30

50

60

70

%

Measured at VDD/2, Reference output

OUT0 (5MHz - 120MHz) with 50% duty cycle input

Measured at VDD/2, Reference output

OUT0 (150.1MHz - 200MHz) with 50% duty cycle

input

2

Slew Rate, SLEW[1:0] = 00

Slew Rate, SLEW[1:0] = 01

Slew Rate, SLEW[1:0] = 10

Slew Rate, SLEW[1:0] = 11

Slew Rate, SLEW[1:0] = 00

Slew Rate, SLEW[1:0] = 01

Slew Rate, SLEW[1:0] = 10

Slew Rate, SLEW[1:0] = 11

Slew Rate, SLEW[1:0] = 00

Slew Rate, SLEW[1:0] = 01

Slew Rate, SLEW[1:0] = 10

Slew Rate, SLEW[1:0] = 11

Single-ended 3.3V LVCMOS output clock rise and

fall time, 20% to 80% of VDDO

(Output Load = 5 pF) VDDOX=3.3V

t4

1.0

1.2

1.3

1.7

0.6

0.7

0.6

1.0

0.3

0.4

0.7

2.2

2.3

2.4

2.7

0.3

1.4

1.7

0.7

0.8

0.9

1.2

V/ns

Single-ended 2.5V LVCMOS output clock rise and

fall time, 20% to 80% of VDDO

(Output Load = 5 pF) VDDOX=2.5V

Single-ended 1.8V LVCMOS output clock rise and

fall time, 20% to 80% of VDDO

(Output Load = 5 pF) VDDOX=1.8V

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5P49V5927 DATASHEET

Symbol

Parameter

Test Conditions

Min. Typ. Max. Units

Clock Jitter

Cycle-to-Cycle jitter (Peak-to-Peak), multiple

output frequencies switching, LVCMOS outputs

(1.8 to 3.3V nominal output voltage)

OUT0=25MHz

t6

74

ps

OUT1=100MHz

OUT2=125MHz

OUT3=156.25MHz

RMS Phase Jitter (12kHz to 5MHz integration

range) reference clock (OUT0),

25 MHz LVCMOS outputs (1.8 to 3.3V nominal

output voltage).

0.5

ps

OUT0=25MHz

OUT1=100MHz

OUT2=125MHz

OUT3=156.25MHz

RMS Phase Jitter (12kHz to 20MHz integration

range) LVCMOS output, VDDO = 3.465V, 25MHz

crystal, 156.25MHz output frequency

OUT0=25MHz

0.75

1.5

ps

OUT1=100MHz

OUT2=125MHz

OUT3=156.25MHz

t7

Output Skew

Startup Time

Skew between the same frequencies, with outputs

using the same driver format and phase delay set

to 0ns.

75

ps

ms

t8 ³

t9 ⁴

PLL lock time from power-up, measured after all

VDD's have raised above 90% of their target

value.

10

4

PLL lock time from shutdown mode

3

1. Practical lower frequency is determined by loop filter settings.

2. A slew rate of 2.75V/ns or greater should be selected for output frequencies of 100MHz or higher.

3. Includes loading the configuration bits from memory to PLL registers. It does not include memory programming/write time.

4. Actual PLL lock time depends on the loop configuration.

Table 18:Spread Spectrum Generation Specifications

Symbol

Parameter

Output Frequency

Mod Frequency

Spread Value

Description

Min Typ Max

Unit

MHz

kHz

Output Frequency Range

Modulation Frequency

f

5

300

OUT

f

30 to 63

MOD

Amount of Spread Value (programmable) - Center Spread

Amount of Spread Value (programmable) - Down Spread

f

±0.25% to ±2.5%

-0.5% to -5%

%f

OUT

SPREAD

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5P49V5927 DATASHEET

Test Circuits and Loads

V_DDOx

V_DDD

V_DDA

OUTx

CLK_OUT

0.1µF

C_L

GND

Test Circuits and Loads for Outputs

Typical Phase Noise at 100MHz (3.3V, 25°C)

NOTE: All outputs operational at 100MHz, Phase Noise Plot with Spurs On.

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5P49V5927 DATASHEET

5P49V5927 Applications Schematic

2

1

2

1

2

E P A D

3 3

E P A D

3 2

1

2

1

2

E P A D

3 1

E P A D

3 0

E P A D

2 9

E P A D

2 8

E P A D

2 7

E P A D

2 6

E P A D

2 5

1

2

1

2

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5P49V5927 DATASHEET

Overdriving the XIN/REF Interface

LVCMOS Driver

The XIN/REF input can be overdriven by an LVCMOS driver

or by one side of a differential driver through an AC coupling

capacitor. The XOUT pin can be left floating. The amplitude of

the input signal should be between 500mV and 1.2V and the

slew rate should not be less than 0.2V/ns. Figure General

Diagram for LVCMOS Driver to XTALInput Interface shows an

example of the interface diagram for a LVCMOS driver.

This configuration has three properties; the total output

impedance of Ro and Rs matches the 50 ohm transmission

line impedance, the Vrx voltage is generated at the CLKIN

inputs which maintains the LVCMOS driver voltage level

across the transmission line for best S/N and the R1-R2

voltage divider values ensure that the clock level at XIN is less

than the maximum value of 1.2V.

VDD

XOUT

C3

Ro

Rs

Zo = 50 Ohm

R1

V_XIN

XIN / REF

Ro + Rs

LVCMOS

=

50 ohms

0. 1 uF

R2

General Diagram for LVCMOS Driver to XTAL Input Interface

Table 19 Nominal Voltage Divider Values vs LVCMOS VDD for

XIN shows resistor values that ensure the maximum drive

level for the XIN/REF port is not exceeded for all combinations

of 5% tolerance on the driver VDD, the VersaClock VDDAand

5% resistor tolerances. The values of the resistors can be

adjusted to reduce the loading for slower and weaker

LVCMOS driver by increasing the voltage divider attenuation

as long as the minimum drive level is maintained over all

tolerances. To assist this assessment, the total load on the

driver is included in the table.

Table 19: Nominal Voltage Divider Values vs LVCMOS VDD for XIN

LVCMOS Driver VDD

Ro+Rs

50.0

R1

130

100

62

R2

75

V_XIN (peak) Ro+Rs+R1+R2

3.3

2.5

1.8

0.97

1.00

0.97

255

250

242

50.0

100

130

50.0

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5P49V5927 DATASHEET

Wiring the Differential Input to Accept Single-Ended Levels

Figure Recommended Schematic for Wiring a Differential

Input to Accept Single-ended Levels shows how a differential

input can be wired to accept single ended levels. This

configuration has three properties; the total output impedance

of Ro and Rs matches the 50 ohm transmission line

impedance, the Vrx voltage is generated at the CLKIN inputs

which maintains the LVCMOS driver voltage level across the

transmission line for best S/N and the R1-R2 voltage divider

values ensure that Vrx p-p at CLKIN is less than the maximum

value of 1.2V.

VDD

Ro

Rs

Zo = 50 Ohm

R1

Vrx

CLKIN

Ro + Rs = 50

LVCMOS

CLKINB

R2

VersaClock 5 Receiver

Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels

Table 20 Nominal Voltage Divider Values vs Driver VDD

shows resistor values that ensure the maximum drive level for

the CLKIN port is not exceeded for all combinations of 5%

tolerance on the driver VDD, the VersaClock Vddo_0 and 5%

resistor tolerances. The values of the resistors can be

adjusted to reduce the loading for slower and weaker

LVCMOS driver by increasing the impedance of the R1-R2

divider. To assist this assessment, the total load on the driver

is included in the table.

Table 20: Nominal Voltage Divider Values vs Driver VDD

LVCMOS Driver VDD

Ro+Rs

50.0

R1

130

100

62

R2

75

Vrx (peak) Ro+Rs+R1+R2

3.3

2.5

1.8

0.97

1.00

0.97

255

250

242

50.0

100

130

50.0

HCSL Differential Clock Input Interface

CLKIN/CLKINB will accept DC coupled HCSL signals.

Zo=50ohm

Q

CLKIN

Zo=50ohm

nQ

CLKINB

VersaClock 5 Receiver

CLKIN, CLKINB Input Driven by an HCSL Driver

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5P49V5927 DATASHEET

3.3V Differential LVPECL Clock Input Interface

The logic levels of 3.3V LVPECL and LVDS can exceed VIH

max for the CLKIN/B pins. Therefore the LVPECL levels must

be AC coupled to the VersaClock differential input and the DC

bias restored with external voltage dividers. A single table of

bias resistor values is provided below for both for 3.3V

LVPECL and LVDS. Vbias can be VDDD, V_DDOXor any other

available voltage at the VersaClock receiver that is most

conveniently accessible in layout.

Vbias

Rpu1

Rpu2

C5

0.01µF

Zo=50ohm

CLKIN

C6

0.01µF

CLKINB

R9

50ohm

R10

50ohm

+3.3V LVPECL

Driver

VersaClock 5 Receiver

R13

4.7kohm

R15

4.7kohm

RTT

50ohm

CLKIN, CLKINB Input Driven by a 3.3V LVPECL Driver

Vbias

Rpu1

Rpu2

C1

0.1µF

Zo=50ohm

CLKIN

C2

0.1µF

Rterm

100ohm

CLKINB

VersaClock 5 Receiver

LVDS Driver

R2

4.7kohm

R1

4.7kohm

CLKIN, CLKINB Input Driven by an LVDS Driver

Table 21: Bias Resistors for 3.3V LVPECL and LVDS Drive to CLKIN/B

Vbias

(V)

Rpu1/2

(kohm)

CLKIN/B Bias Voltage

(V)

3.3

2.5

1.8

22

15

10

0.58

0.60

0.58

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NOVEMBER 11, 2016

5P49V5927 DATASHEET

2.5V Differential LVPECL Clock Input Interface

The maximum DC 2.5V LVPECL voltage meets the VIH max

CLKIN requirement. Therefore, 2.5V LVPECL can be

connected directly to the CLKIN terminals without AC coupling

Zo=50ohm

CLKIN

Zo=50ohm

CLKINB

+2.5V LVPECL

Driver

Versaclock 5 Receiver

R1

50ohm

R2

50ohm

RTT

18ohm

CLKIN, CLKINB Input Driven by a 2.5V LVPECL Driver

NOVEMBER 11, 2016

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PROGRAMMABLE CLOCK GENERATOR

5P49V5927 DATASHEET

Package Outline and Package Dimensions (24-pin 4mm x 4mm VFQFPN)

PROGRAMMABLE CLOCK GENERATOR

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NOVEMBER 11, 2016

5P49V5927 DATASHEET

Package Outline and Package Dimensions, cont. (24-pin 4mm x 4mm VFQFPN)

NOVEMBER 11, 2016

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PROGRAMMABLE CLOCK GENERATOR

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Marking Diagram

5927B

ddd

YWW**$

1. Line 1 is the truncated part number.

2. “ddd” denotes dash code.

3. “YWW” is the last digit of the year and week that the part was assembled.

4. “**” denotes lot number.

5. “$” denotes mark code.

Ordering Information

Part / Order Number Shipping Packaging

Package

24-pin VFQFPN

Temperature

-40° to +85°C

5P49V5927BdddNLGI

5P49V5927BdddNLGI8

Tubes

Tape and Reel

“G” after the two-letter package code denotes Pb-Free configuration, RoHS compliant.

Revision History

Rev.

A

Date

Originator Description of Change

12/04/14 B. Chandhoke Initial release.

B

07/13/15 B. Chandhoke 1. Added conditions text and min/max values for VIH/VIL.

2. Updated 1.8V, 2.5V, and 3.3V VIH/VIL conditions text and min/max values for "Single-ended

inputs - CLKSEL, SD/OE"

3. Changed name of parameter "Lock Time" to "Startup Time"

4. Added IDT and Fox crystal references.

C

D

E

F

10/15/15 B. Chandhoke Changed device revision from “A” to “B”.

11/12/15 B. Chandhoke Updated fVCO, t3, and t4 parameters in AC Characteristics table.

09/19/16

10/19/16

11/11/16

Y. Guo

Corrected typo [Ci1 to Cs1] on page 6.

Removed IDT crystal part number

G

Corrected typo for the order of t4 Slew Rates

PROGRAMMABLE CLOCK GENERATOR

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NOVEMBER 11, 2016

Corporate Headquarters

6024 Silver Creek Valley Road

San Jose, CA 95138 USA

www.IDT.com

Sales

Tech Support

www.idt.com/go/support

1-800-345-7015 or 408-284-8200

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型号：	5P49V5927
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	Programmable Clock Generator
文件：	总27页 (文件大小：361K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

5P49V5927 [IDT]

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