5V41315NLGI8 [IDT]
2 OUTPUT PCIE GEN1-2-3 SYNTHESIZER;
| 型号： | 5V41315NLGI8 |
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| 描述： | 2 OUTPUT PCIE GEN1-2-3 SYNTHESIZER 时钟 PC 输出元件 外围集成电路 晶体 |
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DATASHEET
2 OUTPUT PCIE GEN1-2-3 SYNTHESIZER
IDT5V41315
Recommended Applications
Features/Benefits
PCIe Gen1-2-3 Synthesizer for Common and
SRNS-clocked systems
• 16-pin TSSOP or VFQFPN package; small board
footprint
• Outputs can be terminated to LVDS; can drive a wider
variety of devices
General Description
• OE control pin; greater system power management
The IDT5V41315 is a PCIe Gen1-2-3 clock synthesizer
suitable for use in both Common-Clocked and Separate
Reference clock with No Spread (SRNS) timing
architectures. The IDT5V41315 uses a 25MHz input to
generate 4 different output frequencies. The output
frequency is selectable via select pins.
• Industrial temperature range available; supports
demanding embedded applications
Key Specifications
• Cycle-to-cycle jitter: 80ps
• Output-to-output skew: <50 ps
Output Features
• PCIe Gen2 phase jitter: <3.0ps RMS (Common Clock)
• PCIe Gen3 phase jitter: <1.0ps RMS (Common Clock)
• Low Phase Noise: 12KHz to 20MHz <6ps RMS
• 2 - 0.7V current mode differential HCSL output pairs
Block Diagram
VDD
2
CLK0
CLK0
Control
Logic
S1:S0
2
Phase Lock Loop
CLK1
CLK1
X1/ICLK
Clock
Buffer/
Crystal
Oscillator
25 MHz
crystal or clock
X2
2
Optional tuning crystal
capacitors
Rr(IREF)
GND
OE
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Pin Assignments
1
2
3
4
5
6
7
8
VDDXD
CLK0
16
15
14
13
12
11
10
9
S0
S1
16 15 14 13
NC
X1/ICLK
X2
CLK0
S1 1
NC 2
X1/CLK 3
X2 4
12 GNDODA
11 VDDODA
10 CLK1
GNDODA
VDDODA
CLK1
5V41315
9 CLK1#
OE
5
6
7
8
GNDXD
NC
CLK1
IREF
16-pin VFQFPN
16-pin (173 mil) TSSOP
Output Select Table 1 (MHz)
S1
0
S0
0
CLK(1:0), CLK(1:0)
25M
100M
125M
200M
0
1
1
0
1
1
Pin Descriptions
VFQFPN TSSOP Pin
Pin Number Number
Pin Name Pin Type Pin Description
16
1
2
3
4
5
6
7
1
2
3
4
5
6
7
8
S0
S1
NC
X1/ICLK
X2
OE
Input
Input
--
Select pin 0. See Table1. Internal pull-up resistor.
Select pin 1. See Table 1. Internal pull-up resistor.
No connect.
Input
Crystal or clock input. Connect to a 25 MHz crystal or single ended clock.
Output Crystal connection. Leave unconnected for clock input.
Input
Power
--
Output enable. Tri-states outputs and device is not shut down. Internal pull-up resistor.
Connect to ground.
No connect.
GNDXD
NC
Precision resistor attached to this pin is connected to the internal current reference,
typically 475 ohm.
8
9
IREF
Output
9
10
11
12
13
14
15
16
CLK1
CLK1
VDDODA
GNDODA
CLK0
Output HCSL complementary clock output 1.
Output HCSL true clock output 1.
10
11
12
13
14
15
Power
Power
Connect to voltage supply +3.3 V for output driver and analog circuits
Connect to ground.
Output HCSL complementary clock output 0.
Output HCSL true clock output 0.
CLK0
VDDXD
Power
Connect to voltage supply +3.3 V for crystal oscillator and digital circuit.
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Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the IDT5V41315. These ratings are stress ratings
only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of
the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product
reliability. Electrical parameters are guaranteed only over the recommended operating temperature range.
Item
Supply Voltage, VDDXD, VDDODA
All Inputs and Outputs
Rating
4.6 V
-0.5 V to VDD+0.5 V
-65 to +150C
125C
Storage Temperature
Junction Temperature
Soldering Temperature
260C
ESD Protection (Input)
2000 V min. (HBM)
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V ±±%, T = T
A
AMBIENT
Parameter
Supply Voltage
Symbol
Conditions
Min.
3.135
-40
Typ.
3.3
Max.
3.465
+85
Units
V
V
Ambient Operating
Temperature
T
Industrial Temperature range
+25
°C
AMBIENT
1
Input High Voltage
V
S0, S1, OE, ICLK
S0, S1, OE, ICLK
0 < Vin < VDD
2.2
VSS-0.3
-5
VDD +0.3
V
IH
1
Input Low Voltage
V
0.8
5
V
IL
2
Input Leakage Current
I
A
mA
mA
pF
pF
pF
nH
k
k
IL
Operating Supply Current
@100 MHz
I
R =33R =50, C =2 pF
63
42
85
50
7
DD
S
P
L
I
OE =Low
DDOE
Input Capacitance
Output Capacitance
X1, X2 Capacitance
Pin Inductance
C
Input pin capacitance
Output pin capacitance
IN
C
6
OUT
C
5
INX
PIN
L
5
Output Impedance
Pull-up Resistor
Z
CLK outputs
S0, S1, OE
3.0
O
R
100
PU
1. Single edge is monotonic when transitioning through region.
2. Inputs with pull-ups/-downs are not included.
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AC Electrical Characteristics - CLK0/CLK1, CLK0/CLK1
Unless stated otherwise, VDD=3.3 V 5%, T = T
A
AMBIENT
Parameter
Input Frequency
Symbol
Conditions
Min.
Typ.
25
Max.
Units
MHz
MHz
MHz
mV
mV
mV
mV
ps
Output Frequency
HCSL termination
LVDS termination
HCSL
25
25
200
100
850
1,2
Output High Voltage
V
OH
1,2
Output Low Voltage
V
HCSL
-150
250
OL
1,2
Crossing Point Voltage
Crossing Point Voltage
Absolute
550
140
80
1,2,4
Variation over all edges
1,3
Jitter, Cycle-to-Cycle
Frequency Synthesis Error
All outputs
150mV
0
ppm
V/ns
V/ns
ps
1,3
Rise Time
t
1
1
4
OR
1,3
Fall Time
t
150mV
4
OF
1,2
Rise/Fall Time Variation
125
50
Output to Output Skew
ps
1,3
Duty Cycle
45
55
%
5
Output Enable Time
All outputs
50
50
100
100
1.8
ns
5
Output Disable Time
All outputs
ns
Stabilization Time
t
From power-up VDD=3.3 V
ms
STABLE
Note 1: Test setup is R =33R =50 with C =2 pF, Rr = 475 (1%).
S
P
L
Note 2: Measurement taken from a single-ended waveform.
Note 3: Measurement taken from a differential waveform.
Note 4: Measured at the crossing point where instantaneous voltages of both CLK and CLK are equal.
Note 5: CLK pins are tri-stated when OE is low asserted. CLK is driven differential when OE is high.
Electrical Characteristics - Differential Phase Jitter Parameters
TA = TAMBIENT, Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
Symbol
tjphaseG1
Conditions
PCIe Gen 1
Min
Typ
32
Max
86
Units Notes
ps (p-p) 1,2,3
PCIe Gen 2
10kHz < f < 1.5MHz
PCIe Gen 2
ps
tjphaseG2Lo
tjphaseG2High
tjphaseG3
0.7
2.3
0.6
3
3.1
1
1,2,3
(RMS)
ps
(RMS)
ps
(RMS)
1,2,3
Jitter, Phase
1.5MHz < f < Nyquist (50MHz)
PCIe Gen 3
1,2,3
ps
N/A
tjphase12K20M
12kHz-20MHz
1,2,3
(RMS)
1Guaranteed by design and characterization, not 100% tested in production.
2See http://www.pcisig.com for complete specs
3Applies to 100MHz
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Applications Information
External Components
A minimum number of external components are required for
proper operation.
Output Structures
6*IREF
IREF
=2.3 mA
Decoupling Capacitors
Decoupling capacitors of 0.01F should be connected
between each VDD pin and the ground plane, as close to
the VDD pin as possible. Do not share ground vias between
components. Route power from power source through the
capacitor pad and then into ICS pin.
Crystal
See Output Termination
Sections
A 25 MHz fundamental mode parallel resonant crystal
should be used. This crystal must have less than 300 ppm
of error across temperature in order for the IDT5V41315 to
meet PCI Express specifications.
RR 475
General PCB Layout Recommendations
Crystal Capacitors
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
Crystal capacitors are connected from pins X1 to ground
and X2 to ground to optimize the accuracy of the output
frequency.
1. Each 0.01µF decoupling capacitor should be mounted on
the component side of the board as close to the VDD pin as
possible.
C = Crystal’s load capacitance in pF
L
Crystal Capacitors (pF) = (C - 8) * 2
L
2. No vias should be used between decoupling capacitor
and VDD pin.
For example, for a crystal with a 16 pF load cap, each
external crystal cap would be 16 pF. (16-8)*2=16.
3. The PCB trace to VDD pin should be kept as short as
possible, as should the PCB trace to the ground via.
Distance of the ferrite bead and bulk decoupling from the
device is less critical.
Current Source (Iref) Reference Resistor - R
R
If board target trace impedance (Z) is 50, then R = 475
R
(1%), providing IREF of 2.32 mA. The output current (I ) is
equal to 6*IREF.
OH
4. An optimum layout is one with all components on the
same side of the board, minimizing vias through other signal
layers (any ferrite beads and bulk decoupling capacitors can
be mounted on the back). Other signal traces should be
routed away from the IDT5V41315.This includes signal
traces just underneath the device, or on layers adjacent to
the ground plane layer used by the device.
Output Termination
The PCI-Express differential clock outputs of the
IDT5V41315 are open source drivers and require an
external series resistor and a resistor to ground. These
resistor values and their allowable locations are shown in
detail in the PCI-Express Layout Guidelines section.
The IDT5V41315 can also be configured for LVDS
compatible voltage levels. See the LVDS Compatible
Layout Guidelines section.
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Layout Guidelines
SRC Reference Clock
Common Recommendations for Differential Routing
L1 length, route as non-coupled 50ohm trace
L2 length, route as non-coupled 50ohm trace
L3 length, route as non-coupled 50ohm trace
Dimension or Value
0.5 max
0.2 max
0.2 max
33
Unit Figure
inch
inch
inch
ohm
ohm
1
1
1
1
1
Rs
Rt
49.9
Down Device Differential Routing
L4 length, route as coupled microstrip 100ohm differential trace
L4 length, route as coupled stripline 100ohm differential trace
2 min to 16 max
1.8 min to 14.4 max
inch
inch
1
1
Differential Routing to PCI Express Connector
L4 length, route as coupled microstrip 100ohm differential trace
L4 length, route as coupled stripline 100ohm differential trace
0.25 to 14 max
0.225 min to 12.6 max
inch
inch
2
2
Figure 1: Down Device Routing
L2
L1
Rs
Rs
L4
L4'
L2'
L1'
Rt
Rt
HCSL Output Buffer
PCI Express
Down Device
REF_CLK Input
L3' L3
Figure 2: PCI Express Connector Routing
L2
L1
Rs
L4
L4'
L2'
L1'
Rs
Rt
Rt
HCSL Output Buffer
PCI Express
Add-in Board
REF_CLK Input
L3' L3
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Alternative Termination for LVDS and other Common Differential Signals (figure 3)
Vdiff
0.45v
0.58
0.80
0.60
Vp-p
0.22v
0.28
0.40
0.3
Vcm
1.08
0.6
0.6
1.2
R1
33
33
33
33
R2
R3
R4
Note
150
78.7
78.7
174
100
137
none
140
100
100
100
100
ICS874003i-02 input compatible
Standard LVDS
R1a = R1b = R1
R2a = R2b = R2
Figure 3
L2
L1
R3
R4
R1a
R1b
L4
L4'
L2'
L1'
R2a
R2b
HCSL Output Buffer
Down Device
REF_CLK Input
L3'
L3
Cable Connected AC Coupled Application (figure 4)
Component
Value
Note
R5a, R5b
R6a, R6b
Cc
8.2K 5%
1K 5%
0.1 µF
Vcm
0.350 volts
Figure 4
3.3 Volts
R5a
R5b
Cc
L4
L4'
Cc
R6a
R6b
PCIe Device
REF_CLK Input
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Typical PCI-Express (HCSL) Waveform
700 mV
0
500 ps
500 ps
tOR
tOF
0.525 V
0.175 V
0.525 V
0.175 V
Typical LVDS Waveform
1325 mV
1000 mV
500 ps
500 ps
tOR
tOF
1250 mV
1150 mV
1250 mV
1150 mV
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Thermal Characteristics (16-TSSOP)
Parameter
Thermal Resistance Junction to
Ambient
Symbol
Conditions
Still air
Min.
Min.
Typ. Max. Units
78
70
68
37
C/W
C/W
C/W
C/W
JA
JA
JA
JC
1 m/s air flow
3 m/s air flow
Thermal Resistance Junction to Case
Thermal Characteristics (16-VFQFPN)
Parameter
Symbol
Conditions
Typ. Max. Units
Thermal Resistance Junction to
Ambient
Still air
63.2
55.9
51.4
65.8
C/W
C/W
C/W
C/W
JA
JA
JA
JC
1 m/s air flow
3 m/s air flow
Thermal Resistance Junction to Case
Marking Diagrams
16
9
IDT5V413
15PGGI
#YYWW$
XXX
YWW$
315I
1
8
Notes:
1. “XXX” denotes lot number.
2. “#” denotes die revision.
3. “YYWW” or “YWW” denotes date code
4. “$” denotes assembly location.
5. “G” after the two-letter package code designates RoHS compliant package.
6. “I” at the end of part number indicates industrial temperature range.
7. Bottom marking: country of origin if not USA (TSSOP package only).
IDT® 2 OUTPUT PCIE GEN1-2-3 SYNTHESIZER
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Ordering Information
Part / Order Number
5V41315PGGI
Marking
See Page 9
Shipping Packaging
Tubes
Package
Temperature
-40 to +85 C
-40 to +85 C
-40 to +85 C
-40 to +85 C
16-pin TSSOP
16-pin TSSOP
16-pin VFQFPN
16-pin VFQFPN
5V41315PGGI8
5V41315NLGI
Tape and Reel
Trays
5V41315NLGI8
Tape and Reel
“G” after the two-letter package code denotes Pb-Free configuration, RoHS compliant.
Revision History
Rev.
A
Date
Originator Description of Change
10/24/12
03/20/13
J. Chao
Initial release–preliminary
B
R. Wade
1. Updated General Description verbiage.
2. Added 16-pin VFQFPN package and pinout
3. Updated pin descriptions for both TSSOP and VFQFPN
4. Minor updates to AC/DC char tables.
5. Updated Differential Phase Jitter Parameters table; removed typical specs, added
‘tjphase12K20M’ parameter.
6. Added 16-pin VFQFPN package drawing/dimensions, thermal characteristics, marking diagram,
and ordering information
B
C
D
E
07/30/13
09/20/13
06/01/15
05/08/17
J. Chao
RDW
IH
Updated device top-side marking on VFQFPN package; removed “G”.
Changed Rise/Fall times to differential slew rates.
Added typical values to Differential Phase Jitter table.
Updated package outline drawings and legal disclaimer.
C.P.
IDT® 2 OUTPUT PCIE GEN1-2-3 SYNTHESIZER
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