5V9351PFI [IDT]
Clock Driver;
| 型号： | 5V9351PFI |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Driver |
| 文件： | 总10页 (文件大小：96K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LOW VOLTAGE PLL
CLOCK DRIVER
IDT5V9351
FEATURES:
DESCRIPTION:
• Fully integrated PLL
The IDT5V9351is a highperformance, zerodelay, lowskew, phase-lock
loop (PLL) clock driver. It has four banks of configurable outputs. The
IDT5V9351usesadifferentialPECLreferenceinputandanexternalfeedback
input. These features allow the IDT5V9351 to be used as a zero delay, low
skewfan-outbuffer. REF_SELallowsselectionbetweenPECLinputorTCLK,
a CMOS clock driver input.
• Output frequency up to 200MHz
• 2.5V and 3.3V Compatible
• Compatible with PowerPC™, Intel, and high performance RISC
microprocessors
• Output frequency configurable
• Cycle-to-cycle jitter max. 22ps RMS
• Compatible with MPC9351
IfPLL_ENissettolowandREF_SELtohigh,itwillbypassthePLL. Bydoing
so,theIDT5V9351willbeinclockbuffermode. AnyclockappliedtoTCLKwill
be divideddowntofouroutputbanks.
• Available in TQFP package
WhenPLL_ENis sethigh,PLLis enabled. AnyclockappliedtoTCLKwill
beclockedinbothphaseandfrequencytoFBIN. PECLclockisactivatedby
settingREF_SELtolow.
FUNCTIONALBLOCKDIAGRAM
(pullup)
PECL_CLK
0
0
1
PECL_CLK
÷2
÷4
÷8
0
1
REF
(pulldown)
D
D
D
D
Q
Q
Q
Q
1
QA
tCLK
REF_SEL
FBIN
(pulldown)
(pulldown)
PLL
FB
200 - 400MHz
0
1
QB
(pullup)
PLL_En
QC0
QC1
0
1
(pulldown)
fSELA
fSELB
fSELC
fSELD
(pulldown)
(pulldown)
QD0
QD1
QD2
QD3
QD4
0
1
(pulldown)
(pulldown)
OE
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
INDUSTRIAL TEMPERATURE RANGE
MARCH 2003
1
© 2003 Integrated Device Technology, Inc.
DSC-5972/18
IDT5V9351
LOWVOLTAGEPLLCLOCKDRIVER
INDUSTRIALTEMPERATURERANGE
ABSOLUTEMAXIMUMRATINGS(1)
PINCONFIGURATION
Symbol
VCC
VI
Description
Max.
–0.3 to +4.6
–0.3 to VCC+0.3
–0.3 to VCC+0.3
±20
Unit
V
Supply Voltage
Input Voltage
V
VO
DC Output Voltage
Input Current
V
IIN
mA
mA
° C
32 31 30 29 28 27 26 25
IO
DC Output Current
Storage Temperature
±50
1
2
3
4
5
6
7
8
24
23
22
21
20
19
VCCA
FBIN
fSELA
fSELB
fSELC
QC0
VCC
QC1
GND
QD0
VCC
QD1
GND
TSTG
–55 to +150
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
fSELD
GND
18
17
PECL_CLK
CAPACITANCE (TA = +25°C, F = 1.0MHz)
9
10 11 12 13 14 15 16
Symbol
Parameter
Min.
Typ.
Max.
—
Unit
pF
CIN
Input Capacitance
—
4
CPD
Power Dissipation
Capacitance
—
10
—
pF
TQFP
TOP VIEW
GENERALSPECIFICATIONS
Symbol
VTT
Description
Min.
Typ.
Max.
Unit
V
Output Termination Voltage
ESD (Human Body Model)
Latch-Up Immunity
VCC/2
HBM
LU
2000
200
V
mA
LOGICDIAGRAM(1,2)
RF
VCCA
VCC
10nF
CF
VCC
33...100nF
NOTES:
1. IDT5V9351 requires an external RC filter for the analog power supply pin VCCA.
2. For VCC = 2.5V, RF = 9-10Ω, CF = 22μF.
For VCC = 3.3V, RF = 5-15Ω, CF = 22μF.
2
IDT5V9351
LOWVOLTAGEPLLCLOCKDRIVER
INDUSTRIALTEMPERATURERANGE
PINDESCRIPTION
Terminal
Name
PECL-CLK
PECL-CLK
TCLK
No.
Type
Description
8, 9
I
Differentialclockreference,LOWvoltagepositiveECLinput
30
2
I
I
Single-endedreferenceclocksignalortestclock
Feedbacksignalinput
FBIN
REF_SEL
fSEL(D:A)
OE
32
I
Referenceclockinput
3, 4, 5, 6
10
I
Frequencycontrolpin
I
Outputenable/disable
QA
28
O
O
O
O
BankAclockoutput
QB
26
BankBclockoutput
QC(1:0)
QD(4:0)
22,24
12, 14, 16,
18,20
1
Bank C clock output
BankDclockoutput
VCCA
VCC
PWR
PWR
Positive power supply for PLL
11, 15, 19,
23,27
Positive power supply for I/O and core
GND
7, 13, 17, 21, Ground
25,29
Negative power supply
PLL_EN
31
I
PLL enable input. When set HIGH, PLL is enabled. When set LOW, PLL is disabled.
FUNCTIONALITY
Control
REF_SEL
PLL_EN
OE
Default
0
1
0
1
0
0
0
0
0
Selects PECL_CLK as reference clock
TestmodewithPLLDisabled
Outputsenabled
SelectsTCLKasreferenceclock
PLLEnabled
Outputsdisabled
QA = VCO ÷ 4
QB = VCO ÷ 8
QC = VCO ÷ 8
QD = VCO ÷ 8
FSELA
FSELB
FSELC
FSELD
QA = VCO ÷ 2
QB = VCO ÷ 4
QC = VCO ÷ 4
QD = VCO ÷ 4
NOTE:
1. Output frequency relationship with respect to input reference frequency CLK. QC1 is connected to FBIN.
3
IDT5V9351
LOWVOLTAGEPLLCLOCKDRIVER
INDUSTRIALTEMPERATURERANGE
FUNCTIONTABLE(1)
INPUTS
OUTPUTS
fSELA
0
fSELB
0
fSELC
0
fSELD
0
QA
QB
QC
QD
2 * CLK
2 * CLK
4 * CLK
4 * CLK
2 * CLK
2 * CLK
4 * CLK
4 * CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
0
0
0
1
CLK ÷ 2
2 * CLK
CLK
0
0
1
0
2 * CLK
2 * CLK
CLK ÷ 2
CLK ÷ 2
CLK
0
0
1
1
0
1
0
0
CLK
0
1
0
1
CLK ÷ 2
2 * CLK
CLK
0
1
1
0
0
1
1
1
CLK
1
0
0
0
CLK
CLK
1
0
0
1
CLK
CLK
CLK ÷ 2
2 * CLK
CLK
1
0
1
0
2 * CLK
2 * CLK
CLK
2 * CLK
2 * CLK
CLK ÷ 2
CLK ÷ 2
CLK
1
0
1
1
1
1
0
0
CLK
1
1
0
1
CLK
CLK ÷ 2
2 * CLK
CLK
1
1
1
0
2 * CLK
2 * CLK
1
1
1
1
CLK
NOTE:
1. Output frequency relationship with respect to input reference frequency CLK. QC1 is connected to FBIN.
DCELECTRICALCHARACTERISTICS
TA = -40°C to +85°C, VCC = 3.3V ± 5%
Symbol
VIH
Parameter
Input HIGH Voltage
InputLOWVoltage
Test Conditions
LVCMOS Inputs
Min.
2
Typ.
Max
VCC + 0.3
0.8
Unit
—
—
V
V
VIL
LVCMOS Inputs
PECL_CLK
PECL_CLK
IOH = -24mA
IOL = 24mA
—
250
1
VPP
Peak-to-PeakInputVoltage
CommonMode(1)
Output HIGH Voltage(2)
OutputLOWVoltage(2)
—
—
mV
V
VCMR
VOH
VOL
—
VCC - 0.6
—
2.4
—
—
—
—
—
—
—
V
—
0.55
0.3
V
IOL = 12mA
—
ZOUT
IIN
OutputImpedance
14 - 17
—
—
Ω
InputLeakageCurrent
±150
1
μA
mA
mA
ICC
MaximumQuiescentSupplyCurrent
Maximum PLL Supply Current
All VCC Pins
VCCA Only
—
ICCPLL
3
5
NOTES:
1. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP
(DC) specification.
2. The IDT5V9351 outputs can drive series or paralell terminated 50Ω (or 50Ω to VCC/2) transmission lines on the incident edge.
4
IDT5V9351
LOWVOLTAGEPLLCLOCKDRIVER
INDUSTRIALTEMPERATURERANGE
PLLINPUTREFERENCECHARACTERISTICS
VCC = 3.3V ± 5%, TA = -40°C to +85°C
Symbol
Parameter
Min.
—
100
50
Max
1
Unit
tR,tF
TCLK Input Rise/Fall Levels, 0.8V to 2V
ns
÷2feedback
200
100
50
(1)
fREF
ReferenceInputFrequency ÷4feedback
÷8feedback
StaticTestMode
MHz
%
25
0
300
75
fREFDC
ReferenceInputDutyCycle
25
NOTE:
1. Maximum and minimum input reference is limited by the VCO lock range and the feedback divider for the TCLK or PECL_CLK inputs.
ACELECTRICALCHARACTERISTICS(1)
TA = -40°C to +85°C, VCC = 3.3V ± 5%
Symbol
tR,tF
Parameter
Conditions
0.55V to 2.4V
LVPECL
Min.
0.1
500
1.2
45
Typ.
—
Max
1
Unit
ns
OutputRise/FallTime
Peak-to-PeakInputVoltage
CommonModeRange(2)
VPP
—
1000
mV
V
VCMR
LVPECL
—
VCC - 0.9
55
100-200MHz
50-100 MHz
25-50 MHz
50
tPW
Output Duty Cycle
47.5
48.75
—
50
52.5
51.75
150
400
200
100
50
%
50
tSK(O)
fVCO
OutputtoOutputSkew
PLL VCO Lock Range
—
ps
200
100
50
—
MHz
÷2output
÷4output
÷8output
TCLK to FBIN
—
fMAX
tPD
MaximumOutputFrequency
—
MHz
ps
25
—
PropagationDelay(StaticPhaseOffset)
-50
25
—
150
325
10
PECL_CLK to FBIN
—
tPLZ,tPHZ
tPZL,tPZH
OutputDisableTime
OutputEnableTime
—
—
ns
ns
—
—
10
÷2feedback
÷4feedback
÷8feedback
-3dbpointof
PLLtransfer
characteristic
—
9 - 20
3 - 9.5
1.2 - 2.1
10
—
BW
PLLClosedLoopBandwidth
—
—
MHz
ps
—
—
tJ
Cycle-to-CycleJitter÷ 4feedback
(SingleOutputFrequencyConfiguration)
PeriodJitter÷4feedback
RMS Value
—
22
tJIT(PER)
RMS Value
RMS Value
—
8
15
ps
(SingleOutputFrequencyConfiguration)
tJIT (φ)
tLOCK
I/O Phase Jitter
—
—
4 - 17
—
—
1
ps
Maximum PLL Lock Time
ms
NOTES:
1. AC Characteristics apply for parallel output termination of 50Ω to VTT.
2. VCMR(AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the input swing lies within VPP(AC)
specifications.
5
IDT5V9351
LOWVOLTAGEPLLCLOCKDRIVER
INDUSTRIALTEMPERATURERANGE
DCELECTRICALCHARACTERISTICS
TA = -40°C to +85°C, VCC = 2.5V ± 5%
Symbol
VIH
Parameter
Input HIGH Voltage
Test Conditions
LVCMOS Inputs
Min.
1.7
—
250
1
Typ.
—
Max
VCC + 0.3
0.7
Unit
V
VIL
InputLOWVoltage
LVCMOS Inputs
PECL_CLK
PECL_CLK
IOH = -15mA
IOL = 15mA
—
V
VPP
Peak-to-PeakInputVoltage
CommonMode(1)
Output HIGH Voltage(2)
OutputLOWVoltage(2)
InputCurrent
—
—
mV
V
VCMR
VOH
VOL
IIN
—
VCC - 0.6
—
1.8
—
—
—
—
—
—
—
—
V
—
0.6
V
—
±150
—
μA
pF
Ω
pF
mA
mA
CIN
InputCapacitance
4
ZOUT
CPD
ICC
OutputImpedance
17 - 20
10
—
PowerDissipationCapacitance
MaximumQuiescentSupplyCurrent
Maximum PLL Supply Current
—
All VCC Pins
VCCA Only
—
1
ICCPLL
3
5
NOTES:
1. VCMR is the difference from the most positive side of the differential input signal. Normal operation is obtained when the HIGH input is within the VCMR range and the input swing
lies within the VPP specification.
2. The IDT5V9351 outputs can drive series or paralell terminated 50Ω (or 50Ω to VCC/2) transmission lines on the incident edge.
PLLINPUTREFERENCECHARACTERISTICS
VCC = 2.5V ± 5%, TA = -40°C to +85°C
Symbol
Parameter
Min.
—
100
50
Max
1
Unit
tR,tF
TCLK Input Rise/Fall Levels, 0.7V to 1.7V
ns
÷2feedback
200
100
50
(1)
fREF
ReferenceInputFrequency ÷4feedback
MHz
%
÷8feedback
25
fREFDC
ReferenceInputDutyCycle
25
75
NOTE:
1. Maximum and minimum input reference is limited by the VCO lock range and the feedback divider for the TCLK or PECL_CLK inputs.
6
IDT5V9351
LOWVOLTAGEPLLCLOCKDRIVER
INDUSTRIALTEMPERATURERANGE
ACELECTRICALCHARACTERISTICS(1)
TA = -40°C to +85°C, VCC = 2.5V ± 5%
Symbol
tR,tF
Parameter
Conditions
0.6V to 1.8V
LVPECL
Min.
0.1
500
1.2
45
Typ.
—
Max
1
Unit
ns
OutputRise/FallTime
Peak-to-PeakInputVoltage
CommonModeRange(2)
VPP
—
1000
VCC - 0.6
55
mV
V
VCMR
LVPECL
—
100-200MHz
50-100 MHz
25-50 MHz
50
tPW
Output Duty Cycle
47.5
48.75
—
50
52.5
51.75
150
400
200
100
50
%
50
tSK(O)
fVCO
OutputtoOutputSkew
PLL VCO Lock Range
—
ps
200
100
50
—
MHz
÷2output
÷4output
÷8output
TCLK to FBIN
—
fMAX
MaximumOutputFrequency
Input to FBIN Delay
—
MHz
ps
25
—
tPD
-100
0
—
100
300
12
PECL_CLK to FBIN
—
tPLZ,tPHZ
tPZL,tPZH
OutputDisableTime
OutputEnableTime
—
—
ns
ns
—
—
12
÷2feedback
÷4feedback
÷8feedback
-3dbpointof
PLLtotransfer
characteristic
—
4 - 15
2 - 7
0.7 - 2
10
—
BW
tJ
PLLClosedLoopBandwidth
—
—
MHz
ps
—
—
Cycle-to-CycleJitter÷4feedback
(SingleOutputFrequencyConfiguration)
PeriodJitter÷4feedback
RMS Value
—
22
tJIT(PER)
RMS Value
RMS Value
—
8
15
ps
(SingleOutputFrequencyConfiguration)
tJIT (φ)
I/O Phase Jitter
—
—
6 - 25
—
—
1
ps
tLOCK
Maximum PLL Lock Time
ms
NOTES:
1. AC Characteristics apply for parallel output termination of 50Ω to VTT.
2. VCMR(AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the input swing lies within VPP(AC)
specifications.
7
IDT5V9351
LOWVOLTAGEPLLCLOCKDRIVER
INDUSTRIALTEMPERATURERANGE
TESTCIRCUITSANDWAVEFORMS
IDT5V9351 D.U.T.
ZO = 50Ω
ZO = 50Ω
Pulse
Generator
Z = 50Ω
RT = 50Ω
RT = 50Ω
VTT
VTT
TCLK AC Test Reference for VCC = 2.5V and VCC = 3.3V
IDT5V9351 D.U.T.
ZO = 50Ω
ZO = 50Ω
Pulse
Generator
Z = 50Ω
RT = 50Ω
RT = 50Ω
VTT
VTT
PECL_CLK AC Test Reference
VCC
2V
2V
VCC/2
0.8V
0V
0.8V
Input
VCC/2
1ns
1ns
tCLK
VCC/2
FBIN
Input Characteristics for 3.3V
tPD
VCC
1.7V
1.7V
PECL_CLK
PECL_CLK
VCC/2
0.7V
0V
0.7V
Input
1ns
1ns
Prop Delay
Input Characteristics for 2.5V
VOH
2.4V
VOH
1.8V
2.4V
1.8V
VCC/2
VCC/2
0.55V
VOL
0.6V
VOL
0.55V
tR
0.6V
tR
Output
Output
tF
tF
Output Test Conditions for VCC = 2.5V ± 5%
Output Test Conditions for VCC = 3.3V ± 5%
8
IDT5V9351
LOWVOLTAGEPLLCLOCKDRIVER
INDUSTRIALTEMPERATURERANGE
CCLK
FBIN
TJ(0) = T0 - T1 MEAN
I/O Jitter
VCC
VCC/2
GND
tP
T0
tPW = tP/T0 x 100%
Output Duty Cycle
TJ = Tn - Tn+1
Tn+1
Cycle-to-Cycle Jitter
Tn
TJ(PER) = Tn - 1/f0
T0
Period Jitter
9
IDT5V9351
LOWVOLTAGEPLLCLOCKDRIVER
INDUSTRIALTEMPERATURERANGE
ORDERINGINFORMATION
IDT XXXXX
XX
X
Device Type Package
Process
-40°C to +85°C (Industriall)
I
Thin Quad Flat Pack
TQFP - Green
PF
PFG
5V9351
Low Voltage PLL Clock Driver
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
800-345-7015 or 408-284-8200
fax: 408-284-2775
www.idt.com
for Tech Support:
clockhelp@idt.com
10
相关型号：
5V9352PFGI8
PLL Based Clock Driver, 5V Series, 11 True Output(s), 0 Inverted Output(s), PQFP32, GREEN, TQFP-32
IDT
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