650R-07ILFT [IDT]
NETWORKING CLOCK SOURCE;
| 型号： | 650R-07ILFT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | NETWORKING CLOCK SOURCE |
| 文件： | 总9页 (文件大小：215K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
NETWORKING CLOCK SOURCE
ICS650-07C
Description
Features
The ICS650-07C is a low cost, low jitter, high performance
clock synthesizer for networking applications. Using analog
Phase-Locked Loop (PLL) techniques, the device accepts a
12.5 MHz or 25.00 MHz clock or fundamental mode crystal
input to produce multiple output clocks for networking chips,
PCI devices, SDRAM, and ASICs. The ICS650-07C outputs
all have 0 ppm synthesis error.
• Packaged in 20-pin tiny SSOP (QSOP)
• Pb (lead) free package
• 12.5 MHz or 25.00 MHz fundamental crystal or clock
input
• Six output clocks with selectable frequencies
• SDRAM frequencies of 67, 83, 100, and 133 MHz
• Buffered crystal reference output
See the MK74CB214, ICS551, and ICS552-01 for non-PLL
buffer devices which produce multiple low-skew copies of
these output clocks.
• Zero ppm synthesis error in all clocks
• Ideal for PMC-Sierra’s ATM switch chips
See the ICS570, ICS9112-16/17/18 for zero delay buffers
that can synchronize outputs and other needed clocks.
• Full CMOS output swing with 25 mA output drive
capability at TTL levels
• Advanced, low power, sub-micron CMOS process
• 3.0 V to 5.5 V operating voltage
Block Diagram
VDD
2
CLKA1
CLKA2
CLKB1
/2
/2
2
ACS1, 0
Clock
2
Synthesis
and Control
Circuitry
BCS1, 0
CLKB2
CCS
CLKC1
CLKC2
12.5 MHz or 25.00 MHz
Crystal or Clock
Clock
Buffer/
Crystal
Oscillator
X1/ICLK
REFOUT
X2
2
Optional crystal capacitors are shown and
may be required for tuning of initial accuracy
OE (all outputs)
GND
IDT™ / ICS™ NETWORKING CLOCK SOURCE
1
ICS650-07C
REV D 102709
ICS650-07C
NETWORKING CLOCK SOURCE
CLOCK SYNTHESIZER
Pin Assignment
1
2
20
19
18
17
16
15
14
13
12
11
BCS1
BCS0
REFOUT
CLKA1
VDD
ACS0
X2
3
X1/ICLK
VDD
4
ACS1
GND
5
6
OE
CLKC1
7
GND
CLKC2
CLKB2
CLKB1
8
CLKA2
DC
9
10
CCS
20 pin (150 mil) SSOP
Pin Descriptions
Pin
1
Name
ACS0
X2
Pin Type
Description
Tri-level Input A clock select 0. Selects outputs on CLKA1 and CLKA2. See table below.
2
XO
XI
Crystal connection. Connect to a crystal or leave unconnected for clock input.
Crystal connection. Connect to fundamental crystal or clock input.
Connect to 3.3 V or 5 V. Must be same value as other VDD.
3
X1/ICLK
VDD
4
Power
Input
5
ACS1
A clock select 1. Selects outputs on CLKA1 and CLKA2. Internal pull-up
resistor. See table below.
6
GND
CLKC1
CLKC2
CLKB2
CLKB1
CCS
Power
Output
Output
Output
Output
Connect to ground.
7
Clock C output 1. Depends on setting of CCS per table below.
Clock C output 2. Depends on setting of CCS per table below. Same as CLKC1.
Clock B output 2. Depends on setting of BCS1, 0 per table below.
Clock B output 1. Depends on setting of BCS1, 0 per table below.
8
9
10
11
12
13
14
15
16
17
18
19
20
Tri-level Input Clock C Select pin. Selects outputs on CLKC1 and CLKC2 per table below.
DC
—
Don’t Connect. Do not connect anything to this pin.
CLKA2
GND
Output
Power
Input
Clock A output 2. Depends on setting of ACS1, 0 per table below.
Connect to ground.
OE
Output enable. Tri-states all outputs when low. Internal pull-up resistor.
Connect to VDD. Must be same value as other VDD.
Clock A output 1. Depends on setting of ACS1, 0 per table below.
Buffered reference clock output. Same frequency as crystal or clock input.
VDD
Power
Output
Output
CLKA1
REFOUT
BCS0
BCS1
Tri-level Input B clock select 0. Selects outputs on CLKB1 and CLKB2. See table below.
Input B clock select 1. Selects outputs on CLKB1 and CLKB2. See table below.
IDT™ / ICS™ NETWORKING CLOCK SOURCE
2
ICS650-07C
REV D 102709
ICS650-07C
NETWORKING CLOCK SOURCE
CLOCK SYNTHESIZER
For a 25 MHz Fundamental Crystal or Clock Input, use the following tables:
A Clocks Select Table (MHz) B Clocks Select Table (MHz)
ACS1
ACS0
CLKA1
100
CLKA2
OFF (low)
TEST
BCS1
BCS0
CLKB1
TEST
CLKB2
TEST
0
0
0
1
1
1
0
M
1
0
0
0
1
1
1
0
M
1
TEST
75
66.6667
100
33.3333
50
OFF (low)
16.6667
TEST
0
33.3333
TEST
66.6667
0
83.3333
TEST
41.6667
TEST
M
1
M
1
33.3333
133.3333
66.6667
REFOUT = 25 MHz
C Clocks Select Table (MHz)
CCS
0
CLKC1
125
CLKC2
125
M
TEST
75
TEST
75
1
0 = connect directly to ground
1 = connect directly to VDD
M = leave unconnected (automatically self biases to VDD/2)
IDT™ / ICS™ NETWORKING CLOCK SOURCE
3
ICS650-07C
REV D 102709
ICS650-07C
NETWORKING CLOCK SOURCE
CLOCK SYNTHESIZER
For a 12.5 MHz Crystal or Clock Input, use the following tables:
A Clocks Select Table (MHz)
B Clocks Select Table (MHz)
ACS1
ACS0
CLKA1
50
CLKA2
OFF (low)
TEST
BCS1
BCS0
CLKB1
TEST
CLKB2
TEST
0
0
0
1
1
1
0
M
1
0
0
0
1
1
1
0
M
1
TEST
37.5
33.3333
50
16.6667
25
OFF (low)
8.3333
0
16.6667
TEST
33.3333
0
41.66667
TEST
20.8333
TEST
M
1
TEST
M
1
16.6667
66.6667
33.3333
REFOUT = 12.5 MHz
C Clocks Select Table (MHz)
CCS
0
CLKC1
62.5
CLKC2
62.5
M
TEST
37.5
TEST
37.5
1
0 = connect directly to ground
1 = connect directly to VDD
M = leave unconnected (automatically self biases to VDD/2)
IDT™ / ICS™ NETWORKING CLOCK SOURCE
4
ICS650-07C
REV D 102709
ICS650-07C
NETWORKING CLOCK SOURCE
CLOCK SYNTHESIZER
impedance) place a 33Ωresistor in series with the clock line,
as close to the clock output pin as possible. The nominal
impedance of the clock output is 20Ω.
External Components
The ICS650-07C requires a minimum number of external
components for proper operation.
Crystal Information
Decoupling Capacitor
The crystal used should be a fundamental mode (do not use
third overtone), parallel resonant. Crystal capacitors should
be connected from pins X1 to ground and X2 to ground to
optimize the initial accuracy. The value of these capacitors
is given by the following equation:
Decoupling capacitors of 0.01µF must be connected
between each VDD and GND (pins 4 and 6, pins 16 and 14),
as close to the device as possible. For optimum device
performance, the decoupling capacitor should be mounted
on the component side of the PCB. Avoid the use of vias in
the decoupling circuit.
Crystal caps (pF) = (C - 6) x 2
L
In the equation, C is the crystal load capacitance. So, for a
L
Series Termination Resistor
crystal with a 16 pF load capacitance, two 20 pF capacitors
should be used. If a clock input is used, drive it into X1 and
leave X2 unconnected.
When the PCB trace between the clock outputs and the
loads are over 1 inch, series termination should be used. To
series terminate a 50Ω trace (a commonly used trace
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS650-07C. These ratings, which are
standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these
or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical
parameters are guaranteed only over the recommended operating temperature range.
Item
Rating
Supply Voltage, VDD
All Inputs and Outputs
7 V
-0.5 V to VDD+0.5 V
0 to +70° C
-40 to +85° C
-65 to +150° C
125°C
Ambient Operating Temperature (commercial)
Ambient Operating Temperature (industrial)
Storage Temperature
Junction Temperature
Soldering Temperature (20 seconds max)
260°C
Recommended Operation Conditions
Parameter
Min.
0
Typ.
Max.
+70
Units
° C
Ambient Operating Temperature (commercial)
Ambient Operating Temperature (industrial)
Power Supply Voltage (measured with respect to GND)
-40
+3.0
+85
° C
+3.3
+5.5
V
IDT™ / ICS™ NETWORKING CLOCK SOURCE
5
ICS650-07C
REV D 102709
ICS650-07C
NETWORKING CLOCK SOURCE
CLOCK SYNTHESIZER
DC Electrical Characteristics
Unless stated otherwise, VDD = 5 V
Parameter
Operating Voltage
Supply Current
Symbol
VDD
Conditions
Min.
Typ.
Max.
Units
3.0
5.5
V
mA
V
IDD
No load
60
Input High Voltage
Input Low Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
V
X1 pin only, Clock input
X1 pin only, Clock input
All tri-level inputs
VDD/2+1 VDD/2
IH
V
VDD/2 VDD/2-1
V
IL
V
VDD-0.5
2
V
IH
V
All tri-level inputs
0.5
V
IL
V
Other inputs, except
tri-level
V
IH
Input Low Voltage
V
Other inputs, except
tri-level
0.8
V
IL
Output High Voltage
Output High Voltage
Output Low Voltage
Short Circuit Current
Internal Pull-up Resistor
V
V
I
I
I
= -25 mA
= -8 mA
= 25 mA
2.4
V
V
OH
OH
OH
OL
VDD-0.4
OH
V
0.4
V
OL
I
Each output
100
200
mA
kΩ
OS
ACS1, BCS1, OE
AC Electrical Characteristics
Unless stated otherwise, VDD = 5 V
Parameter
Symbol
Conditions
Min.
Typ.
Max. Units
Input Frequency
10
12.5 or 25
27
0
MHz
ppm
ns
Frequency Error
All clocks
Output Rise Time
t
0.8 to 2.0 V
2.0 to 0.8 V
At VDD/2
1.5
1.5
60
OR
Output Fall Time
t
ns
OF
Output Clock Duty Cycle
Absolute Jitter, short term
40
50
%
Variation from mean
150
ps
IDT™ / ICS™ NETWORKING CLOCK SOURCE
6
ICS650-07C
REV D 102709
ICS650-07C
NETWORKING CLOCK SOURCE
CLOCK SYNTHESIZER
Thermal Characteristics
Parameter
Symbol
Conditions
Min.
Typ. Max. Units
Thermal Resistance Junction to
Ambient
θ
Still air
135
93
° C/W
° C/W
° C/W
° C/W
JA
θ
1 m/s air flow
3 m/s air flow
JA
θ
78
JA
Thermal Resistance Junction to Case
θ
60
JC
Marking Diagram—ICS650R-07LF
Marking Diagram—ICS650R-07ILF
20
11
20
11
650R-07LF
######
YYWW
650R-07ILF
######
YYWW
10
1
10
1
Notes:
1. ###### is the lot code.
2. YYWW is the last two digits of the year, and the week number that the part was assembled.
3. “LF” denotes Pb (lead) free package.
4. “I” denotes industrial grade device.
5. Bottom marking: (origin) = country of origin if not USA.
IDT™ / ICS™ NETWORKING CLOCK SOURCE
7
ICS650-07C
REV D 102709
ICS650-07C
NETWORKING CLOCK SOURCE
CLOCK SYNTHESIZER
Package Outline and Package Dimensions (20-pin SSOP, 150 Mil. Body)
Package dimensions are kept current with JEDEC Publication No. 95
20
Millimeters
Inches*
Symbol
Min
1.35
0.10
--
Max
1.75
0.25
1.50
0.30
0.25
8.75
6.20
4.00
Min
Max
A
A1
A2
b
c
D
0.053
0.004
--
0.069
0.010
0.059
0.012
0.010
0.344
0.244
0.157
E1
E
INDEX
AREA
0.20
0.18
8.55
5.80
3.80
0.008
0.007
0.337
0.228
0.150
1 2
E
E1
e
D
.635 Basic
.025 Basic
L
0.40
1.27
0.016
0.050
α
0°
8°
0°
8°
*For reference only. Controlling dimensions in mm.
A
2
A
A
1
c
- C -
e
SEATING
PLANE
b
L
.10 (.004)
C
Ordering Information
Part / Order Number
650R-07LF
Marking
see page 7
Shipping Packaging
Tubes
Package
Temperature
0 to +70° C
0 to +70° C
-40 to +85° C
-40 to +85° C
20-pin SSOP
20-pin SSOP
20-pin SSOP
20-pin SSOP
650R-07LFT
Tape and Reel
Tubes
650R-07ILF
650R-07ILFT
Tape and Reel
Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility
for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses
are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range,
high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to
change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical
instruments.
IDT™ / ICS™ NETWORKING CLOCK SOURCE
8
ICS650-07C
REV D 102709
ICS650-07C
NETWORKING CLOCK SOURCE
CLOCK SYNTHESIZER
Innovate with IDT and accelerate your future networks. Contact:
www.IDT.com
For Sales
800-345-7015
408-284-8200
Fax: 408-284-2775
For Tech Support
www.idt.com/go/clockhelp
Corporate Headquarters
Integrated Device Technology, Inc.
www.idt.com
© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device
Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered
trademarks used to identify products or services of their respective owners.
Printed in USA
相关型号：
©2020 ICPDF网 联系我们和版权申明