7005L17J_技术文档

HIGH-SPEED

IDT7005S/L

8K x 8 DUAL-PORT

STATIC RAM

◆

M/S = H for BUSY output flag on Master,

M/S = L for BUSY input on Slave

Interrupt Flag

On-chip port arbitration logic

Full on-chip hardware support of semaphore signaling

between ports

Fully asynchronous operation from either port

Devices are capable of withstanding greater than 2001V

electrostatic discharge

Battery backup operation—2V data retention

TTL-compatible, single 5V (±10%) power supply

Available in 68-pin PGA, quad flatpack, PLCC, and a 64-pin

thin quad flatpack

Industrial temperature range (-40°C to +85°C) is available

for selected speeds

Green parts available, see ordering information

Features

◆

True Dual-Ported memory cells which allow simultaneous

◆

reads of the same memory location

High-speed access

◆

– Military:20/25/35/55/70ns(max.)

– Industrial: 35/55ns(max.)

◆

– Commercial:15/17/20/25/35/55ns(max.)

Low-power operation

◆

– IDT7005S

◆

Active:750mW(typ.)

Standby: 5mW (typ.)

– IDT7005L

Active:700mW(typ.)

Standby: 1mW (typ.)

IDT7005 easily expands data bus width to 16 bits or more

◆

using the Master/Slave select when cascading more than

one device

FunctionalBlockDiagram

OE

R

OE

CE

L

CER

R/W

L

R/WR

I/O0L- I/O7L

I/O0R-I/O7R

I/O

Control

BUSY ^(1,2)

L

(1,2)

BUSY

R

A

12R

0R

A

12L

Address

Decoder

MEMORY

ARRAY

Address

Decoder

A

0L

A

13

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

CE

OE

R/W

L

CE

OE

R/W

R

L

R

L

SEM

R

SEM

INTL

L

M/S

(2)

INTR

2738 drw 01

NOTES:

1. (MASTER): BUSY is output; (SLAVE): BUSY is input.

2. BUSY outputs and INT outputs are non-tri-stated push-pull.

SEPTEMBER 2012

1

DSC 2738/17

IDT7005S/L

High-Speed 8K x 8 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

Description

The IDT7005 is a high-speed 8K x 8 Dual-Port Static RAM. The

IDT7005isdesignedtobeusedasastand-alone64K-bitDual-PortRAM

orasacombinationMASTER/SLAVEDual-PortRAMfor16-bit-or-more

wordsystems.UsingtheIDTMASTER/SLAVEDual-PortRAMapproach

in16-bitorwidermemorysystemapplicationsresultsinfull-speed,error-

freeoperationwithouttheneedforadditionaldiscretelogic.

This device provides two independent ports with separate control,

address,andI/Opinsthatpermitindependent,asynchronousaccessfor

reads or writes to any location in memory. An automatic power down

featurecontrolledbyCEpermitstheon-chipcircuitryofeachporttoenter

a very low standby power mode.

Fabricated using CMOS high-performance technology, these de-

vicestypicallyoperateononly750mWofpower.Low-power(L)versions

offerbatterybackupdataretentioncapabilitywithtypicalpowerconsump-

tionof500µWfroma2Vbattery.

The IDT7005 is packaged in a ceramic 68-pin PGA, 68-pin quad

flatpack,68-pinPLCCanda64-pinthinquadflatpack,(TQFP).Military

gradeproductismanufacturedincompliancewiththelatestrevisionofMIL-

PRF-38535QMLmakingitideallysuitedtomilitarytemperatureapplica-

tionsdemandingthehighestlevelofperformanceandreliability.

PinConfigurations^(1,2,3)

11/16/01

INDEX

9

8

7

6

5

4

3

2

1

68 67 66 65 64 63 62 61

60

I/O2L

I/O3L

I/O4L

I/O5L

GND

I/O6L

I/O7L

A

5L

4L

3L

2L

1L

0L

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

59

58

57

56

55

IDT7005J or F

J68-1⁽⁴⁾

54

53

52

51

50

49

48

47

46

45

44

INT

BUSY

GND

M/S

BUSY

L

F68-1⁽⁴⁾

V

CC

L

GND

I/O0R

I/O1R

I/O2R

68 Pin PLCC / FLATPACK

Top View⁽⁵⁾

,

R

INT

R

V

CC

A0R

A1R

A2R

A3R

A4R

I/O3R

I/O4R

I/O5R

I/O6R

27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

2738 drw 02

11/16/01

INDEX

1

2

3

4

5

6

48

47

46

A

4L

3L

2L

1L

0L

I/O2L

I/O3L

I/O4L

I/O5L

GND

I/O6L

I/O7L

45

44

43

42

41

40

39

38

37

INT

L

7005PF

PN-64⁽⁴⁾

7

8

BUSY

L

GND

M/S

VCC

64-Pin TQFP

Top View⁽⁵⁾

9

GND

I/O0R

I/O1R

I/O2R

.

10

11

12

BUSY

R

INT

R

NOTES:

A

0R

1. All VCC pins must be connected to power supply.

2. All GND pins must be connected to ground supply.

VCC

13

14

15

1R

2R

3R

4R

36

35

34

33

I/O3R

I/O4R

I/O5R

3. J68-1 package body is approximately .95 in x .95 in x .12 in.

F68-1 package body is approximately .97 in x .97 in x .08 in.

PN64 package body is approximately 14mm x 14mm x 1.4mm.

4. This package code is used to reference the package diagram.

5. This text does not indicate oriention of the actual part-marking

16

2738 drw 03

6.42

2

IDT7005S/L

High-Speed 8K x 8 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

Pin Configurations^(1,2,3)(con't.)

11/19/01

51

A

50

48

A

46

A

44

BUSY

42

M/S

40

INT

38

36

11

10

09

08

07

5L

A4L

2L

0L

A1R

A3R

L

R

53

A

52

49

47

A

45

INT

43

GND

41

BUSYR

39

37

35

34

L

A4R

7L

A3L

1L

A

0R

A2R

A

5R

6R

8R

A

6L

55

A

54

32

33

A

A7R

9L

A

8L

57

A

56

A10L

30

31

A

A9R

11L

59

58

A

28

29

A10R

12L

A

11R

IDT7005G

(4)

V

CC

G68-1

61

N/C

60

N/C

26

GND

27

68-Pin PGA

Top View

06

05

A

12R

(5)

63

SEM

62

24

N/C

25

N/C

L

CE

L

65

64

22

SEM

23

04

03

02

R

CE

21

R

OE

L

R/W

L

67

I/O0L

66

20

OE

R/W

R

N/C

1

I/O2L

3

5

7

9

GND

68

I/O1L

11

I/O1R

13

V

15

18

I/O7R

19

N/C

CC I/O4R

I/O4L GND I/O7L

,

2

4

I/O5L

6

8

V

10

12

14

16

17

01

I/O3L

I/O6L

CC

I/O0R I/O2R I/O3R I/O5R I/O6R

A

B

C

D

E

F

G

H

J

K

L

INDEX

2738 drw 04

NOTES:

1. All VCC pins must be connected to power supply.

2. All GND pins must be connected to ground supply.

3. Package body is approximately 1.18in x 1.18in x .16in.

4. This package code is used to reference the package diagram.

5. This text does not indicate oriention of the actual part-marking

PinNames

Left Port

Right Port

Names

Chip Enable

CE

R/W

OE

L

CE

R/W

OE

R

L

R

Read/Write Enable

Output Enable

Address

L

R

A0L - A12L

A

0R - A12R

I/O0R - I/O7R

SEM

INT

BUSY

M/S

I/O^0L- I/O7L

SEM

INT

BUSY

Data Input/Output

Semaphore Enable

Interrupt Flag

Busy Flag

L

R

L

R

L

R

Master or Slave Select

Power

V

CC

GND

Ground

2738 tbl 01

6.42

3

IDT7005S/L

High-Speed 8K x 8 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

Truth Table I: Non-Contention Read/Write Control

Inputs⁽¹⁾

R/W

Outputs

I/O0-7

Mode

CE

H

L

OE

X

SEM

H

X

L

High-Z

DATAIN

Deselected: Power-Down

Write to Memory

X

H

L

H

X

L

H

DATAOUT Read Memory

High-Z Outputs Disabled

X

H

X

2738 tbl 02

NOTE:

1. A0L – A12L is not equal to A0R – A12R

Truth Table II: Semaphore Read/Write Control⁽¹⁾

Inputs⁽¹⁾

R/W

Outputs

I/O0-7

Mode

CE

H

OE

L

SEM

H

↑

X

L

DATAOUT Read in Semaphore Flag Data Out

H

X

DATA^IN

Write I/Oo into Semaphore Flag

Not Allowed

____

L

X

2738 tbl 03

NOTE:

1. There are eight semaphore flags written to via I/O0 and read from I/O0 - I/O7. These eight semaphores are addressed by A0 - A2.

AbsoluteMaximumRatings⁽¹⁾

MaximumOperatingTemperature

andSupplyVoltage^(1,2)

Commercial

Symbol

Rating

& Industrial

Military

Unit

Ambient

(2)

Grade

Temperature

-55^OC to+125^OC

0^OC to +70^OC

-40^OC to +85^OC

GND

0V

Vcc

VTE RM

Terminal Voltage

with Respect to

GND

-0.5 to +7.0

V

Military

5.0V

+

10%

Temperature Under

Bias

-55 to +125

-65 to +150

50

-65 to +135

-65 to +150

50

^oC

Commercial

Industrial

0V

5.0V

10%

T

BIAS

OV

Storage

Temperature

TSTG

2738 tbl 05

NOTES:

1. This is the parameter TA. This is the "instant on" case temperature.

IOUT

mA

DC Output Current

2

Industrial temperature: for specific speeds, packages and powers contact

your sales office.

2738 tbl 04

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS

may cause permanent damage to the device. This is a stress rating only and

functional operation of the device at these or any other conditions above

those indicated in the operational sections of this specification is not implied.

Exposure to absolute maximum rating conditions for extended periods may

affect reliability.

RecommendedDCOperating

Conditions

Symbol

Parameter

Min.

Typ.

Max.

5.5

0

Unit

V

2. VTERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10%

maximum, and is limited to < 20mA for the period of VTERM > Vcc + 10%.

V

CC

Supply Voltage

4.5

5.0

GND

Ground

0

V

Capacitance⁽¹⁾(TA = +25°C, f = 1.0MHz)

6.0⁽²⁾

0.8

V

____

V

IH

IL

Input High Voltage

Input Low Voltage

2.2

Symbol

Parameter

Input Capacitance

Output Capacitance

Conditions⁽²⁾

IN = 3dV

OUT = 3dV

Max.

Unit

V

-0.5⁽¹⁾

V

____

2738 tbl 06

C

IN

V

9

pF

NOTES:

1. VIL > -1.5V for pulse width less than 10ns.

2. VTERM must not exceed Vcc + 10%.

COUT

V

10

pF

2738 tbl 07

NOTES:

1. These parameters are determined by device characterization but are not

production tested (TQFP Package only).

2. 3dV references the interpolated capacitance when the input and output signals

switch from 0V to 3V or from 3V to 0V.

6.42

4

IDT7005S/L

High-Speed 8K x 8 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

DC Electrical Characteristics Over the 0perating

Temperature and Supply Voltage Range (VCC = 5.0V ± 10%)

7005S

7005L

Symbol

|I^LI

|I^LO

Parameter

Input Leakage Current⁽¹⁾

Output Leakage Current

Output Low Voltage

Test Conditions

Min.

Max.

10

Min.

Max.

Unit

µA

V

___

|

V

CC = 5.5V, VIN = 0V to VCC

5

___

|

10

CE = V^IH, VOUT = 0V to VCC

OL = +4mA

OH = -4mA

V

OL

OH

I

0.4

___

V

Output High Voltage

I

2.4

V

2738 tbl 08

NOTE:

1. At Vcc < 2.0V input leakages are undefined.

Data Retention Characteristics Over All Temperature Ranges

(L Version Only) (VLC = 0.2V, VHC = VCC - 0.2V)

Symbol

Parameter

Test Condition

Min.

Typ.⁽¹⁾

Max.

Unit

V

___

V

DR

V

CC for Data Retention

VCC = 2V

2.0

___

ICCDR

Data Retention Current

Mil. & Ind.

Com'l.

100

4000

µA

CE > VHC

IN > VHC or < VLC

___

V

100

1500

(3)

___

t

CDR

Chip Deselect to Data Retention Time

Operation Recovery Time

0

ns

SEM > VHC

(3)

(2)

___

tR

t

RC

ns

2738 tbl 09

NOTES:

1. TA = +25°C, VCC = 2V, and are not production tested.

2. tRC = Read Cycle Time

3. This parameter is guaranteed by characterization, but is not production tested.

Data Retention Waveform

DATA RETENTION MODE

VDR >

4.5V

VCC

2V

tCDR

tR

VDR

CE

VIH

2738 drw 05

6.42

5

IDT7005S/L

High-Speed 8K x 8 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range⁽¹⁾(VCC = 5.0V ± 10%)

7005X15

7005X17

7005X20

Com'l, Ind

& Military

7005X25

Com'l &

Military

Com'l Only

Symbol

Parameter

Test Condition

Version

COM'L

Typ.⁽²⁾

Max.

Typ.⁽²⁾

Max.

Typ.⁽²⁾

Max.

Typ.⁽²⁾

Max.

Unit

ICC

Dynamic Operating Current

(Both Ports Active)

S

L

170

160

310

260

170

160

310

260

160

150

290

240

155

145

265

220

mA

CE = VIL, Outputs Disabled

SEM = VIH

(3)

f = fMAX

____

MIL &

IND

S

L

160

150

370

320

155

145

340

280

I

SB1

Standby Current

(Both Ports - TTL

Level Inputs)

COM'L

S

L

20

10

60

20

10

60

50

20

10

60

50

16

10

60

50

mA

CE

SEM

f = fMAX

L

= CE

R

= VIH

R

= SEM

L

(3)

____

MIL &

IND

S

L

20

10

90

70

16

10

80

65

(5)

ISB2

Standby Current

(One Port - TTL

Level Inputs)

COM'L

S

L

105

95

190

160

105

95

190

160

95

85

180

150

90

80

170

140

CE^"A"= VIL and CE"B" = VIH

Active Port Outputs Disabled

(3)

f=fMAX

____

MIL &

IND

S

L

95

85

240

210

90

80

215

180

SEM

R

= SEM

L

= VIH

I

SB3

Full Standby Current (Both

Ports - All CMOS Level

Inputs)

Both Ports CE

L

and

COM'L

S

L

1.0

0.2

15

5

1.0

0.2

15

5

1.0

0.2

15

5

1.0

0.2

15

5

mA

CE

R

> VCC - 0.2V

V

IN > VCC - 0.2V or

IN < 0.2V, f = 0⁽⁴⁾

____

MIL &

IND

S

L

1.0

0.2

30

10

1.0

0.2

30

10

SEMR = SEML > VCC - 0.2V

ISB4

Full Standby Current

(One Port - All

CMOS Level Inputs)

COM'L

S

L

100

90

170

140

100

90

170

140

90

80

155

130

85

75

145

120

CE^"A"< 0.2V and

CE^"B"> VCC - 0.2V⁽⁵⁾

SEMR = SEML > VCC - 0.2V

____

MIL &

IND

S

L

90

80

225

200

85

75

200

170

V

IN > VCC - 0.2V or VIN < 0.2V

Active Port Outputs Disabled

(3)

f = fMAX

2738 tbl 10

7005X35

Com'l, Ind

& Military

7005X55

Com'l, Ind

& Military

7005X70

Military

Only

Symbol

Parameter

Test Condition

Version

Typ.⁽²⁾

Max.

Typ.⁽²⁾

Max.

Typ.^{(2 )}

Max.

Unit

____

ICC

Dynamic Operating

Current

(Both Ports Active)

COM'L

S

L

150

140

250

210

150

140

250

210

mA

CE = VIL, Outputs Disabled

SEM = VIH

(3)

f = fMAX

MIL &

IND

S

L

150

140

300

250

150

140

300

250

140

130

300

250

____

I

SB1

Standby Current

(Both Ports - TTL

Level Inputs)

COM'L

S

L

13

10

60

50

13

10

60

50

mA

CE

SEM

f = fMAX

L

= CE

R

= VIH

R

= SEM

L

(3)

MIL &

IND

S

L

13

10

80

65

13

10

80

65

10

8

80

65

(5)

____

ISB2

Standby Current

(One Port - TTL

Level Inputs)

COM'L

S

L

85

75

155

130

85

75

155

130

CE^"A"= VIL and CE"B" = VIH

Active Port Outputs Disabled

(3)

f=fMAX

85

75

MIL &

IND

S

L

190

160

85

75

190

160

80

70

190

160

SEM

R

= SEM

L

= VIH

____

I

SB3

Full Standby Current

(Both Ports - All

Both Ports CE

L

and

COM'L

S

L

1.0

0.2

15

5

1.0

0.2

15

5

mA

CER

> VCC - 0.2V

IN > VCC - 0.2V or

IN < 0.2V, f = 0⁽⁴⁾

= SEM > VCC - 0.2V

CMOS Level Inputs)

V

SEM

MIL &

IND

S

L

1.0

0.2

30

10

1.0

0.2

30

10

1.0

0.2

30

10

R

L

____

ISB4

Full Standby Current

(One Port - All

CMOS Level Inputs)

COM'L

S

L

80

70

135

110

80

70

135

110

CE^"A"< 0.2V and

CE^"B"> VCC - 0.2V⁽⁵⁾

SEMR = SEML > VCC - 0.2V

MIL &

IND

S

L

80

70

175

150

80

70

175

150

75

65

175

150

V

IN > VCC - 0.2V or VIN < 0.2V

Active Port Outputs Disabled

(3)

f = fMAX

2738 tbl 11

NOTES:

1. 'X' in part number indicates power rating (S or L)

2. VCC = 5V, TA = +25°C and are not production tested. ICC DC = 120mA (typ)

3. At f = fMAX, address and I/O'S are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions” of input levels of GND to 3V.

4. f = 0 means no address or control lines change.

5. Port "A" may be either left or right port. Port "B" is the port opposite port "A".

6.42

6

IDT7005S/L

High-Speed 8K x 8 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

5V

AC Test Conditions

Input Pulse Levels

GND to 3.0V

5ns Max.

1.5V

1250Ω

Input Rise/Fall Times

Input Timing Reference Levels

Output Reference Levels

Output Load

DATAOUT

BUSY

INT

DATAOUT

5pF*

775Ω

30pF

775Ω

1.5V

Figures 1 and 2

2738 tbl 12

2738 drw 06

Figure 1. AC Output Test Load

Figure 2. Output Test Load

(For tLZ, tHZ, tWZ, tOW)

*Including scope and jig

AC Electrical Characteristics Over the

OperatingTemperatureandSupplyVoltageRange⁽⁴⁾

7005X15

7005X17

7005X20

Com'l, Ind

& Military

7005X25

Com'l &

Military

Com'l Only

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Unit

READ CYCLE

____

t

RC

AA

ACE

AOE

OH

LZ

HZ

PU

PD

SOP

SAA

Read Cycle Time

15

17

20

25

ns

____

t

Address Access Time

Chip Enable Access Time⁽³⁾

Output Enable Access Time

15

17

20

25

____

t

10

12

13

____

t

Output Hold from Address Change

Output Low-Z Time^(1,2)

3

____

t

3

Output High-Z Time^(1,2)

10

12

15

____

t

Chip Enable to Power Up Time^(2,5)

Chip Disable to Power Down Time^(2,5)

Semaphore Flag Update Pulse (OE or SEM)

Semaphore Address Access Time

0

____

t

15

17

20

25

____

t

10

____

t

15

17

20

25

ns

2738 tbl 13a

7005X35

Com'l, Ind

& Military

7005X55

Com'l, Ind

& Military

IDT7005X70

Military

Only

Symbol

READ CYCLE

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

____

t

RC

AA

ACE

AOE

OH

LZ

HZ

PU

PD

SOP

SAA

Read Cycle Time

35

55

70

ns

____

t

Address Access Time

35

55

70

Chip Enable Access Time⁽³⁾

Output Enable Access Time

Output Hold from Address Change

Output Low-Z Time^(1,2)

____

t

20

30

35

____

t

3

____

t

3

Output High-Z Time^(1,2)

15

25

30

____

t

Chip Enable to Power Up Time^(2,5)

Chip Disable to Power Down Time^(2,5)

0

____

t

35

50

____

t

Semaphore Flag Update Pulse (OE or SEM)

Semaphore Address Access Time

15

____

t

35

55

70

ns

2738 tbl 13b

NOTES:

1. Transition is measured 0mV from Low or High impedance voltage with load (Figures 1 and 2).

2. This parameter is guaranteed but not production tested.

3. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL.

4. 'X' in part number indicates power rating (S or L).

6.42

7

IDT7005S/L

High-Speed 8K x 8 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

Waveform of Read Cycles⁽⁵⁾

t

RC

ADDR

(4)

t

AA

(4)

ACE

CE

OE

(4)

tAOE

R/W

(1)

tOH

t

LZ

VALID DATA⁽⁴⁾

DATAOUT

(2)

HZ

t

BUSYOUT

(3,4)

t

BDD

2738 drw 07

NOTES:

1. Timing depends on which signal is asserted last, OE or CE.

2. Timing depends on which signal is de-asserted first CE or OE.

3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY

has no relation to valid output data.

4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBDD.

5. SEM = VIH.

Timing of Power-Up Power-Down

CE

tPU

tPD

ICC

ISB

,

2738 drw 08

6.42

8

IDT7005S/L

High-Speed 8K x 8 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

AC Electrical Characteristics Over the

OperatingTemperatureandSupplyVoltage⁽⁵⁾

7005X15

7005X17

Com'l Only

7005X20

Com'l, Ind

& Military

7005X25

Com'l &

Military

Com'l Only

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Unit

WRITE CYCLE

____

t

WC

EW

AW

AS

WP

WR

DW

HZ

DH

WZ

OW

SWRD

SPS

Write Cycle Time

15

12

0

17

12

0

20

15

0

25

20

0

ns

t

Chip Enable to End-of-Write⁽³⁾

Address Valid to End-of-Write

Address Set-up Time⁽³⁾

t

Write Pulse Width

12

0

12

0

15

0

20

0

t

Write Recovery Time

t

Data Valid to End-of-Write

Output High-Z Time^(1,2)

10

15

____

t

10

12

15

t

Data Hold Time⁽⁴⁾

0

____

Write Enable to Output in High-Z^(1,2)

Output Active from End-of-Write^(1,2,4)

SEM Flag Write to Read Time

SEM Flag Contention Window

10

12

15

____

t

____

t

0

5

0

5

0

5

0

5

____

t

ns

2738 tbl 14a

7005X35

Com'l, Ind

& Military

7005X55

Com'l, Ind

& Military

7005X70

Military Only

Symbol

WRITE CYCLE

Parameter

Min. Max.

Min.

Max.

Min.

Max.

Unit

____

t

WC

EW

AW

AS

WP

WR

DW

HZ

DH

WZ

OW

SWRD

SPS

Write Cycle Time

35

30

0

55

45

0

70

50

0

ns

t

Chip Enable to End-of-Write⁽³⁾

Address Valid to End-of-Write

Address Set-up Time⁽³⁾

Write Pulse Width

t

25

0

40

0

50

0

t

Write Recovery Time

Data Valid to End-of-Write

Output High-Z Time^(1,2)

Data Hold Time⁽⁴⁾

t

15

30

40

____

t

15

25

30

____

t

0

Write Enable to Output in High-Z^(1,2)

Output Active from End-of-Write^{(1, 2,4)}

SEM Flag Write to Read Time

SEM Flag Contention Window

15

25

30

____

t

____

t

0

5

0

5

0

5

____

t

ns

2738 tbl 14b

NOTES:

1. Transition is measured 0mV from Low or High-impedance voltage with load (Figure 2).

2. This parameter is guaranteed by device characterization but is not production tested.

3. To access RAM, CE = VIL, SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time.

4. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage

and temperature, the actual tDH will always be smaller than the actual tOW.

5. 'X' in part number indicates power rating (S or L).

6.42

9

IDT7005S/L

High-Speed 8K x 8 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

Timing Waveform of Write Cycle No. 1, R/W Controlled Timing^(1,5,8)

tWC

ADDRESS

(7)

HZ

t

OE

tAW

CE or SEM⁽⁹⁾

(3)

WR

(6)

AS

(2)

t

tWP

R/W

DATAOUT

DATAIN

(7)

WZ

t

OW

t

(4)

tDW

tDH

2738 drw 09

Timing Waveform of Write Cycle No. 2, CE Controlled Timing^(1,5)

t

WC

ADDRESS

t

AW

CE or SEM⁽⁹⁾

R/W

(6)

AS

(2)

EW

(3)

tWR

t

DW

tDH

DATAIN

2738 drw 10

NOTES:

1. R/W or CE must be HIGH during all address transitions.

2. A write occurs during the overlap (tEW or tWP) of a LOW CE and a LOW R/W for memory array writing cycle.

3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle.

4. During this period, the I/O pins are in the output state and input signals must not be applied.

5. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.

6. Timing depends on which enable signal is asserted last, CE or R/W.

7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load (Figure

2).

8. If OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be placed

on the bus for the required tDW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified

tWP.

9. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition.

6.42

10

IDT7005S/L

High-Speed 8K x 8 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

Timing Waveform of Semaphore Read after Write Timing, Either Side⁽¹⁾

tSAA

tOH

A0-A2

VALID ADDRESS

tAW

tWR

tACE

tEW

SEM

tDW

tSOP

OUT

VALID

DATA

0

DATAIN VALID

tAS

tWP

tDH

R/W

tSWRD

tAOE

OE

tSOP

Write Cycle

Read Cycle

2738 drw 11

NOTE:

1. CE = VIH for the duration of the above timing (both write and read cycle).

Timing Waveform of Semaphore Write Contention^(1,3,4)

A0"A"-A2"A"

MATCH

(2)

SIDE

“A”

R/W"A"

SEM"A"

tSPS

A0"B"-A2"B"

MATCH

(2)

R/W"B"

SEM"B"

SIDE “B”

2738 drw 12

NOTES:

1. DOR = DOL = VIL, CER = CEL = VIH. Semaphore flag is released from both sides (reads as ones from both sides) at cycle start.

2. All timing is the same for left and right ports. Port “A” may be either left or right port. “B” is the opposite from port “A”.

3. This parameter is measured from R/W^“A”or SEM“A” going HIGH to R/W“B” or SEM“B” going HIGH.

4. If tSPS is not satisfied, the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtain the flag.

6.42

11

IDT7005S/L

High-Speed 8K x 8 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

AC Electrical Characteristics Over the

OperatingTemperatureandSupplyVoltageRange⁽⁶⁾

7005X15

Com'l Only

7005X17

Com'l Only

7005X20

Com'l, Ind

& Military

7005X25

Com'l &

Military

Symbol

BUSY TIMING (M/S=VIH

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max. Unit

)

____

t

BAA

BDA

BAC

BDC

APS

BDD

WH

15

17

20

ns

BUSY Access Time from Address Match

BUSY Disable Time from Address Not Matched

BUSY Access Time from Chip Enable Low

BUSY Access Time from Chip Enable High

Arbitration Priority Set-up Time⁽²⁾

t

15

17

____

t

5

____

BUSY Disable to Valid Data⁽³⁾

t

18

30

t

Write Hold After BUSY⁽⁵⁾

12

13

15

17

____

BUSY TIMING (M/S=VIL

)

____

BUSY Input to Write⁽⁴⁾

Write Hold After BUSY⁽⁵⁾

t

WB

0

ns

tWH

12

13

15

17

PORT-TO-PORT DELAY TIMING

____

t

WDD

Write Pulse to Data Delay⁽¹⁾

30

25

30

25

45

35

50

35

ns

tDDD

Write Data Valid to Read Data Delay⁽¹⁾

ns

2738 tbl 15a

7005X35

Com'l, Ind

& Military

7005X55

Com'l, Ind &

Military

7005X70

Military

Only

Symbol

BUSY TIMING (M/S=VIH

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

)

____

t

BAA

BDA

BAC

BDC

APS

BDD

WH

20

45

40

45

40

ns

BUSY Access Time from Address Match

BUSY Disable Time from Address Not Matched

BUSY Access Time from Chip Enable Low

BUSY Access Time from Chip Enable High

Arbitration Priority Set-up Time⁽²⁾

BUSY Disable to Valid Date⁽³⁾

t

20

35

____

t

5

____

t

35

40

45

t

Write Hold After BUSY⁽⁵⁾

25

____

BUSY TIMING (M/S=VIL

)

____

BUSY Input to Write⁽⁴⁾

Write Hold After BUSY⁽⁵⁾

t

WB

0

ns

tWH

25

PORT-TO-PORT DELAY TIMING

____

t

WDD

Write Pulse to Data Delay⁽¹⁾

60

45

80

65

95

80

ns

tDDD

Write Data Valid to Read Data Delay⁽¹⁾

ns

2738 tbl 15b

NOTES:

1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY".

2. To ensure that the earlier of the two ports wins.

3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual).

4. To ensure that the write cycle is inhibited on port "B" during contention with port "A".

5. To ensure that a write cycle is completed on port "B" after contention on port "A".

6. 'X' in part number indicates power rating (S or L).

6.42

12

IDT7005S/L

High-Speed 8K x 8 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

Timing Waveform of Write with Port-to-Port Read with BUSY^(2,5)

(M/S = VIH)⁽⁴⁾

tWC

MATCH

ADDR"A"

t

WP

R/W"A"

t

DW

t

DH

VALID

DATAIN "A"

(1)

APS

t

MATCH

ADDR"B"

t

BDA

tBDD

BUSY"B"

tWDD

VALID

DATAOUT "B"

(3)

t

DDD

2738 drw 13

NOTES:

1. To ensure that the earlier of the two ports wins. tAPS is ignored for for M/S = VIL (slave).

2. CEL = CER = VIL

3. OE = VIL for the reading port.

4. If M/S = VIL (slave), then BUSY is an input (BUSY"A" =VIH), and BUSY"B" = "don't care", for this example.

5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite port "A".

Timing Waveform of Write with BUSY

t

WP

R/W"A"

(3)

tWB

BUSY"B"

(1)

tWH

(2)

R/W"B"

2738 drw 14

NOTES:

1. tWH must be met for both BUSY input (slave) and output (master).

2. BUSY is asserted on Port "B", blocking R/W^"B", until BUSY"B" goes HIGH

3. tWB is only for the 'Slave' Version..

6.42

13

IDT7005S/L

High-Speed 8K x 8 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

Waveform of BUSY Arbitration Controlled by CE Timing⁽¹⁾(M/S = VIH)

ADDR"A"

ADDRESSES MATCH

and "B"

CE"A"

(2)

tAPS

CE"B"

t

BAC

tBDC

BUSY"B"

2738 drw 15

Waveform of BUSY Arbitration Cycle Controlled by Address Match

Timing⁽¹⁾(M/S = VIH)

ADDR"A"

ADDRESS "N"

(2)

APS

t

ADDR"B"

MATCHING ADDRESS "N"

t

BAA

tBDA

BUSY"B"

2738 drw 16

NOTES:

1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.

2. If tAPS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.

AC Electrical Characteristics Over the

OperatingTemperatureandSupplyVoltageRange⁽¹⁾

7005X15

Com'l Only

7005X17

Com'l Only

7005X20

Com'l, Ind

& Military

7005X25

Com'l &

Military

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Unit

INTERRUPT TIMING

____

t

AS

WR

INS

INR

Address Set-up Time

0

ns

t

Write Recovery Time

Interrupt Set Time

0

____

t

15

20

____

t

Interrupt Reset Time

ns

2738 tbl 16a

7005X35

Com'l, Ind

& Military

7005X55

Com'l, Ind

& Military

7005X70

Military

Only

Symbol

INTERRUPT TIMING

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

____

t

AS

WR

INS

INR

Address Set-up Time

Write Recovery Time

Interrupt Set Time

0

ns

t

0

____

t

25

40

50

____

t

Interrupt Reset Time

ns

2738 tbl 16b

NOTES:

1. 'X' in part number indicates power rating (S or L).

6.42

14

IDT7005S/L

High-Speed 8K x 8 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

Waveform of Interrupt Timing⁽¹⁾

tWC

ADDR"A"

INTERRUPT SET ADDRESS⁽²⁾

(3)

AS

(4)

t

tWR

CE"A"

R/W"A"

INT"B"

(3)

INS

t

2738 drw 17

t

RC

INTERRUPT CLEAR ADDRESS⁽²⁾

ADDR"B"

CE"B"

(3)

AS

t

OE"B"

(3)

INR

t

INT"B"

2738 drw 18

NOTES:

1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.

2. See Interrupt Truth Table III.

3. Timing depends on which enable signal (CE or R/W) asserted last.

4. Timing depends on which enable signal (CE or R/W) is de-asserted first.

Truth Table III — Interrupt Flag^(1,4)

Left Port

Right Port

R/W

L

A

12L-A0L

1FFF

X

R/W

R

A

12R-A0R

Function

Set Right INT Flag

Reset Right INT Flag

Set Left INT Flag

Reset Left INT Flag

CE

L

OE

L

INT

L

CE

R

OE

R

INTR

L

X

L

X

L

X

L

X

L

X

L⁽²⁾

H⁽³⁾

X

R

X

1FFF

1FFE

X

R

X

L⁽³⁾

H⁽²⁾

L

X

L

1FFE

X

L

2738 tbl 17

NOTES:

1. Assumes BUSY^L= BUSYR = VIH.

2. If BUSY^L= VIL, then no change.

3. If BUSY^R= VIL, then no change.

4. INTR and INTL must be initialized at power-up.

6.42

15

IDT7005S/L

High-Speed 8K x 8 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

Truth Table IV — Address BUSY

Arbitration

Inputs

Outputs

A

OL-A12L

(1)

(1 )

A

OR-A12R

Function

Normal

CE

L

CE

R

BUSY

L

BUSYR

X

H

X

L

X

H

L

NO MATCH

MATCH

H

MATCH

H

MATCH

(2)

Write Inhibit⁽³⁾

2738 tbl 18

NOTES:

1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSYX outputs on the IDT7005 are

push-pull, not open drain outputs. On slaves the BUSY^Xinput internally inhibits writes.

2. 'L' if the inputs to the opposite port were stable prior to the address and enable inputs of this port. 'H' if the inputs to the opposite port became stable after the address

and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs can not be LOW simultaneously.

3. Writes to the left port are internally ignored when BUSY^Loutputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored

when BUSY^Routputs are driving LOW regardless of actual logic level on the pin.

Truth Table V — Example of Semaphore Procurement Sequence^(1,2,3)

Functions

D0

- D7

Left

D0

- D7

Right

Status

No Action

1

Semaphore free

Left Port Writes "0" to Semaphore

Right Port Writes "0" to Semaphore

Left Port Writes "1" to Semaphore

Left Port Writes "0" to Semaphore

Right Port Writes "1" to Semaphore

Left Port Writes "1" to Semaphore

Right Port Writes "0" to Semaphore

Right Port Writes "1" to Semaphore

Left Port Writes "0" to Semaphore

Left Port Writes "1" to Semaphore

0

1

0

1

0

1

0

1

0

1

Left port has semaphore token

No change. Right side has no write access to semaphore

Right port obtains semaphore token

No change. Left port has no write access to semaphore

Left port obtains semaphore token

Semaphore free

Right port has semaphore token

Semaphore free

Left port has semaphore token

Semaphore free

2738 tbl 19

NOTES:

1. This table denotes a sequence of events for only one of the eight semaphores on the IDT7005.

2. There are eight semaphore flags written to via I/O0 and read from all I/O's. These eight semaphores are addressed by A0 - A2.

3. CE=VIH, SEM=VIL to access the semaphores. Refer to the semaphore Read/Write Control Truth Table.

FunctionalDescription

(HEX), where a write is defined as CE = R/W= VIL per Truth Table III.

Theleftportclearstheinterruptthroughaccessofaddresslocation1FFE

when CE =OE = VIL. For this example, R/Wis a "don't care". Likewise,

therightportinterruptflag(INTR)isassertedwhentheleftportwritesto

memory location 1FFF (HEX) and to clear the interrupt flag (INTR), the

rightportmustreadthememorylocation1FFF.Themessage(8bits)at

1FFEor1FFFisuser-defined,sinceitisanaddressableSRAMlocation.

Iftheinterruptfunctionisnotused,addresslocations1FFEand1FFFare

notusedasmailboxes,butaspartoftherandomaccessmemory.Refer

toTruthTableIIIfortheinterruptoperation.

TheIDT7005providestwoportswithseparatecontrol,addressand

I/Opinsthatpermitindependentaccessforreadsorwritestoanylocation

inmemory.TheIDT7005hasanautomaticpowerdownfeaturecontrolled

by CE. The CE controls on-chip power down circuitry that permits the

respectiveporttogointoastandbymodewhennotselected(CEHIGH).

Whenaportisenabled,accesstotheentirememoryarrayispermitted.

Interrupts

Iftheuserchoosestheinterruptfunction,amemorylocation(mailbox

or message center) is assigned to each port. The left port interrupt flag

(INTL) is asserted when the right port writes to memory location 1FFE

6.42

16

IDT7005S/L

High-Speed 8K x 8 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

SLAVE

Dual Port

RAM

MASTER

Dual Port

RAM

CE

BUSY (L) BUSY (R)

MASTER

Dual Port

RAM

SLAVE

Dual Port

RAM

CE

BUSY (R)

BUSY (L) BUSY (R)

BUSY (L)

2738 drw 19

Figure 3. Busy and chip enable routing for both width and depth expansion with IDT7005 RAMs.

BusyLogic

address signals only. It ignores whether an access is a read or write.

In a master/slave array, both address and chip enable must be valid

long enough for a BUSY flag to be output from the master before the

actualwritepulsecanbeinitiatedwiththeR/Wsignal.Failuretoobserve

thistimingcanresultinaglitchedinternalwriteinhibitsignalandcorrupted

dataintheslave.

BusyLogicprovidesahardwareindicationthatbothportsoftheRAM

haveaccessedthesamelocationatthesametime.Italsoallowsoneofthe

twoaccessestoproceedandsignalstheothersidethattheRAMis“busy”.

The BUSYpincanthenbeusedtostalltheaccessuntiltheoperationon

theothersideiscompleted.Ifawriteoperationhasbeenattemptedfrom

thesidethatreceivesaBUSYindication,thewritesignalisgatedinternally

topreventthewritefromproceeding.

TheuseofBUSYlogicisnotrequiredordesirableforallapplications.

InsomecasesitmaybeusefultologicallyORtheBUSYoutputstogether

and use any BUSY indication as an interrupt source to flag the event of

anillegalorillogicaloperation.IfthewriteinhibitfunctionofBUSYlogicis

notdesirable,theBUSYlogiccanbedisabledbyplacingthepartinslave

modewiththeM/Spin.OnceinslavemodetheBUSYpinoperatessolely

asawriteinhibitinputpin.Normaloperationcanbeprogrammedbytying

the BUSY pins HIGH. If desired, unintended write operations can be

prevented to a port by tying the BUSY pin for that port LOW.

TheBUSYoutputsontheIDT7005RAMinmastermode,arepush-

pulltypeoutputsanddonotrequirepullupresistorstooperate. Ifthese

RAMs are being expanded in depth, then the BUSY indication for the

resulting array requires the use of an external AND gate.

Semaphores

TheIDT7005isanextremelyfastDual-Port8Kx8CMOSStaticRAM

withanadditional8addresslocationsdedicatedtobinarysemaphoreflags.

TheseflagsalloweitherprocessorontheleftorrightsideoftheDual-Port

RAMtoclaimaprivilegeovertheotherprocessorforfunctionsdefinedby

thesystemdesigner’ssoftware.Asanexample,thesemaphorecanbe

usedbyoneprocessortoinhibittheotherfromaccessingaportionofthe

Dual-Port RAM or any other shared resource.

The Dual-Port RAM features a fast access time, and both ports are

completelyindependentofeachother.Thismeansthattheactivityonthe

leftportinnowayslowstheaccesstimeoftherightport. Bothportsare

identicalinfunctiontostandardCMOSStaticRAMandcanbereadfrom,

orwrittento,atthesametimewiththeonlypossibleconflictarisingfromthe

simultaneous writing of, or a simultaneous READ/WRITE of, a non-

semaphorelocation.Semaphoresareprotectedagainstsuchambiguous

situationsandmaybeusedbythesystemprogramtoavoidanyconflicts

inthenon-semaphoreportionoftheDual-PortRAM.Thesedeviceshave

anautomaticpower-downfeaturecontrolledbyCE,theDual-PortRAM

enable,andSEM,thesemaphoreenable.TheCEandSEMpinscontrol

on-chip power down circuitry that permits the respective port to go into

standbymodewhennotselected. Thisistheconditionwhichisshownin

Truth Table I where CE and SEM are both HIGH.

SystemswhichcanbestusetheIDT7005containmultipleprocessors

or controllers and are typically very high-speed systems which are

softwarecontrolledorsoftwareintensive.Thesesystemscanbenefitfrom

aperformanceincreaseofferedbytheIDT7005'shardwaresemaphores,

whichprovidealockoutmechanismwithoutrequiringcomplexprogram-

ming.

Width Expansion with Busy Logic

Master/SlaveArrays

WhenexpandinganIDT7005RAMarrayinwidthwhileusingBUSY

logic,onemasterpartisusedtodecidewhichsideoftheRAMarraywill

receivea BUSYindication,andtooutputthatindication.Anynumberof

slavestobeaddressedinthesameaddressrangeasthemaster,usethe

BUSYsignalasawriteinhibitsignal.ThusontheIDT7005RAMtheBUSY

pinisanoutputifthepartisusedasamaster(M/Spin=VIH),andtheBUSY

pin is an input if the part used as a slave (M/S pin = VIL) as shown in

Figure 3.

Iftwoormoremasterpartswereusedwhenexpandinginwidth,asplit

decisioncouldresultwithonemasterindicatingBUSY ononesideofthe

arrayandanothermasterindicating BUSYononeothersideofthearray.

Thiswouldinhibitthewriteoperationsfromoneportforpartofawordand

inhibitthewriteoperationsfromtheotherportfortheotherpartoftheword.

The BUSY arbitration on a master is based on the chip enable and

Softwarehandshakingbetweenprocessorsoffersthemaximumin

systemflexibilitybypermittingsharedresourcestobeallocatedinvarying

6.42

17

IDT7005S/L

High-Speed 8K x 8 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

configurations.TheIDT7005doesnotuseitssemaphoreflagstocontrol cause either signal (SEM or OE) to go inactive or the output will

anyresourcesthroughhardware,thusallowingthesystemdesignertotal never change.

flexibilityinsystemarchitecture.

AsequenceWRITE/READmustbeusedbythesemaphoreinorder

An advantage of using semaphores rather than the more common to guarantee that no system level contention will occur. A processor

methodsofhardwarearbitrationisthatwaitstatesareneverincurredin requestsaccesstosharedresourcesbyattemptingtowriteazerointoa

either processor. This can prove to be a major advantage in very semaphorelocation.Ifthesemaphoreisalreadyinuse,thesemaphore

high-speedsystems.

requestlatchwillcontainazero,yetthesemaphoreflagwillappearasone,

afactwhichtheprocessorwillverifybythesubsequentread(seeTruth

TableV).Asanexample,assumeaprocessorwritesazerototheleftport

atafreesemaphorelocation.Onasubsequentread,theprocessorwill

verifythatithaswrittensuccessfullytothatlocationandwillassumecontrol

overtheresourceinquestion.Meanwhile,ifaprocessorontherightside

attemptstowriteazerotothesamesemaphoreflagitwillfail, aswillbe

verifiedbythefactthataonewillbereadfromthatsemaphoreontheright

side during subsequent read. Had a sequence of READ/WRITE been

usedinstead,systemcontentionproblemscouldhaveoccurredduringthe

gap between the read and write cycles.

Itisimportanttonotethatafailedsemaphorerequestmustbefollowed

byeitherrepeatedreadsorbywritingaoneintothesamelocation. The

reasonforthisiseasilyunderstoodbylookingatthesimplelogicdiagram

ofthesemaphoreflaginFigure4.Twosemaphorerequestlatchesfeed

into a semaphore flag. Whichever latch is first to present a zero to the

semaphoreflagwillforceitssideofthesemaphoreflagLOWandtheother

sideHIGH.Thisconditionwillcontinueuntilaoneiswrittentothesame

semaphorerequestlatch.Shouldtheotherside’ssemaphorerequestlatch

havebeenwrittentoazerointhemeantime,thesemaphoreflagwillflip

overtotheothersideassoonasaoneiswrittenintothefirstside’srequest

latch.Thesecondside’sflagwillnowstayLOWuntilitssemaphorerequest

latchiswrittentoaone.Fromthisitiseasytounderstandthat,ifasemaphore

is requested and the processor which requested it no longer needs the

resource, the entire system can hang up until a one is written into that

semaphorerequestlatch.

The critical case of semaphore timing is when both sides request a

single token by attempting to write a zero into it at the same time. The

semaphorelogicisspeciallydesignedtoresolvethisproblem.Ifsimulta-

neousrequestsaremade,thelogicguaranteesthatonlyonesidereceives

thetoken. Ifonesideisearlierthantheotherinmakingtherequest, the

firstsidetomaketherequestwillreceivethetoken.Ifbothrequestsarrive

at the same time, the assignment will be arbitrarily made to one port or

the other.

One caution that should be noted when using semaphores is that

semaphoresalonedonotguaranteethataccesstoaresourceissecure.

Aswithanypowerfulprogrammingtechnique,ifsemaphoresaremisused

or misinterpreted, a software error can easily happen.

How the Semaphore Flags Work

Thesemaphorelogicisasetofeightlatcheswhichareindependent

oftheDual-PortRAM.Theselatchescanbeusedtopassaflag,ortoken,

fromoneporttotheothertoindicatethatasharedresourceisinuse.The

semaphores provide a hardware assist for a use assignment method

called“TokenPassingAllocation.”Inthismethod,thestateofasemaphore

latchisusedasatokenindicatingthatsharedresourceisinuse.Iftheleft

processorwantstousethisresource,itrequeststhetokenbysettingthe

latch.Thisprocessorthenverifiesitssuccessinsettingthelatchbyreading

it. If it was successful, it proceeds to assume control over the shared

resource.Ifitwasnotsuccessfulinsettingthelatch,itdeterminesthatthe

rightsideprocessorhassetthelatchfirst, hasthetokenandisusingthe

sharedresource.Theleftprocessorcantheneitherrepeatedlyrequest

thatsemaphore’sstatusorremoveitsrequestforthatsemaphoretoperform

anothertaskandoccasionallyattemptagaintogaincontrolofthetokenvia

thesetandtestsequence.Oncetherightsidehasrelinquishedthetoken,

theleftsideshouldsucceedingainingcontrol.

ThesemaphoreflagsareactiveLOW.Atokenisrequestedbywriting

azerointoasemaphorelatchandisreleasedwhenthesamesidewrites

aonetothatlatch.

The eight semaphore flags reside within the IDT7005 in a separate

memoryspacefromtheDual-PortRAM.Thisaddressspaceisaccessed

byplacingaLOWinputontheSEMpin(whichactsasachipselectforthe

semaphore flags) and using the other control pins (Address, OE, and

R/W) as they would be used in accessing a standard static RAM. Each

oftheflagshasauniqueaddresswhichcanbeaccessedbyeitherside

throughaddresspinsA0–A2.Whenaccessingthesemaphores,noneof

theotheraddresspinshasanyeffect.

Whenwritingtoasemaphore,onlydatapinD0isused.IfaLOWlevel

iswrittenintoanunusedsemaphorelocation,thatflagwillbesettoazero

on that side and a one on the other side (see Truth Table V). That

semaphorecannowonlybemodifiedbythesideshowingthezero.When

aoneiswrittenintothesamelocationfromthesameside,theflagwillbe

settoaoneforbothsides(unlessasemaphorerequestfromtheotherside

ispending)andthencanbewrittentobybothsides. Thefactthattheside

whichisabletowriteazerointoasemaphoresubsequentlylocksoutwrites

fromtheothersideiswhatmakessemaphoreflagsusefulininterprocessor

communications.(Athoroughdiscussionontheuseofthisfeaturefollows

shortly.)Azerowrittenintothesamelocationfromtheothersidewillbe

storedinthesemaphorerequestlatchforthatsideuntilthesemaphoreis

freedbythefirstside.

Initializationofthesemaphoresisnotautomaticandmustbehandled

viatheinitializationprogramatpower-up.Sinceanysemaphorerequest

flagwhichcontainsazeromustberesettoaone,allsemaphoresonboth

sidesshouldhaveaonewrittenintothematinitializationfrombothsides

to assure that they will be free when needed.

Whenasemaphoreflagisread,itsvalueisspreadintoalldatabitsso

thataflagthatisaonereadsasaoneinalldatabitsandaflagcontaining

azeroreadsasallzeros.Thereadvalueislatchedintooneside’soutput

UsingSemaphores—SomeExamples

Perhapsthesimplestapplicationofsemaphoresistheirapplicationas

registerwhenthatside'ssemaphoreselect(SEM)andoutputenable(OE) resourcemarkersfortheIDT7005’sDual-PortRAM.Saythe8Kx8RAM

signalsgoactive.Thisservestodisallowthesemaphorefromchanging wastobedividedintotwo4Kx8blockswhichweretobededicatedatany

stateinthemiddleofareadcycleduetoawritecyclefromtheotherside. onetimetoservicingeithertheleftorrightport.Semaphore0couldbeused

Becauseofthislatch,arepeatedreadofasemaphoreinatestloopmust toindicatethesidewhichwouldcontrolthelowersectionofmemory,and

6.42

18

IDT7005S/L

High-Speed 8K x 8 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

Semaphore 1 could be defined as the indicator for the upper section of evenbeassigneddifferentmeaningsondifferentsidesratherthanbeing

memory.

Totakearesource,inthisexamplethelower4Kof Dual-PortRAM,

given a common meaning as was shown in the example above.

Semaphores are a useful form of arbitration in systems like disk

the processor on the left port could write and then read a zero in to interfaceswheretheCPUmustbelockedoutofasectionofmemoryduring

Semaphore0.Ifthistaskweresuccessfullycompleted(azerowasread atransferandtheI/Odevicecannottolerateanywaitstates.Withtheuse

back rather than a one), the left processor would assume control of the ofsemaphores,oncethetwodeviceshasdeterminedwhichmemoryarea

lower4K.Meanwhiletherightprocessorwasattemptingtogaincontrolof was“off-limits”totheCPU,boththeCPUandtheI/Odevicescouldaccess

theresourceaftertheleftprocessor,itwouldreadbackaoneinresponse theirassignedportionsofmemorycontinuouslywithoutanywaitstates.

tothezeroithadattemptedtowriteintoSemaphore0. Atthispoint, the

Semaphoresarealsousefulinapplicationswherenomemory“WAIT”

softwarecouldchoosetotryandgaincontrolofthesecond4Ksectionby stateisavailableononeorbothsides.Onceasemaphorehandshakehas

writing,thenreadingazerointoSemaphore1.Ifitsucceededingaining been performed, both processors can access their assigned RAM

control,itwouldlockouttheleftside.

segmentsatfullspeed.

Once the left side was finished with its task, it would write a one to

Anotherapplicationisintheareaofcomplexdatastructures.Inthis

Semaphore 0 and may then try to gain access to Semaphore 1. If case,blockarbitrationisveryimportant.Forthisapplicationoneprocessor

Semaphore1wasstilloccupiedbytherightside,theleftsidecouldundo mayberesponsibleforbuildingandupdatingadatastructure.Theother

itssemaphorerequestandperformothertasksuntilitwasabletowrite,then processorthenreadsandinterpretsthatdatastructure.Iftheinterpreting

readazerointoSemaphore1.Iftherightprocessorperformsasimilartask processorreadsanincompletedatastructure,amajorerrorconditionmay

withSemaphore0,thisprotocolwouldallowthetwoprocessorstoswap exist.Therefore,somesortofarbitrationmustbeusedbetweenthetwo

4K blocks of Dual-Port RAM with each other.

differentprocessors.Thebuildingprocessorarbitratesfortheblock,locks

The blocks do not have to be any particular size and can even be itandthenisabletogoinandupdatethedatastructure.Whentheupdate

variable, depending upon the complexity of the software using the is completed, the data structure block is released. This allows the

semaphoreflags.AlleightsemaphorescouldbeusedtodividetheDual- interpretingprocessortocomebackandreadthecompletedatastructure,

Port RAM or other shared resources into eight parts. Semaphores can therebyguaranteeingaconsistentdatastructure.

L PORT

R PORT

SEMAPHORE

REQUEST FLIP FLOP

SEMAPHORE

REQUEST FLIP FLOP

D0

D

D0

Q

WRITE

SEMAPHORE

READ

SEMAPHORE

,

READ

2738 drw 20

Figure 4. IDT7005 Semaphore Logic

6.42

19

IDT7005S/L

High-Speed 8K x 8 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

OrderingInformation

XXXXX

A

999

A

Device Power Speed Package

Type

Process/

Temperature

Range

Tube or Tray

Tape and Reel

Blank

8

Blank Commercial (0°C to +70°C)

I⁽¹⁾

B

Industrial (-40°C to +85°C)

Military (-55°C to +125°C)

Compliant to MIL-PRF-38538 QML

G⁽²⁾

Green

64-pin TQFP (PN64-1)

68-pin PGA (G68-1)

68-pin PLCC (J68-1)

68-pin Flatpack (F64-1)

PF

G

J

F

Commercial Only

Commercial, Industrial & Military

Commercial & Military

Commercial, Industrial & Military

Military Only

15

17

20

25

35

55

70

Speed in nanoseconds

S

L

Standard Power

Low Power

7005 64K (8K x 8) Dual-Port RAM

2738 drw 21

NOTES:

1. Industrial temperature range is available on selected TQFP packages in standard power.

For other speeds, packages and powers contact your sales office.

2. Green parts available. For specific speeds, packages and powers contact your local sales office.

DatasheetDocumentHistory

12/21/98:

Initiateddatasheetdocumenthistory

Convertedtonewformat

Cosmeticandtypographicalcorrections

Addedadditionalnotestopinconfigurations

Changeddrawingformat

Replaced IDT logos

Addedcopywrightinfo

Fixed overbar errors

Increatedstoragetemperatureparameter

ClarifiedTA Parameter

DCElectricalparameters–changedwordingfrom"open"to"disabled"

Changed±500mVto0mVinnotes

Addeddaterevisionforpinconfigurations

Pages 2 & 3

06/03/99:

11/10/99:

08/07/00:

Page 1

Page 4

Page 6

09/18/01:

Page 2 & 3

Page 14

Replaced one copy of table 13b with 13a for 15, 17,20 & 25ns speeds for AC Electrical Characteristics

INTERRUPT TIMING

6.42

20

IDT7005S/L

High-Speed 8K x 8 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

DatasheetDocumentHistory(continued)

01/31/06:

Page 1

Addedgreenavailabilitytofeatures

Page 20

Pages 6,7,9,12,& 14

Addedgreenindicatortoorderinginformation

Removed "IDT" from orderable part number

In all of the DC & AC Electrical tables the 7005X20 speed grade

changedfrom7005X20Com'l&MilitarytoincludeIndmakingit

Com'l, Ind&Military

10/21/08:

09/17/12:

Page 20

AddedT&Rindicatortoorderinginformation

CORPORATE HEADQUARTERS

6024 Silver Creek Valley Road

San Jose, CA 95138

for SALES:

for Tech Support:

408-284-2794

DualPortHelp@idt.com

800-345-7015 or 408-284-8200

fax: 408-284-2775

www.idt.com

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

6.42

21


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厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	PLCC-68, Tube
文件：	总21页 (文件大小：358K)
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