7008S15PFGI8 [IDT]
HIGH-SPEED 64K x 8 DUAL-PORT STATIC RAM;
| 型号： | 7008S15PFGI8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | HIGH-SPEED 64K x 8 DUAL-PORT STATIC RAM |
| 文件： | 总20页 (文件大小：181K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HIGH-SPEED
IDT7008S/L
64K x 8 DUAL-PORT
STATIC RAM
LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018
Features
◆
◆
True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
High-speed access
IDT7008 easily expands data bus width to 16 bits or
more using the Master/Slave select when cascading more
than one device
M/S = VIH for BUSY output flag on Master,
M/S = VIL for BUSY input on Slave
Interrupt Flag
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
TTL-compatible, single 5V (±10%) power supply
Available in 84-pin PGA, 84-pin PLCC, and a 100-pin TQFP
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
◆
◆
– Commercial:15/20/25/35/55ns(max.)
– Industrial:20/55ns(max.)
Low-poweroperation
◆
◆
◆
◆
– IDT7008S
Active:750mW(typ.)
Standby: 5mW (typ.)
– IDT7008L
◆
◆
◆
◆
Active:750mW(typ.)
Standby: 1mW (typ.)
Dual chip enables allow for depth expansion without
external logic
◆
◆
Green parts available, see ordering information
FunctionalBlockDiagram
R/W
L
R
R/W
CE0L
CE1L
CE0R
CE1R
OE
L
OE
R
I/O
Control
I/O
Control
I/O0-7L
I/O0-7R
BUSYL(1,2)
(1,2)
BUSY
R
64Kx8
MEMORY
ARRAY
7008
A
15L
A
A
15R
0R
Address
Decoder
Address
Decoder
A
0L
16
16
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE0L
CE0R
1L
CE
1R
CE
OE
L
L
OE
R
R/W
R
R/W
SEM
INTL
L
R
SEM
(2)
(2)
INT
R
M/S(1)
3198 drw 01
NOTES:
1. BUSY is an input as a Slave (M/S = VIL) and an output when it is a Master (M/S = VIH).
2. BUSY and INT are non-tri-state totem-pole outputs (push-pull).
MARCH 2018
1
©2018 Integrated Device Technology, Inc.
DSC 3198/12
IDT7008S/L
High-Speed 64K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Description
The IDT7008 is a high-speed 64K x 8 Dual-Port Static RAM. The reads or writes to any location in memory. An automatic power down
IDT7008isdesignedtobeusedasastand-alone512K-bitDual-PortRAM featurecontrolledbythe chipenables(CE0andCE1)permittheon-chip
orasacombinationMASTER/SLAVEDual-PortRAMfor16-bit-or-more circuitry of each port to enter a very low standby power mode.
wordsystems.UsingtheIDTMASTER/SLAVEDual-PortRAMapproach
Fabricated using a CMOS high-performance technology, these
in16-bitorwidermemorysystemapplicationsresultsinfull-speed,error- devicestypicallyoperateononly750mWofpower.
freeoperationwithouttheneedforadditionaldiscretelogic.
TheIDT7008ispackagedina84-pinCeramicPinGridArray(PGA),
This device provides two independent ports with separate control, a84-pinPlasticLeadlessChipCarrier(PLCC)anda100-pinThinQuad
address,andI/Opinsthatpermitindependent,asynchronousaccessfor Flatpack(TQFP).
PinConfigurations(1,2,3)
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12
A
A
A
7L
8L
9L
33
34
11
10
9
A
A
A
A
A
A
A
A
A
7R
8R
35
36
37
38
9R
A10L
10R
11R
12R
13R
8
A11L
7
A
A
12L
13L
6
39
40
41
42
43
44
45
46
47
48
49
5
A14L
4
14R
15R
A15L
3
NC
Vcc
2
NC
GND
NC
7008
J84
1
(3,4)
NC
NC
CE0L
CE1L
84
83
82
81
80
79
78
NC
CE0R
CE1R
SEM
RIW
L
SEM
R
L
R/W
OE
R
50
51
OE
L
R
GND
GND
GND
NC
77
76
52
53
GND
NC
75
54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74
NOTES:
3198 drw 02
1. AllVccpinsmustbeconnectedtopowersupply.
2. Packagebodyisapproximately1.15inx1.15inx.17in.
3. Thispackagecodeisusedtoreferencethepackagediagram.
4. AllGNDpinsmustbeconnectedtogroundsupply.
2
IDT7008S/L
High-Speed 64K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Pin Configurations(1,2,3) (con't.)
75
74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
NC
NC
76
50
49
48
47
NC
NC
NC
77
78
A6R
A
5R
I/O7R
79
80
A4R
46
45
I/O6R
I/O5R
I/O4R
I/O3R
Vcc
I/O2R
I/O1R
I/O0R
GND
Vcc
A3R
A2R
A1R
A0R
81
44
82
83
43
42
84
85
INTR
41
40
BUSY
R
86
87
88
89
7008
PN100
M/S
GND
39
38
(3
)
BUSY
INT
NC
L
37
36
L
I/O0L
I/O1L
90
91
35
34
A0L
GND
I/O2L
I/O3L
I/O4L
I/O5L
I/O6L
I/O7L
NC
92
93
A1L
33
A2L
94
32
31
A3L
95
96
A
4L
5L
6L
30
29
A
A
97
98
99
28
27
26
NC
NC
100
1
GND
2
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
3198 drw 03
NOTES:
1. AllVccpinsmustbeconnectedtopowersupply.
2. Packagebodyisapproximately14mmx14mmx1.4mm.
3. Thispackagecodeisusedtoreferencethepackagediagram.
3
6.42
IDT7008S/L
High-Speed 64K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Pin Configurations(1,2,3) (con't)
63
66
67
69
72
61
64
65
68
71
60
58
55
54
49
51
50
48
46
45
42
40
11
10
09
08
A
7R
A
9R
A
10R
A
12R
A
15R
NC
GND
NC
NC SEM
R
OER
62
59
56
47
44
43
A
A
A
4R
3R
1R
A
A
A
6R
5R
2R
A8R
A
11R
A
14R
CE0R R/W
R
GND
NC
I/O6R
CE1R
57
53
52
41
39
A
13R GND
NC
I/O7R I/O5R
38
37
I/O4R I/O3R
73
33
35
34
I/O0R
I/O2R I/O1R
M
INT
R
/S
BUSY
R
07
IDT7008G
G84
(4)
75
70
74
32
31
36
06 BUSY
L
GND
GND
A
0R
Vcc
Vcc
84-PIN PGA
TOP VIEW
(5)
76
77
78
28
29
30
NC
A0L
INT
L
I/O1
L
I/O0L
GND
05
04
79
80
83
1
26
27
A1L
A
A
A
2L
I/O3L I/O2L
81
82
84
7
8
9
11
12
14
23
25
03
02
01
NC
A
3L
5L
7L
A
13L
Vcc
NC
I/O6L I/O4L
2
4
5
6
10
17
20
22
24
A
4L
6L
A8L
A
11L
A14L
CE0L R/W
L
GND I/O7L I/O5L
3
15
13
16
18
19
21
GND
A
A9L
A10L
A12L
A15L
NC
G
OEL
NC
L
CE1L
F
SEML
A
B
C
D
E
H
J
K
3198 drw 04
INDEX
NOTES:
1. All Vcc pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. Package body is approximately 1.12 in x 1.12 in x .16 in.
PinNames
Left Port
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part marking.
Right Port
CE0R, CE1R
R/W
OE
Names
Chip Enables
CE0L, CE1L
R/W
L
R
Read/Write Enable
Output Enable
Address
OEL
R
A
0L - A15L
A
0R - A15R
I/O0R - I/O7R
SEM
INT
BUSY
M/S
I/O0L - I/O7L
SEM
INT
BUSY
Data Input/Output
Semaphore Enable
Interrupt Flag
Busy Flag
L
R
L
R
L
R
Master or Slave Select
Power
V
CC
GND
Ground
3198 tbl 01
4
IDT7008S/L
High-Speed 64K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Truth Table I: Chip Enable(1)
CE
1
Mode
CE
CE0
V
IL
V
IH
Port Selected (TTL Active)
L
< 0.2V
>VCC -0.2V
X
Port Selected (CMOS Active)
Port Deselected (TTL Inactive)
Port Deselected (TTL Inactive)
Port Deselected (CMOS Inactive)
Port Deselected (CMOS Inactive)
V
IH
X
VIL
H
>VCC -0.2V
X
X
<0.2V
3198 tbl 02
NOTES:
1. Chip Enable references are shown above with the actual CE0 and CE1 levels, CE is a reference only.
Truth Table II: Non-Contention Read/Write Control
Inputs(1)
Outputs
(2)
R/W
I/O0-7
Mode
CE
OE
X
SEM
H
H
L
X
L
High-Z
DATAIN
Deselected: Power-Down
Write to memory
X
H
L
H
X
L
H
DATAOUT Read memory
High-Z Outputs Disabled
X
H
X
3198 tbl 03
NOTES:
1. A0L – A15L ≠ A0R – A15R.
2. Refer to Chip Enable Truth Table.
Truth Table III: Semaphore Read/Write Control(1)
Inputs
Outputs
(2)
R/W
I/O0-7
Mode
CE
OE
SEM
H
H
↑
X
L
L
DATAOUT Read Semaphore Flag Data Out
H
L
X
X
L
L
DATAIN
Write I/O0 into Semaphore Flag
______
Not Allowed
3198 tbl 04
NOTES:
1. There are eight semaphore flags written to via I/O0 and read from all the I/Os (I/O0-I/O7). These eight semaphore flags are addressed by A0-A2.
2. Refer to Chip Enable Truth Table.
5
6.42
IDT7008S/L
High-Speed 64K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AbsoluteMaximumRatings(1)
RecommendedDCOperating
Conditions
Symbol
Rating
Commercial
& Industrial
Unit
Symbol
Parameter
Min.
Typ.
Max. Unit
(2)
V
TERM
Terminal Voltage
with Respect
to GND
-0.5 to +7.0
V
V
CC
Supply Voltage
4.5
5.0
5.5
0
V
V
V
GND
Ground
0
0
T
BIAS
STG
Temperature
Under Bias
-55 to +125
-65 to +150
50
oC
oC
6.0(2)
0.8
____
V
IH
IL
Input High Voltage
Input Low Voltage
2.2
T
Storage
Temperature
-0.5(1)
V
____
V
3198 tbl 07
IOUT
DC Output Current
mA
NOTES:
1. VIL > -1.5V for pulse width less than 10ns.
2. VTERM must not exceed Vcc + 10%.
3198 tbl 05
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect
reliability.
Capacitance
2. VTERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of VTERM > Vcc + 10%.
(TA = +25°C, f = 1.0mhz) (TQFP Only)
Symbol
Parameter
Input Capacitance
Output Capacitance
Conditions
Max. Unit
CIN
V
IN = 0V
9
pF
(2)
OUT
C
V
OUT = 0V
10
pF
3198 tbl 08
MaximumOperatingTemperature
andSupplyVoltage(1)
NOTES:
1. This parameter is determined by device characterization but is not production
tested.
Ambient
2. COUT also references CI/O.
Grade
Commercial
Industrial
Temperature
0OC to +70OC
-40OC to +85OC
GND
0V
Vcc
5.0V
5.0V
+
+
10%
10%
0V
3198 tbl 06
NOTES:
1. This is the parameter TA. This is the "instant on" case tempreature.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(2) (VCC = 5.0V ± 10%)
7008S
7008L
Symbol
|ILI
|ILO
Parameter
Input Leakage Current(1)
Output Leakage Current
Output Low Voltage
Test Conditions
CC = 5.5V, VIN = 0V to VCC
CE = VIH, VOUT = 0V to VCC
OL = 4mA
OH = -4mA
Min.
Max.
10
Min.
Max.
Unit
µA
µA
V
___
___
|
V
5
5
___
___
___
___
|
10
V
OL
OH
I
0.4
0.4
___
___
V
Output High Voltage
I
2.4
2.4
V
3198 tbl 09
NOTES:
1. At Vcc < 2.0V, input leakages are undefined.
2. Refer to Chip Enable Truth Table.
6
IDT7008S/L
High-Speed 64K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1,6) (VCC = 5.0V ± 10%)
7008X15
7008X20
7008X25
Com'l Only
Com'l Only
Com'l & Ind
Typ.(2)
Typ.(2)
Typ.(2)
Symbol
Parameter
Test Condition
Version
COM'L
Max.
Max.
Max.
Unit
ICC
Dynamic Operating
S
L
205
200
365
325
190
180
325
285
180
170
305
265
mA
CE = VIL, Outputs Disabled
SEM = VIH
Current
(3)
(Both Ports Active)
f = fMAX
___
___
___
___
___
___
___
___
___
___
IND
S
L
180
335
I
SB1
Standby Current
(Both Ports - TTL Level
Inputs)
COM'L
IND
S
L
65
65
110
90
50
50
90
70
40
40
85
60
mA
mA
CE
SEM
f = fMAX
L
= CE
R
= VIH
= VIH
R
= SEM
L
(3)
___
___
___
___
___
___
___
___
___
___
S
L
50
85
(5)
ISB2
Standby Current
(One Port - TTL Level
Inputs)
COM'L
IND
S
L
130
130
245
215
115
115
215
185
105
105
200
170
CE"A" = VIL and CE"B" = VIH
Active Port Outputs Disabled,
(3)
f=fMAX
___
___
___
___
___
___
___
___
___
___
S
L
SEM
R
= SEM
L
= VIH
115
220
I
SB3
Full Standby Current
(Both Ports - All CMOS
Level Inputs)
Both Ports CE
L
and
mA
mA
COM'L
IND
S
L
1.0
0.2
15
5
1.0
0.2
15
5
1.0
0.2
15
5
CE
R
> VCC - 0.2V
V
V
IN > VCC - 0.2V or
___
___
___
___
___
___
___
___
___
___
IN < 0.2V, f = 0(4)
S
L
0.2
10
SEMR = SEML > VCC - 0.2V
ISB4
Full Standby Current
(One Port - All CMOS
Level Inputs)
COM'L
IND
S
L
120
120
220
190
110
110
190
160
100
100
170
145
CE"A" < 0.2V and
CE"B" > VCC - 0.2V(5)
SEMR = SEML > VCC - 0.2V
___
___
___
___
___
___
___
___
___
___
S
L
V
IN > VCC - 0.2V or VIN < 0.2V
110
195
Active Port Outputs Disabled
(3)
f = fMAX
3198 tbl 10a
7008X35
Com'l Only
7008X55
Com'l & Ind
Typ.(2)
Symbol
Parameter
Test Condition
Version
COM'L
Max.
Typ.(2)
Max.
Unit
ICC
Dynamic Operating Current
(Both Ports Active)
S
160
160
295
255
150
150
270
230
mA
CE = VIL, Outputs Disabled
L
SEM = VIH
(3)
f = fMAX
_____
_____
_____
_____
IND
S
L
150
150
310
270
ISB1
ISB2
Standby Current
(Both Ports - TTL Level
Inputs)
COM'L
IND
S
L
30
30
85
60
20
20
85
60
mA
mA
CEL = CER = VIH
SEMR = SEML = VIH
_____
_____
_____
_____
S
L
13
13
100
80
(5)
Standby Current
(One Port - TTL Level
Inputs)
COM'L
IND
S
L
95
95
185
155
85
85
165
135
CE"A" = VIL and CE"B" = VIH
Active Port Outputs Disabled,
(3)
f=fMAX
_____
_____
_____
_____
S
L
85
85
195
165
SEMR = SEML = VIH
ISB3
ISB4
Full Standby Current
(Both Ports - All CMOS
Level Inputs)
Both Ports CEL and
CER > VCC - 0.2V
mA
mA
COM'L
IND
S
L
1.0
0.2
15
5
1.0
0.2
15
5
VIN > VCC - 0.2V or
_____
_____
_____
_____
VIN < 0.2V, f = 0(4)
SEMR = SEML > VCC - 0.2V
S
L
1.0
0.2
30
10
Full Standby Current
(One Port - All CMOS
Level Inputs)
COM'L
IND
S
L
90
90
160
135
80
80
135
110
CE"A" < 0.2V and
CE"B" > VCC - 0.2V(5)
SEMR = SEML > VCC - 0.2V
___
___
___
___
80
80
175
150
VIN > VCC - 0.2V or VIN < 0.2V
Active Port Outputs Disabled
S
L
(3)
f = fMAX
3198 tbl 10b
NOTES:
1. 'X' in part numbers indicates power rating (S or L)
2. VCC = 5V, TA = +25°C, and are not production tested. ICCDC = 120mA (Typ.)
3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/ tRC, and using “AC Test Conditions” of input
levels of GND to 3V.
4. f = 0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
6. Refer to Chip Enable Truth Table.
7
6.42
IDT7008S/L
High-Speed 64K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
5V
5V
AC Test Conditions
Input Pulse Levels
GND to 3.0V
5ns Max.
1.5V
893Ω
893Ω
Input Rise/Fall Times
DATAOUT
BUSY
INT
DATAOUT
Input Timing Reference Levels
Output Reference Levels
1.5V
30pF
5pF*
347Ω
347Ω
Output Load
Figures 1 and 2
3198 tbl 11
3198 drw 05
3198 drw 06
Figure 2. Output Test Load
(for tLZ, tHZ, tWZ, tOW)
Figure 1. AC Output Test Load
* Including scope and jig.
Waveform of Read Cycles(5)
tRC
ADDR
(4)
tAA
(4)
CE(6)
OE
t
ACE
(4)
tAOE
R/W
(1)
tOH
tLZ
VALID DATA(4)
DATAOUT
(2)
t
HZ
BUSYOUT
(3,4)
3198 drw 07
t
BDD
Timing of Power-Up Power-Down
CE(6)
t
PU
tPD
ICC
ISB
,
3198 drw 08
NOTES:
1. Timing depends on which signal is asserted last, OE or CE.
2. Timing depends on which signal is de-asserted first CE or OE.
3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY
has no relation to valid output data.
4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBDD.
5. SEM = VIH.
6. Refer to Chip Enable Truth Table.
8
IDT7008S/L
High-Speed 64K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltageRange(6)
7008X15
7008X20
7008X25
7008X35
Com'l Only
7008X55
Com'l & Ind
Com'l Only
Com'l & Ind
Com'l Only
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
____
____
____
____
____
t
t
t
t
t
t
t
t
t
t
t
RC
Read Cycle Time
15
20
25
35
55
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
____
____
____
____
____
AA
Address Access Time
15
15
20
20
25
25
35
35
55
55
Chip Enable Access Time(4)
____
____
____
____
____
____
____
____
____
____
ACE
AOE
OH
LZ
Output Enable Access Time
Output Hold from Address Change
Output Low-Z Time(1,2)
10
12
13
20
30
____
____
____
____
____
3
3
3
3
3
____
____
____
____
____
3
3
3
3
3
Output High-Z Time(1,2)
10
12
15
15
25
____
____
____
____
____
HZ
PU
Chip Enable to Power Up Time(2)
Chip Disable to Power Down Time(2)
Semaphore Flag Update Pulse (OE or SEM)
Semaphore Address Access Time
0
0
0
0
0
____
____
____
____
____
____
____
____
____
____
PD
15
20
25
35
50
____
____
____
____
____
SOP
SAA
10
10
12
15
15
____
____
____
____
____
15
20
25
35
55
ns
3198 tbl 12
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltage(6)
7008X15
7008X20
7008X25
Com'l Only
7008X35
Com'l Only
7008X55
Com'l & Ind
Com'l Only
Com'l & Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min. Max.
Min.
Max.
Unit
WRITE CYCLE
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
t
t
t
t
t
t
t
t
t
t
t
t
WC
EW
AW
Write Cycle Time
15
12
12
0
20
15
15
0
25
20
20
0
35
30
30
0
55
45
45
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Enable to End-of-Write(3)
Address Valid to End-of-Write
Address Set-up Time(3)
AS
WP
WR
DW
HZ
Write Pulse Width
12
0
15
0
20
0
25
0
40
0
Write Recovery Time
Data Valid to End-of-Write
Output High-Z Time(1,2)
10
15
15
15
30
____
____
____
____
____
10
12
15
15
25
DH
Data Hold Time(5)
0
0
0
0
0
____
____
____
____
____
Write Enable to Output in High-Z(1,2)
Output Active from End-of-Write(1,2,5)
SEM Flag Write to Read Time
SEM Flag Contention Window
10
12
15
15
25
____
____
____
____
____
WZ
OW
SWRD
SPS
____
____
____
____
____
0
5
5
0
5
5
0
5
5
0
5
5
0
5
5
____
____
____
____
____
____
____
____
____
____
ns
3198 tbl 13
NOTES:
1. Transition is measured 0mV from Low- or High-impedance voltage with Output Test Load (Figure 2).
2. Thisparameterisguaranteedbydevicecharacterization,butisnotproductiontested.
3. To access RAM, CE= VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time.
4. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE= VIH and SEM = VIL.
5. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage
and temperature, the actual tDH will always be smaller than the actual tOW.
6. 'X' in part numbers indicates power rating (s or L).
9
6.42
IDT7008S/L
High-Speed 64K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8)
tWC
ADDRESS
(7)
tHZ
OE
tAW
CE or SEM(9,10)
(3)
(2)
(6)
AS
tWP
tWR
t
R/W
DATAOUT
DATAIN
(7)
tWZ
tOW
(4)
(4)
tDW
t
DH
3198 drw 09
Timing Waveform of Write Cycle No. 2, CE Controlled Timing(1,5)
tWC
ADDRESS
tAW
CE or SEM(9,10)
(3)
WR
(6)
(2)
t
t
EW
tAS
R/W
t
DW
tDH
DATAIN
3198 drw 10
NOTES:
1. R/W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of a LOW CE and a LOW R/W for memory array writing cycle.
3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal is asserted last, CE or R/W.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load (Figure
2).
8. If OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be
placed on the bus for the required tDW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as
the specified tWP.
9. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition.
10. Refer to Chip Enable Truth Table.
10
IDT7008S/L
High-Speed 64K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Semaphore Read after Write Timing, Either Side(1)
tSAA
tOH
A0-A2
VALID ADDRESS
VALID ADDRESS
tAW
tWR
tACE
tEW
SEM
tDW
tSOP
DATAOUT
VALID(2)
DATAIN VALID
DATA
0
tAS
tWP
tDH
R/W
tSWRD
tAOE
OE
tSOP
Write Cycle
Read Cycle
3198 drw 11
NOTES:
1. CE = VIH for the duration of the above timing (both write and read cycle) (Refer to Chip Enable Truth Table).
2. "DATAOUT VALID" represents all I/O's (I/O0 - I/O15) equal to the semaphore value.
Timing Waveform of Semaphore Write Contention(1,3,4)
A0"A"-A2"A"
MATCH
(2)
SIDE "A"
R/W"A"
SEM"A"
tSPS
A0"B"-A2"B"
MATCH
(2)
SIDE
R/W"B"
SEM"B"
"B"
3198 drw 12
NOTES:
1. DOR = DOL = VIL, CEL = CER = VIH (Refer to Chip Enable Truth Table).
2. All timing is the same for left and right ports. Port "A" may be either left or right port. "B" is the opposite from port "A".
3. This parameter is measured from R/W"A" or SEM"A" going HIGH to R/W"B" or SEM"B" going HIGH.
4. If tSPS is not satisfied, the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtain the flag.
11
6.42
IDT7008S/L
High-Speed 64K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltageRange(6)
7008X15
7008X20
7008X25
7008X35
Com'l Only
7008X55
Com'l & Ind
Com'l Only
Com'l & Ind
Com'l Only
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max. Unit
BUSY TIMING (M/S=VIH
)
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
t
t
t
t
t
t
BAA
BDA
BAC
BDC
APS
BDD
WH
15
15
15
20
20
20
20
20
20
20
20
20
45
40
40
ns
ns
ns
ns
ns
ns
ns
BUSY Access Time from Address Match
BUSY Disable Time from Address Not Matched
BUSY Access Time from Chip Enable Low
15
17
17
20
35
BUSY Access Time from Chip Enable High
Arbitration Priority Set-up Time(2)
____
____
____
____
____
5
5
5
5
5
____
____
____
____
____
BUSY Disable to Valid Data(3)
Write Hold After BUSY(5)
15
20
25
35
55
____
____
____
____
____
12
15
17
25
25
BUSY TIMING (M/S=VIL
)
____
____
____
____
____
____
____
____
____
____
BUSY Input to Write(4)
Write Hold After BUSY(5)
t
t
WB
WH
0
0
0
0
0
ns
ns
12
15
17
25
25
PORT-TO-PORT DELAY TIMING
____
____
____
____
____
____
____
____
____
____
t
t
WDD
DDD
Write Pulse to Data Delay(1)
30
25
45
30
50
35
60
45
80
65
ns
Write Data Valid to Read Data Delay(1)
ns
3198 tbl 14
NOTES:
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = VIH)".
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited on port "B" during contention on port "A".
5. To ensure that a write cycle is completed on port "B" after contention on port "A".
6. 'X' in part numbers indicates power rating (S or L).
12
IDT7008S/L
High-Speed 64K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
TimingWaveformof WritewithPort-to-PortReadandBUSY(2,5)(M/S =VIH)(4)
tWC
ADDR"A"
MATCH
tWP
R/W"A"
tDH
tDW
DATAIN "A"
VALID
(1)
tAPS
ADDR"B"
MATCH
tBDA
tBDD
BUSY"B"
t
WDD
DATAOUT "B"
VALID
(3)
tDDD
NOTES:
3198 drw 13
1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (SLAVE).
2. CEL = CER = VIL, refer to Chip Enable Truth Table.
3. OE = VIL for the reading port.
4. If M/S = VIL (SLAVE), then BUSY is an input (BUSY"A" = VIH and BUSY"B" = "don't care", for this example).
5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
Timing Waveform of Write with BUSY (M/S = VIL)
tWP
R/W"A"
(3)
tWB
BUSY"B"
(1)
tWH
R/W"B"
(2)
3198 drw 14
NOTES:
1. tWH must be met for both BUSY input (SLAVE) and output (MASTER).
2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH.
3. tWB is only for the 'Slave' version.
13
6.42
IDT7008S/L
High-Speed 64K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Waveform of BUSY Arbitration Controlled by CE Timing(1,3) (M/S = VIH)
ADDR"A"
ADDRESSES MATCH
and "B"
CE"A"
(2)
tAPS
CE"B"
tBAC
tBDC
BUSY"B"
3198 drw 15
Waveform of BUSY Arbitration Cycle Controlled by Address Match
Timing(1) (M/S = VIH)
ADDR"A"
ADDR"B"
BUSY"B"
ADDRESS "N"
(2)
tAPS
MATCHING ADDRESS "N"
t
BAA
tBDA
3198 drw 16
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. If tAPS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.
3. Refer to Chip Enable Truth Table.
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltageRange(1)
7008X15
7008X20
7008X25
7008X35
Com'l Only
7008X55
Com'l & Ind
Com'l Only
Com'l & Ind
Com'l Only
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
INTERRUPT TIMING
____
____
____
____
____
____
____
____
____
____
t
t
t
t
AS
Address Set-up Time
0
0
0
0
0
ns
ns
ns
WR
INS
INR
Write Recovery Time
Interrupt Set Time
0
0
0
0
0
____
____
____
____
____
15
15
20
20
20
20
25
25
40
40
____
____
____
____
____
Interrupt Reset Time
ns
3198 tbl 15
NOTES:
1. 'X' in part numbers indicates power rating (S or L).
14
IDT7008S/L
High-Speed 64K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Waveform of Interrupt Timing(1,5)
tWC
INTERRUPT SET ADDRESS(2)
ADDR"A"
(3)
(4)
t
AS
tWR
CE"A"
R/W"A"
INT"B"
(3)
tINS
3198 drw 17
t
RC
INTERRUPT CLEAR ADDRESS (2)
ADDR"B"
CE"B"
(3)
t
AS
OE"B"
(3)
tINR
INT"B"
3198 drw 18
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. See Interrupt Truth Table.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
5. Refer to Chip Enable Truth Table.
Truth Table IV — Interrupt Flag(1,4,5)
Left Port
Right Port
R/W
L
A
15L-A0L
R/W
R
A
15R-A0R
Function
CE
L
OE
L
INT
L
CE
X
OE
R
INT
R
L
X
X
X
X
FFFF
X
X
X
X
X
X
L(2)
Set Right INT
Reset Right INT
Set Left INT Flag
Reset Left INT Flag
R
Flag
H(3
X
R
Flag
)
X
X
X
L
L
FFFF
FFFE
X
X
X
X
L(3)
H(2)
L
L
X
L
L
L
FFFE
X
X
X
X
L
3198 tbl 16
NOTES:
1. Assumes BUSYL = BUSYR =VIH.
2. If BUSYL = VIL, then no change.
3. If BUSYR = VIL, then no change.
4. INTL and INTR must be initialized at power-up.
5. Refer to Chip Enable Truth Table.
15
6.42
IDT7008S/L
High-Speed 64K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Truth Table V —Address BUSY
Arbitration(4)
Inputs
Outputs
A
OL-A15L
(1)
(1)
A
OR-A15R
Function
Normal
Normal
Normal
CE
L
CE
R
BUSY
L
BUSY
R
X
H
X
X
X
H
NO MATCH
MATCH
H
H
H
H
H
H
MATCH
Write
L
L
MATCH
(2)
(2)
Inhibit(3)
3198 tbl 17
NOTES:
1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the IDT7008 are
push-pull, not open drain outputs. On slaves the BUSY input internally inhibits writes.
2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address
and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs can not be LOW simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored
when BUSYR outputs are driving LOW regardless of actual logic level on the pin.
4. Refer to Chip Enable Truth Table.
Truth Table VI — Example of Semaphore Procurement Sequence(1,2,3)
Functions
D0
- D7
Left
D0
- D7
Right
Status
No Action
1
1
1
1
0
0
1
1
0
1
1
1
Semaphore free
Left Port Writes "0" to Semaphore
Right Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "1" to Semaphore
Right Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
0
0
1
1
0
1
1
1
0
1
Left port has semaphore token
No change. Right side has no write access to semaphore
Right port obtains semaphore token
No change. Left port has no write access to semaphore
Left port obtains semaphore token
Semaphore free
Right port has semaphore token
Semaphore free
Left port has semaphore token
Semaphore free
3198 tbl 18
NOTES:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT7008.
2. There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0-I/O7). These eight semaphores are addressed by A0-A2.
3. CE = VIH, SEM = VIL to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table.
FunctionalDescription
TheIDT7008providestwoportswithseparatecontrol,addressand (INTL) is asserted when the right port writes to memory location FFFE
I/Opinsthatpermitindependentaccessforreadsorwritestoanylocation (HEX),whereawriteisdefinedasCER=R/WR =VILpertheTruthTable.
inmemory.TheIDT7008hasanautomaticpowerdownfeaturecontrolled TheleftportclearstheinterruptthroughaccessofaddresslocationFFFE
by CE. The CE0 and CE1 control the on-chip power down circuitry that when CEL = OEL = VIL, R/W is a "don't care". Likewise, the right port
permitstherespectiveporttogointoastandbymodewhennotselected interruptflag(INTR)isassertedwhentheleftportwritestomemorylocation
(CEHIGH). Whenaportisenabled, accesstotheentirememoryarray FFFF(HEX)andtocleartheinterruptflag(INTR),therightportmustread
ispermitted.
thememorylocationFFFF. Themessage(8bits)atFFFEorFFFFisuser-
definedsinceitisanaddressableSRAMlocation.Iftheinterruptfunction
isnotused,addresslocationsFFFEandFFFFarenotusedasmailboxes,
butaspartoftherandomaccessmemory.RefertoTableIVfortheinterrupt
operation.
Interrupts
Iftheuserchoosestheinterruptfunction,amemorylocation(mailbox
ormessagecenter)isassignedtoeachport. Theleftportinterruptflag
16
IDT7008S/L
High-Speed 64K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
result in a glitched internal write inhibit signal and corrupted data in the
slave.
BusyLogic
BusyLogicprovidesahardwareindicationthatbothportsoftheRAM
haveaccessedthesamelocationatthesametime.Italsoallowsoneofthe
twoaccessestoproceedandsignalstheothersidethattheRAMis“busy”.
TheBUSYpincanthenbeusedtostalltheaccessuntiltheoperationon
Semaphores
TheIDT7008isanextremelyfastDual-Port64Kx8CMOSStaticRAM
theothersideiscompleted.Ifawriteoperationhasbeenattemptedfrom withanadditional8addresslocationsdedicatedtobinarysemaphoreflags.
thesidethatreceivesaBUSYindication,thewritesignalisgatedinternally TheseflagsalloweitherprocessorontheleftorrightsideoftheDual-Port
topreventthewritefromproceeding.
RAMtoclaimaprivilegeovertheotherprocessorforfunctionsdefinedby
TheuseofBUSYlogicisnotrequiredordesirableforallapplications. thesystemdesigner’ssoftware.Asanexample,thesemaphorecanbe
InsomecasesitmaybeusefultologicallyORtheBUSYoutputstogether usedbyoneprocessortoinhibittheotherfromaccessingaportionofthe
and use any BUSYindication as an interrupt source to flag the event of Dual-Port RAM or any other shared resource.
anillegalorillogicaloperation.IfthewriteinhibitfunctionofBUSYlogicis
The Dual-Port RAM features a fast access time, and both ports are
notdesirable,theBUSYlogiccanbedisabledbyplacingthepartinslave completelyindependentofeachother.Thismeansthattheactivityonthe
modewiththeM/Spin.OnceinslavemodetheBUSYpinoperatessolely leftportinnowayslowstheaccesstimeoftherightport. Bothportsare
asawriteinhibitinputpin.Normaloperationcanbeprogrammedbytying identicalinfunctiontostandardCMOSStaticRAMandcanbereadfrom,
the BUSY pins HIGH. If desired, unintended write operations can be orwrittento,atthesametimewiththeonlypossibleconflictarisingfromthe
prevented to a port by tying the BUSYpin for that port LOW.
simultaneous writing of, or a simultaneous READ/WRITE of, a non-
TheBUSYoutputsontheIDT7008RAMinmastermode,arepush- semaphorelocation.Semaphoresareprotectedagainstsuchambiguous
pulltypeoutputsanddonotrequirepullupresistorstooperate. Ifthese situationsandmaybeusedbythesystemprogramtoavoidanyconflicts
RAMs are being expanded in depth, then the BUSY indication for the inthenon-semaphoreportionoftheDual-PortRAM.Thesedeviceshave
resulting array requires the use of an external AND gate.
anautomaticpower-downfeaturecontrolledbyCE,theDual-PortRAM
enable,andSEM,thesemaphoreenable.TheCEandSEMpinscontrol
on-chip power down circuitry that permits the respective port to go into
standbymodewhennotselected. Thisistheconditionwhichisshownin
Truth Table II where CE and SEM are both HIGH.
A16
CE0
CE0
MASTER
SLAVE
Dual Port RAM
Dual Port RAM
BUSY (L) BUSY (R)
BUSY (L) BUSY (R)
SystemswhichcanbestusetheIDT7008containmultipleprocessors
or controllers and are typically very high-speed systems which are
softwarecontrolledorsoftwareintensive.Thesesystemscanbenefitfrom
aperformanceincreaseofferedbytheIDT7008shardwaresemaphores,
whichprovidealockoutmechanismwithoutrequiringcomplexprogram-
ming.
CE
1
CE1
MASTER
Dual Port RAM
SLAVE
Dual Port RAM
BUSY (L) BUSY (R)
BUSY (L) BUSY (R)
3198 drw 19
Softwarehandshakingbetweenprocessorsoffersthemaximumin
systemflexibilitybypermittingsharedresourcestobeallocatedinvarying
configurations.TheIDT7008doesnotuseitssemaphoreflagstocontrol
anyresourcesthroughhardware,thusallowingthesystemdesignertotal
flexibilityinsystemarchitecture.
An advantage of using semaphores rather than the more common
methodsofhardwarearbitrationisthatwaitstatesareneverincurredin
either processor. This can prove to be a major advantage in very high-
speedsystems.
Figure 3. Busy and chip enable routing for both width and depth
expansion with IDT7008 RAMs.
WidthExpansionBusyLogic
Master/SlaveArrays
WhenexpandinganIDT7008RAMarrayinwidthwhileusingBUSY
logic,onemasterpartisusedtodecidewhichsideoftheRAMsarraywill
receiveaBUSYindication, andtooutputthatindication. Anynumberof
slaves to be addressed in the same address range as the master, use
theBUSYsignalasawriteinhibitsignal. ThusontheIDT7008RAMthe
How the Semaphore Flags Work
Thesemaphorelogicisasetofeightlatcheswhichareindependent
BUSYpinisanoutputifthepartisusedasamaster(M/Spin=VIH),and oftheDual-PortRAM.Theselatchescanbeusedtopassaflag,ortoken,
theBUSYpinisaninputifthepartusedasaslave(M/Spin=VIL)as shown fromoneporttotheothertoindicatethatasharedresourceisinuse.The
in Figure 3.
semaphores provide a hardware assist for a use assignment method
Iftwoormoremasterpartswereusedwhenexpandinginwidth,asplit called“TokenPassingAllocation.”Inthismethod,thestateofasemaphore
decisioncouldresultwithonemasterindicatingBUSYononesideofthe latchisusedasatokenindicatingthatsharedresourceisinuse.Iftheleft
arrayandanothermasterindicatingBUSYononeothersideofthearray. processorwantstousethisresource,itrequeststhetokenbysettingthe
Thiswouldinhibitthewriteoperationsfromoneportforpartofawordand latch.Thisprocessorthenverifiesitssuccessinsettingthelatchbyreading
inhibitthewriteoperationsfromtheotherportfortheotherpartoftheword. it. If it was successful, it proceeds to assume control over the shared
TheBUSYarbitration, onamaster, isbasedonthechipenableand resource.Ifitwasnotsuccessfulinsettingthelatch,itdeterminesthatthe
address signals only. It ignores whether an access is a read or write. In rightsideprocessorhassetthelatchfirst, hasthetokenandisusingthe
a master/slave array, both address and chip enable must be valid long sharedresource. Theleftprocessorcantheneitherrepeatedlyrequest
enoughforaBUSYflagtobeoutputfromthemasterbeforetheactualwrite thatsemaphore’sstatusorremoveitsrequestforthatsemaphoretoperform
pulsecanbeinitiatedwiththeR/Wsignal.Failuretoobservethistimingcan anothertaskandoccasionallyattemptagaintogaincontrolofthetokenvia
17
6.42
IDT7008S/L
High-Speed 64K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
thesetandtestsequence.Oncetherightsidehasrelinquishedthetoken, side during subsequent read. Had a sequence of READ/WRITE been
theleftsideshouldsucceedingainingcontrol. usedinstead,systemcontentionproblemscouldhaveoccurredduringthe
ThesemaphoreflagsareactiveLOW.Atokenisrequestedbywriting gap between the read and write cycles.
azerointoasemaphorelatchandisreleasedwhenthesamesidewrites
aonetothatlatch.
Itisimportanttonotethatafailedsemaphorerequestmustbefollowed
byeitherrepeatedreadsorbywritingaoneintothesamelocation. The
The eight semaphore flags reside within the IDT7008 in a separate reasonforthisiseasilyunderstoodbylookingatthesimplelogicdiagram
memoryspacefromtheDual-PortRAM.This addressspaceisaccessed ofthesemaphoreflaginFigure4.Twosemaphorerequestlatchesfeed
byplacingaLOWinputontheSEMpin(whichactsasachipselectforthe into a semaphore flag. Whichever latch is first to present a zero to the
semaphore flags) and using the other control pins (Address, CE, and semaphoreflagwillforceitssideofthesemaphoreflagLOWandtheother
R/W)astheywouldbeusedinaccessingastandardStaticRAM. Each sideHIGH.Thisconditionwillcontinueuntilaoneiswrittentothesame
oftheflagshasauniqueaddresswhichcanbeaccessedbyeitherside semaphorerequestlatch.Shouldtheotherside’ssemaphorerequestlatch
throughaddresspinsA0–A2.Whenaccessingthesemaphores,noneof havebeenwrittentoazerointhemeantime,thesemaphoreflagwillflip
theotheraddresspinshasanyeffect.
Whenwritingtoasemaphore,onlydatapinD0isused.IfaLOWlevel
L PORT
R PORT
iswrittenintoanunusedsemaphorelocation,thatflagwillbesettoazero
onthatsideandaoneontheotherside(seeTableVI).Thatsemaphore
can now only be modified by the side showing the zero. When a one is
writtenintothesamelocationfromthesameside,theflagwillbesettoa
one for both sides (unless a semaphore request from the other side is
pending)andthencanbewrittentobybothsides.Thefactthattheside
whichisabletowriteazerointoasemaphoresubsequentlylocksoutwrites
fromtheothersideiswhatmakessemaphoreflagsusefulininterprocessor
communications.(Athoroughdiscussionontheuseofthisfeaturefollows
shortly.)Azerowrittenintothesamelocationfromtheothersidewillbe
storedinthesemaphorerequestlatchforthatsideuntilthesemaphoreis
freedbythefirstside.
Whenasemaphoreflagisread,itsvalueisspreadintoalldatabitsso
thataflagthatisaonereadsasaoneinalldatabitsandaflagcontaining
azeroreadsasallzeros.Thereadvalueislatchedintooneside’soutput
registerwhenthatside'ssemaphoreselect(SEM)andoutputenable(OE)
signalsgoactive.Thisservestodisallowthesemaphorefromchanging
stateinthemiddleofareadcycleduetoawritecyclefromtheotherside.
Becauseofthislatch,arepeatedreadofasemaphoreinatestloopmust
cause either signal (SEM or OE) to go inactive or the output will never
change.
AsequenceWRITE/READmustbeusedbythesemaphoreinorder
to guarantee that no system level contention will occur. A processor
requestsaccesstosharedresourcesbyattemptingtowriteazerointoa
semaphorelocation.Ifthesemaphoreisalreadyinuse,thesemaphore
requestlatchwillcontainazero,yetthesemaphoreflagwillappearasone,
afactwhichtheprocessorwillverifybythesubsequentread(seeTable
VI). As an example, assume a processor writes a zero to the left port at
afreesemaphorelocation.Onasubsequentread,theprocessorwillverify
thatithaswrittensuccessfullytothatlocationandwillassumecontrolover
the resource in question. Meanwhile, if a processor on the right side
attemptstowriteazerotothesamesemaphoreflagitwillfail, aswillbe
verifiedbythefactthataonewillbereadfromthatsemaphoreontheright
SEMAPHORE
REQUEST FLIP FLOP
SEMAPHORE
REQUEST FLIP FLOP
0
0
D
D
D
D
Q
Q
WRITE
WRITE
SEMAPHORE
READ
SEMAPHORE
,
READ
3198 drw 20
Figure 4. IDT7008 Semaphore Logic
overtotheothersideassoonasaoneiswrittenintothefirstside’srequest
latch.Thesecondside’sflagwillnowstayLOWuntilitssemaphorerequest
latchiswrittentoaone.Fromthisitiseasytounderstandthat,ifasemaphore
is requested and the processor which requested it no longer needs the
resource, the entire system can hang up until a one is written into that
semaphorerequestlatch.
The critical case of semaphore timing is when both sides request a
single token by attempting to write a zero into it at the same time. The
semaphorelogicisspeciallydesignedtoresolvethisproblem.Ifsimulta-
neousrequestsaremade,thelogicguaranteesthatonlyonesidereceives
thetoken.Ifonesideisearlierthantheotherinmakingtherequest,thefirst
sidetomaketherequestwillreceivethetoken.Ifbothrequestsarriveat
thesametime,theassignmentwillbearbitrarilymadetooneportorthe
other.
One caution that should be noted when using semaphores is that
semaphoresalonedonotguaranteethataccesstoaresourceissecure.
Aswithanypowerfulprogrammingtechnique,ifsemaphoresaremisused
or misinterpreted, a software error can easily happen.
Initializationofthesemaphoresisnotautomaticandmustbehandled
viatheinitializationprogramatpower-up.Sinceanysemaphorerequest
flagwhichcontainsazeromustberesettoaone,allsemaphoresonboth
sidesshouldhaveaonewrittenintothematinitializationfrombothsides
to assure that they will be free when needed.
18
IDT7008S/L
High-Speed 64K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
OrderingInformation
XXXXX
A
999
A
A
A
A
Device Power Speed Package
Type
Process/
Temperature
Range
Blank Tube or Tray
8
Tape and Reel
Blank
I(1)
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
G(2)
Green
PF
G
J
100-pin TQFP (PN100)
84-pin PGA (G84)
84-pin PLCC (J84)
Commercial Only
Commercial & Industrial
Commercial Only
Commercial Only
Commercial & Industrial
15
20
25
35
55
Speed in nanoseconds
S
L
Standard Power
Low Power
7008 512K (64K x 8) Dual-Port RAM
3198 drw 21
NOTES:
1. IndustrialtemperaturerangeisavailableonselectedTQFPpackagesinstandardpower.Forotherspeeds,packagesandpowerscontactyoursalesoffice.
2. Green parts available. For specific speeds, packages and powers contact your local sales office.
LEADFINISH(SnPb)partsareinEOLprocess.ProductDiscontinuationNotice-PDN#SP-17-02
DatasheetDocumentHistory
01/06/99:
Initiated datasheet document history
Convertedtonewformat
Cosmeticandtypographicalcorrections
Addedadditionalnotestopinconfigurations
Changeddrawingformat
Replaced IDT logo
Increasedstoragetemperatureparameter
ClarifiedTA parameter
Pages 2 and 3
06/03/99:
11/10/99:
05/08/99:
Page 6
Page 7
DCElectricalparameters–changedwordingfrom"open"to"disabled"
Changed±200mVto0mVinnotes
07/26/04:
Page 2 - 4
Page 6
Addeddaterevisionforpinconfigurations
UpdatedCapacitancetable
Page 7
Added15nscommercialspeedgradetotheDCElectricalCharacteristics
Added 20nsIndustrialtempforlowpower toDCElectricalCharacteristics
Page 9, 12 & 14 Added15nscommercialspeedgrade toACElectricalCharacteristics
Added20nsIndustrialtempforlowpowertoACElectricalCharacteristicsforRead,Write,BusyandInterrupt
Page 19
Page 1 & 19
AddedCommercialfor15nsandIndustrialtempto20nsinorderinginformation
Replaced old TM logo with new TM logo
19
6.42
IDT7008S/L
High-Speed 64K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
DatasheetDocumentHistory(con't)
04/03/06:
Page 1
Addedgreenavailabilitytofeatures
Page 19
Page 19
Page 19
Addedgreenindicatortoorderinginformation
Removed "IDT" from orderable part number
Added Tape & Reel to Ordering Information
10/21/08:
10/02/14:
Page 2, 3, 4 & 19 The package codes for PN100-1, G108-1 & J84-1 changed to PN100, G108 & J84 respectively to
matchstandardpackagecodes
04/06/16:
Page 2
Changed diagram for the J84 pin configuration by rotating package pin labels and pin
numbers 90 degrees clockwise to reflect pin1 orientation and added pin 1 dot at pin 1
Removed J84 chamfer and aligned the top and bottom pin labels in the standard direction
Changed diagram for the PN100 pin configuration by rotating package pin labels and pin
numbers 90 degrees counter clockwise to reflect pin 1 orientation and added pin 1 dot at pin 1
AddedtheIDTlogo,changedthetext tobeinalignment withnewdiagrammarkingspecs,removeddate
fromallpinconfigurationsandupdatedfootnotereferencesfortheJ84&thePN100pinconfigurations
Military grade removed from Absolute Max and Max Operating tables
Page 3
Page 6
Page 7, 9, 12 & 14 Military grade removed from all DC Elec & all AC Elec tables for all speeds
Page 19
MilitarygraderemovedfromOrderingInformation
ProductDiscontinuationNotice-PDN#SP-17-02
Last time buy expires June 15, 2018
03/06/18:
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
for Tech Support:
408-284-2794
DualPortHelp@idt.com
800-345-7015 or 408-284-8200
fax: 408-284-2775
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
20
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