7014S25JG8 [IDT]
HIGH-SPEED 4K x 9DUAL-PORT STATIC RAM;
| 型号： | 7014S25JG8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | HIGH-SPEED 4K x 9DUAL-PORT STATIC RAM |
| 文件： | 总10页 (文件大小：92K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT7014S
HIGH-SPEED
4K x 9DUAL-PORT
STATIC RAM
LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018
Description:
Features:
◆
The IDT7014 is a high-speed 4K x 9 Dual-Port Static RAM designed
to be used in systems where on-chip hardware port arbitration is not
needed.Thispart lendsitselftohigh-speedapplicationswhichdonotrely
onBUSYsignalstomanagesimultaneousaccess.
True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
High-speed access
◆
– Commercial: 12/15/20/25ns (max.)
– Industrial: 20ns (max.)
Standard-power operation
The IDT7014 provides two independent ports with separate control,
address,andI/Opinsthatpermitindependent,asynchronousaccessfor
readsorwritestoanylocationinmemory.Seefunctionaldescription.
The IDT7014 utilitizes a 9-bit wide data path to allow for parity at the
user's option. This feature is especially useful in data communication
applications where it is necessary to use a parity bit for transmission/
receptionerrorchecking.
Fabricatedusingahigh-performance technology, theseDual-Ports
typicallyoperateononly750mWofpoweratmaximumaccesstimesas
fastas12ns.
◆
– IDT7014S
Active: 750mW (typ.)
Fully asynchronous operation from either port
TTL-compatible; single 5V (±10%) power supply
Available in 52-pin PLCC and a 64-pin TQFP
◆
◆
◆
◆
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Green parts available, see ordering information
◆
The IDT7014 is packaged in a 52-pin PLCC and a 64-pin thin quad
flatpack,(TQFP).
FunctionalBlockDiagram
R/WR
R/W
L
OER
OEL
I/O
CONTROL
I/O
CONTROL
I/O0R- I/O8R
I/O0L- I/O8L
ADDRESS
DECODER
ADDRESS
DECODER
MEMORY
ARRAY
A0R- A11R
A0L- A11L
2528 drw 01
OCTOBER 2017
1
DSC 2528/19
©2017 Integrated Device Technology, Inc.
IDT7014S
High-Speed 4K x 9 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
PinConfiguration(1,2,3)
INDEX
7
6 5 4 3 2
5251 50 4948 47
46
A
A
6L
7L
1
8
9
A
A
A
A
A
7R
45
44
43
42
41
40
39
38
37
36
35
34
8R
A
A
8L
9L
10
11
12
13
14
15
16
17
18
19
20
9R
10R
11R
IDT 7014J
J52(4)
A
A
10L
11L
OE
GND
R/W
R
OE
L
52-Pin
PLCC
Top View(5)
VCC
R
R/W
L
GND
I/O8R
I/O7R
I/O6R
I/O5R
GND
I/O8L
I/O7L
I/O6L
21 2223 24 2526 27 2829 30 3132 33
2528 drw 02
46 45 44 43 424140 39383736353433
4847
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
A
A
A
A
A
A
N/C
N/C
N/C
N/C
A
A
A
A
A
A
5R
4R
3R
2R
1R
0R
I/O5R
I/O4R
VCC
I/O3R
I/O2R
I/O1R
I/O0R
GND
GND
I/O0L
I/O1L
I/O2L
I/O3L
I/O4L
25
24
7014
PN64(4)
23
22
21
20
19
18
17
0L
1L
2L
3L
4L
5L
VCC
I/O5L
1 2 3 4 5 6 7 8 9 10
1112 131415
16
2528 drw 03
INDEX
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. J52-1 package body is approximately .75 in x .75 in. x .17 in.
PN64-1 package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate the orientation of the actual part-marking
2
IDT7014S
High-Speed 4K x 9 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AbsoluteMaximumRatings(1)
MaximumOperatingTemperature
andSupplyVoltage(1,2)
Symbol
Rating
Commercial
& Industrial
Unit
Grade
Ambient
GND
Vcc
(2)
Temperature
V
TERM
Terminal Voltage
with Respect
to GND
-0.5 to +7.0
V
Commercial
Industrial
0OC to +70OC
0V
0V
5.0V
5.0V
+
+
10%
10%
-40OC to +85OC
(2)
V
TERM
BIAS
Terminal Voltage
-0.5 to +VCC
-55 to +125
V
2528 tbl 02
Temperature
Under Bias
oC
T
NOTES:
1. This is the parameter TA. This is the "instant on" case temperature.
Storage
-65 to +150
50
oC
T
STG
Temperature
IOUT
DC Output
Current
mA
RecommendedDCOperating
Conditions
2528 tbl 01
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VTERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of VTERM > Vcc + 10%.
Symbol
Parameter
Min.
Typ.
Max. Unit
V
CC
Supply Voltage
4.5
5.0
5.5
0
V
V
V
GND
Ground
0
0
V
IH
IL
Input High Voltage
Input Low Voltage
2.2
6.0(2)
0.8
____
-0.5(1)
V
____
V
2528 tbl 03
NOTES:
1. VIL > -1.5V for pulse width less than 10ns.
2. VTERM must not exceed Vcc + 10%.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1) (VCC = 5.0V ± 10%)
7014S
Symbol
|ILI
|ILO
Parameter
Input Leakage Current
Test Conditions
CC = 5.5V, VIN = 0V to VCC
OUT = 0V to VCC
Min.
Max.
Unit
µA
µA
V
___
|
V
V
10
10
___
___
|
Output Leakage Current
Output Low Voltage
Output High Voltage
V
OL
OH
I
OL = +4mA
0.4
___
V
I
OH = -4mA
2.4
V
2528 tbl 04
NOTE:
1. At VCC < 2.0V input leakages are undefined.
3
6.42
IDT7014S
High-Speed 4K x 9 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(VCC = 5V ± 10%)
7014S12
Com'l Only
7014S15
Com'l Only
Symbol
Parameter
Test Condition
Outputs Open
Version
COM'L
IND
Typ. Max
160 250
Typ.
160
Max
250
Unit
ICC
Dynamic Operating
mA
S
S
(1)
Current
f = fMAX
____
____
____
____
(Both Ports Active)
2528 tbl 05a
7014S20
Com'l & Ind
7014S25
Com'l Only
Symbol
Parameter
Test Condition
Outputs Open
Version
Typ.
155
155
Max
245
260
Typ. Max.
150 240
Unit
ICC
Dynamic Operating
Current
(Both Ports Active)
mA
COM'L
IND
S
S
(1)
f = fMAX
____
____
2528 tbl 05b
NOTES:
1. At f = fmax, address inputs are cycling at the maximum read cycle of 1/tRC using the "AC Test Conditions" input levels of GND to 3V.
5V
AC Test Conditions
5V
Input Pulse Levels
GND to 3.0V
3ns Max.
893Ω
893Ω
5pF*
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
1.5V
DATAOUT
DATAOUT
1.5V
30pF
347Ω
347Ω
Figures 1,2 and 3
,
2528 tbl 06
2528 drw 04
2528 drw 05
Figure 1. AC Output Test Load.
Figure 2. Output Test Load
(for tHZ, tWZ, and tOW)
Capacitance(1)
*Includingscopeandjig.
(TA = +25°C, f = 1.0MHz) TQFP Package Only
Symbol
Parameter
Input Capacitance
Output Capacitance
Conditions(2)
IN = 3dV
OUT = 3dV
Max. Unit
8
10pF is the I/O capacitance
of this device, and 30pF is the
AC Test Load Capacitance
CIN
V
9
pF
7
6
COUT
V
10
pF
2528 tbl 07
5
4
NOTES:
t
AA
1. This parameter is determined by device characteristics but is not production
tested.
2. 3dv references the interpolated capacitance when the input and output signals
swith from 0V to 3V or from 3V to 0V.
(Typical, ns)
3
2
1
0
20 40 60 80 100 120 140 160 180 200
Capacitance (pF)
-1
,
2528 drw 06
Figure 3. Typical Output Derating (Lumped Capacitive Load).
4
IDT7014S
High-Speed 4K x 9 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltage
7014S12
Com'l Only
7014S15
Com'l Only
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
READ CYCLE
____
____
t
RC
AA
AOE
OH
LZ
HZ
Read Cycle Time
12
15
ns
ns
ns
ns
ns
____
____
t
Address Access Time
Output Enable Access Time
Output Hold from Address Change
Output Low-Z Time(1,2)
12
15
____
____
t
8
8
____
____
t
3
3
____
____
t
3
3
Output High-Z Time(1,2)
7
7
ns
____
____
t
2528 tbl 08a
7014S20
Com'l & Ind
7014S25
Com'l Only
Symbol
READ CYCLE
Parameter
Min.
Max.
Min.
Max.
Unit
____
____
t
RC
AA
AOE
OH
LZ
HZ
Read Cycle Time
20
25
ns
ns
ns
ns
ns
____
____
t
Address Access Time
Output Enable Access Time
Output Hold from Address Change
Output Low-Z Time(1,2)
20
25
____
____
t
10
12
____
____
t
3
3
____
____
t
3
3
Output High-Z Time(1,2)
9
11
ns
____
____
t
2528 tbl 08b
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is determined by device characterization, but is not production tested.
5
6.42
IDT7014S
High-Speed 4K x 9 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Read Cycle No. 1, Either Side(1,2)
tRC
ADDRESS
tAA
tOH
tOH
DATAOUT
PREVIOUS DATA VALID
DATA VALID
2528 drw 07
Timing Waveform of Read Cycle No. 2, Either Side(1, 3)
tAOE
OE
tHZ
tLZ
VALID DATA
DATAOUT
2528 drw 08
NOTES:
1. R/W = VIH for Read Cycles.
2. OE = VIL.
3. Addresses valid prior to OE transition LOW.
Timing Waveform of Write with Port-to-Port Read(1,2)
tWC
ADDR"A"
MATCH
tWP
R/W"A"
tDW
tDH
DATAIN "A"
ADDR"B"
VALID
MATCH
tWDD
DATAOUT "B"
VALID
tDDD
2528 drw 09
NOTES:
1. R/W"B" = VIH, read cycle pass through.
2. All timing is the same for left and right ports. Port "A" may be either left or right port. Port "B" is opposite from port "A".
6
IDT7014S
High-Speed 4K x 9 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltage
7014S12
Com'l Only
7014S15
Com'l Only
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
____
____
____
____
____
____
____
____
____
____
____
____
t
WC
AW
AS
WP
WR
DW
HZ
DH
WZ
OW
WDD
DDD
Write Cycle Time
12
10
0
15
14
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
Address Valid to End-of-Write
Address Set-up Time
Write Pulse Width
t
t
10
1
12
1
t
Write Recovery Time
Data Valid to End-of-Write
Output High-Z Time(1,2)
Data Hold Time(3)
t
8
10
____
____
t
7
7
____
____
t
0
0
(1,2)
____
____
t
Write Enable to Output in High-Z
Output Active from End-of-Write(1, 2,3)
Write Pulse to Data Delay(4)
7
7
____
____
t
0
0
____
____
t
25
22
30
25
Write Data Valid to Read Data Delay(4)
ns
____
____
t
2528 tbl 09a
7014S20
Com'l & Ind
7014S25
Com'l Only
Symbol
WRITE CYCLE
Parameter
Min.
Max.
Min.
Max.
Unit
____
____
____
____
____
____
____
____
____
____
____
____
t
WC
AW
AS
WP
WR
DW
HZ
DH
WZ
OW
WDD
DDD
Write Cycle Time
20
15
0
25
20
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
Address Valid to End-of-Write
Address Set-up Time
Write Pulse Width
t
t
15
2
20
2
t
Write Recovery Time
Data Valid to End-of-Write
Output High-Z Time(1,2)
Data Hold Time(3)
t
12
15
____
____
t
9
11
____
____
t
0
0
(1,2)
____
____
t
Write Enable to Output in High-Z
Output Active from End-of-Write(1, 2,3)
Write Pulse to Data Delay(4)
9
11
____
____
t
0
0
____
____
t
40
30
45
35
Write Data Valid to Read Data Delay(4)
ns
____
____
t
2528 tbl 09b
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage
and temperature, the actual tDH will always be smaller than the actual tOW.
4. Port-to-port delay through RAM cells from writing port to reading port, refer to “Timing Waveform of Write With Port-to-Port Read”.
7
6.42
IDT7014S
High-Speed 4K x 9 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write Cycle(1,2,3,4,5)
ADDRESS
OE
tAW
(5)
t
AS
tWP
tWR
R/W
(4)
(4)
tWZ
tOW
tHZ
DATAOUT
(3)
(3)
tDW
tDH
DATAIN
2528 drw 10
NOTES:
1. R/W must be HIGH during all address transitions.
2. tWR is measured from R/W going HIGH to the end of write cycle.
3. During this period, the I/O pins are in the output state, and input signals must not be applied.
4. Transition is measured 0mV from the Low or High-impedance voltage with the Output Test Load (Figure 2).
5. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be
placed on the bus for the required tDW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as
the specified tWP.
Truth Table I – Read/Write Control
FunctionalDescription
The IDT7014 provides two ports with separate control, address,
and I/O pins that permit independent access for reads or writes to
any location in memory. It lacks the chip enable feature of CMOS Dual
Ports,thusitoperatesinactivemodeassoonaspowerisapplied.Each
porthasitsownOutputEnablecontrol(OE).Inthereadmode,theport’s
OEturnsontheoutputdriverswhensetLOW. Theuserapplicationshould
avoidsimultaneouswriteoperationstothesamememorylocation.There
isnoon-chiparbitrationcircuitrytoresolvewritepriorityandpartialdata
frombothportsmaybewritten.READ/WRITEconditionsareillustrated
in Table 1.
Left or Right Port(1)
R/W OE
D0-8
Function
L
H
X
X
L
DATAIN Data written into memory
DATAOUT Data in memory output on port
H
Z
High-impedance outputs
2528 tbl 10
NOTE:
1. AOL - A11L is not equal to AOR - A11R.
'H' = HIGH,'L' = LOW, 'X' = Don’t Care, and 'Z' = HIGH Impedance.
8
IDT7014S
High-Speed 4K x 9 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
OrderingInformation
XXXX
A
999
A
A
A
A
Device Type Power Speed Package
Process/
Temperature
Range
Blank Tube or Tray
8
Tape and Reel
Blank
I(1)
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
G(2)
Green
64-pin TQFP (PN64)
52-pin PLCC (J52)
PF
J
Commercial Only
Commercial Only
Commercial & Industrial
Commercial Only
12
15
20
25
Speed in nanoseconds
S
Standard Power
7014
36K (4K x 9-Bit) Dual-Port RAM
NOTES:
2528 drw 11
1. Industrial temperature: for other speeds, packages and powers contact your sales office.
2. Greenpartsavaliable.Forspecificspeeds,packagesandpowerscontactyourlocalsalesoffice.
LEADFINISH(SnPb)partsareinEOLprocess.ProductDiscontinuationNotice-PDN#SP-17-02
DatasheetDocumentHistory
01/06/99:
Initiateddatasheetdocumenthistory
Converted to new format
Cosmetic and typographical corrections
Page 2
Page 1
Added additional notes to pin configurations
Changed drawing format
Corrected DSC number
Added Industrial Temperature Ranges and deleted corresponding notes
Replaced IDT logo
06/03/99:
03/10/00:
Page 1
Made corrections to drawing
Changed ±200mV to 0mV in notes
Made changes to drawings
Increased storage temperature parameter
Clarified TA parameter
Page 6
Page 3
05/19/00:
10/16/01:
Page 2
Added date revision for pin configuration
Pages 4, 5 & 7 Removed Industrial temp values and column headings for 15 & 25ns speeds from
DC and AC Electrical Characteristics
Page 9
Removed Industrial temp offering from 15 & 25ns ordering information
Added Industrial temp footnote to ordering information
Replaced TM logo with ® logo
Pages 1 & 9
Page 1
04/04/06:
Added green availability to features
Page 9
Page 9
Page 9
Page 2 & 9
Added green indicator to ordering information
Removed "IDT" from orderable part number
Added Tape and Reel to Ordering Information
The package codes PN84-1 & J52-1 changed to PN84 & J52 respectively to match standard
package codes
12/11/08:
08/18/14:
9
6.42
IDT7014S
High-Speed 4K x 9 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
DatasheetDocumentHistory(con't)
03/16/16:
Page 2
Changed diagram for the PN64 pin configuration by rotating package pin labels and pin
numbers90degreescounterclockwisetoreflectpin1orientationandaddedpin1dotatpin1
RemovedthePN64chamferandalignedthetopandbottompinlabelsinthestandarddirection
Added the IDT logo to the PN64 pin configurations and changed the text to be in
alignment with new diagram marking specs
Removedthedaterevisionindicatorforeachpinconfiguration
UpdatedfootnotereferencesforPN64pinconfiguration
Figuire3TypicalOutputDeratingGraph,correctedatypo
Page 4
ProductDiscontinuationNotice-PDN#SP-17-02
Last time buy expires June 15, 2018
10/10/17:
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
for Tech Support:
408-284-2794
DualPortHelp@idt.com
800-345-7015or408-284-8200
fax:408-284-2775
www.idt.com
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
10
相关型号：
7014S25JI
Dual-Port SRAM, 4KX9, 25ns, CMOS, PQCC52, 0.750 X 0.750 INCH, 0.170 INCH HEIGHT, PLASTIC, LCC-52
IDT
7014S25PFG8
Dual-Port SRAM, 4KX9, 25ns, CMOS, PQFP64, 14 X 14 MM, 1.40 MM HEIGHT, GREEN, TQFP-64
IDT
©2020 ICPDF网 联系我们和版权申明