7015S35JGB8 [IDT]
Dual-Port SRAM, 8KX9, 35ns, CMOS, PQCC68, 0.95 X 0.95 INCH, 0.17 INCH HEIGHT, GREEN, PLASTIC, LCC-68;
| 型号： | 7015S35JGB8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Dual-Port SRAM, 8KX9, 35ns, CMOS, PQCC68, 0.95 X 0.95 INCH, 0.17 INCH HEIGHT, GREEN, PLASTIC, LCC-68 静态存储器 内存集成电路 |
| 文件： | 总21页 (文件大小：308K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT7015S/L
HIGH-SPEED
8K x 9 DUAL-PORT
STATIC RAM
Features:
◆
◆
M/S = VIH for BUSY output flag on Master
M/S = VIL for BUSY input on Slave
Busy and Interrupt Flag
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
TTL-compatible, single 5V (±10%) power supply
Available in ceramic 68-pin PGA, 68-pin PLCC, and an 80-
pin TQFP
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
High-speed access
◆
◆
◆
◆
– Commercial:12/15/17/20/25/35ns(max.)
– Industrial: 20ns (max.)
– Military:20/25/35ns(max.)
Low-power operation
◆
◆
◆
◆
– IDT7015S
Active:750mW(typ.)
Standby: 5mW (typ.)
– IDT7015L
◆
◆
Active:750mW(typ.)
Standby: 1mW (typ.)
Green parts available, see ordering information
◆
IDT7015 easily expands data bus width to 18 bits or more
using the Master/Slave select when cascading more than
one device
FunctionalBlockDiagram
OEL
OER
CER
CEL
R/WR
R/W
L
I/O0L- I/O8L
I/O0R-I/O8R
I/O
I/O
Control
Control
BUSYL(1,2)
(1,2)
BUSY
R
A
12L
A
12R
0R
Address
Decoder
MEMORY
ARRAY
Address
Decoder
A
A
0L
13
13
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE
OE
R/W
L
CE
OE
R/W
R
R
L
R
L
SEM
R
SEM
L
M/S
(2)
(2)
INTL
INTR
2954 drw 01
NOTES:
1. In MASTER mode: BUSY is an output and is a push-pull driver
In SLAVE mode: BUSY is input.
2. BUSY outputs and INT outputs are non-tri-stated push-pull drivers.
AUGUST2014
1
DSC 2954/9
©2014 Integrated Device Technology, Inc.
IDT7015S/L
High-Speed 8K x 9 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Description:
The IDT7015 is a high-speed 8K x 9 Dual-Port Static RAM. The featurecontrolledbyCEpermitstheon-chipcircuitryofeachporttoenter
IDT7015 is designed to be used as a stand-alone Dual-Port RAM or as a very low standby power mode.
acombinationMASTER/SLAVEDual-PortRAMfor18-bit-or-moreword
FabricatedusingIDT’sCMOShigh-performancetechnology,these
systems.UsingtheIDTMASTER/SLAVEDual-PortRAMapproachin18- devices typically operate on only 750mW of power.
bitorwidermemorysystemapplicationsresultsinfull-speed,error-free
operationwithouttheneedforadditionaldiscretelogic.
TheIDT7015ispackagedinaceramic68-pinPGA, a64-pinPLCC
and an 80-pinTQFP (Thin Quad Flatpack). Military grade product is
This device provides two independent ports with separate control, manufactured in compliance with the latest revision of MIL-PRF-
address,andI/Opinsthatpermitindependent,asynchronousaccessfor 38535QML,makingitideallysuitedtomilitarytemperatureapplications
reads or writes to any location in memory. An automatic power down demandingthehighestlevelofperformanceandreliability.
PinConfigurations(1,2,3)
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. Package body is approximately .95 in x .95 in x .17 in.
4. This package code is used to reference the package diagram.
5. This text does not imply orientation of Part-marking.
PinNames
Left Port
Right Port
Names
Chip Enable
CE
R/W
OE
L
CE
R/W
OE
R
L
R
Read/Write Enable
Output Enable
Address
L
R
A
0L - A12L
A0R - A12R
I/O0L - I/O8L
SEM
INT
BUSY
I/O0R - I/O8R
SEM
INT
BUSY
M/S
Data Input/Output
Semaphore Enable
Interrupt Flag
Busy Flag
L
R
L
R
L
R
Master or Slave Select
Power
V
CC
GND
Ground
2954 tbl 01
6.42
2
IDT7015S/L
High-Speed 8K x 9 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Pin Configurations(1,2,3) (con't.)
NOTES:
1. All Vcc must be connected to power supply.
2. All GND must be connected to ground supply.
3. PN80 package body is approximately
14mm x 14mm x 1.4mm.
G68-1 package body is approximately
1.18 in x 1.18 in x .16 in.
4. This package code is used to reference the package diagram.
5. This text does not imply orientation of Part-marking.
6.342
IDT7015S/L
High-Speed 8K x 9 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Truth Table I: Non-Contention Read/Write Control
Inputs(1)
Outputs
R/W
X
I/O0-8
Mode
CE
H
L
OE
X
SEM
H
High-Z
DATAIN
DATAOUT
High-Z
Deselected: Power-Down
Write to Memory
L
X
H
L
H
L
H
Read Memory
X
X
H
X
Outputs Disabled
2954 tbl 02
NOTE:
1. Condition: A0L — A12L = A0R — A12R
Truth Table II: Semaphore Read/Write CONTROL(1)
Inputs(1)
Outputs
R/W
H
I/O0-8
Mode
CE
H
OE
L
SEM
L
L
L
DATAOUT
Read Semaphore Flag Data Out (I/O0-8
Write I/O into Semaphore Flag
Not Allowed
)
H
X
DATAIN
0
↑
____
L
X
X
2954 tbl 03
NOTE:
1. There are eight semaphore flags written to via I/O0 and read from all I/Os (I/O0 - I/O8). These eight semaphores are addressed by A0 - A2.
AbsoluteMaximumRatings(1)
MaximumOperating
TemperatureandSupplyVoltage(1)
Symbol
Rating
Commercial
& Industrial
Military
Unit
Grade
Ambient
Temperature
GND
Vcc
(2)
V
TERM
Terminal Voltage
with Respect
to GND
-0.5 to +7.0
-0.5 to +7.0
V
Military
-55OC to +125OC
0OC to +70OC
0V
0V
0V
5.0V
+
+
+
10%
Commercial
Industrial
5.0V
5.0V
10%
Temperature
Under Bias
-55 to +125
-65 to +150
50
-65 to +135
-65 to +150
50
oC
oC
T
BIAS
-40OC to +85OC
10%
Storage
Temperature
TSTG
2954 tbl 05
NOTES:
1. This is the parameter TA. There is the "instant on" case temperature.
DC Output
Current
mA
IOUT
2954 tbl 04
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS
RecommendedDCOperating
Conditions
may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect
reliability.
Symbol
Parameter
Min.
Typ. Max. Unit
V
CC
Supply Voltage
4.5
5.0
5.5
0
V
V
V
2. VTERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of VTERM > Vcc + 10%.
GND
Ground
0
0
V
V
IH
IL
Input High Voltage
Input Low Voltage
2.2
6.0(2)
0.8
____
-0.5(1)
V
____
2954 tbl 06
NOTES:
1. VIL > -1.5V for pulse width less than 10ns.
2. VTERM must not exceed Vcc + 10%.
6.42
4
IDT7015S/L
High-Speed 8K x 9 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Capacitance(1)
(TA = +25°C, f = 1.0mhz, for TQFP Package)
Symbol
Parameter
Input Capacitance
Output Capacitance
Conditions(2 )
IN = 3dV
OUT = 3dV
Max. Unit
CIN
V
9
pF
COUT
V
10
pF
2954 tbl 07
NOTES:
1. This parameter is determined by device characteristics but is not
production tested.
2. 3dV references the interpolated capacitance when the input and
output signals switch from 0V to 3V or from 3V to 0V .
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VCC = 5.0V ± 10%)
7015S
7015L
Symbol
|ILI
|ILO
Parameter
Input Leakage Current(1)
Output Leakage Current
Output Low Voltage
Test Conditions
Min.
Max.
10
Min.
Max.
Unit
µA
µA
V
___
___
|
V
CC = 5.5V, VIN = 0V to VCC
5
5
___
___
___
___
|
10
CE = VIH, VOUT = 0V to VCC
OL = +4mA
OH = -4mA
V
OL
OH
I
0.4
0.4
___
___
V
Output High Voltage
I
2.4
2.4
V
2954 tbl 08
NOTE:
1. At Vcc < 2.0V, Input leakages are undefined.
OutputLoadsand
AC Test Conditions
Input Pulse Levels
GND to 3.0V
3ns Max.
1.5V
Input Rise/Fall Times(1)
Input Timing Reference Levels
Output Reference Levels
Output Load
1.5V
Figures 1 and 2
2954 tbl 09
5V
5V
893Ω
893Ω
DATAOUT
BUSY
INT
DATAOUT
5pF
30pF
347Ω
347Ω
*
2954 drw 06
2954 drw 05
Figure 1. AC Output Test Load
Figure 2. Output Test Load
(For tLZ, tHZ, tWZ, tOW)
*Including scope and jig.
6.542
IDT7015S/L
High-Speed 8K x 9 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1) (con't.) (VCC = 5.0V ± 10%)
7015X12
Com'l Only
7015X15
Com'l Only
7015X17
Com'l Only
Symbol
Parameter
Test Condition
Version
COM'L
Typ.(2)
Max.
Typ.(2)
Max.
Typ.(2)
Max.
Unit
ICC
Dynamic Operating Current
(Both Ports Active)
S
L
170
170
325
275
170
170
310
260
170
170
310
260
mA
CE = VIL, Outputs Disabled
SEM = VIH
(3)
f = fMAX
____
____
____
____
____
____
____
____
____
____
____
____
MIL. &
IND.
S
L
I
SB1
Standby Current
(Both Ports - TTL
Level Inputs)
COM'L
S
L
25
25
70
60
25
25
60
50
25
25
60
50
mA
mA
mA
mA
CE
SEM
f = fMAX
R
= CE
L
= VIH
= VIH
R
= SEM
L
(3)
____
____
____
____
____
____
____
____
____
____
____
____
MIL. &
IND.
S
L
ISB2
Standby Current
(One Port - TTL
Level Inputs)
COM'L
S
L
105
105
200
170
105
105
190
160
105
109
190
160
CE"A" = VIL and
(5)
CE"B" = VIH
, Active Port
(3)
Outputs Disabled, f=fMAX
____
____
____
____
____
____
____
____
____
____
____
____
MIL. &
IND.
S
L
SEMR
= SEM
L
= VIH
and
ISB3
Full Standby Current (Both
Ports - All
CMOS Level Inputs)
Both Ports CE
L
COM'L
S
L
1.0
0.2
15
5
1.0
0.2
15
5
1.0
0.2
15
5
CE
R
> VCC - 0.2V
IN > VCC - 0.2V or
IN < 0.2V, f = 0(4)
= SEM >VCC - 0.2V
V
V
____
____
____
____
____
____
____
____
____
____
____
____
MIL. &
IND.
S
L
SEM
R
L
ISB4
Full Standby Current
(One Port - All
CMOS Level Inputs)
COM'L
S
L
100
100
180
150
100
100
170
140
100
100
170
140
CE"A" < 0.2V and
CE"B" > VCC - 0.2V(5)
SEM
R
= SEM
L
>VCC - 0.2V
____
____
____
____
____
____
____
____
____
____
____
____
MIL. &
IND.
S
L
V
V
IN > VCC - 0.2V or
IN < 0.2V, Active Port
Outputs Disable d, f = fMAX
(3)
2954 tbl 10
7015X20
Com'l, Ind
& Military
7015X25
Com'l &
Military
7015X35
Com'l &
Military
Symbol
Parameter
Test Condition
Version
Typ.(2)
Max.
Typ.(2)
Max.
Typ.(2)
Max.
Unit
ICC
Dynamic Operating Current
(Both Ports Active)
COM'L
S
L
160
160
290
240
155
155
265
220
150
150
250
210
mA
CE = VIL, Outputs Disabled
SEM = VIH
(3)
f = fMAX
MIL. &
IND.
S
L
160
160
380
310
155
155
340
280
150
150
300
250
I
SB1
Standby Current
(Both Ports - TTL
Level Inputs)
COM'L
S
L
20
20
60
50
16
16
60
50
13
13
60
50
mA
mA
mA
mA
CE
SEM
f = fMAX
R
= CE
L
= VIH
= VIH
R
= SEM
L
(3)
MIL. &
IND.
S
L
20
20
80
65
16
16
80
65
13
13
80
65
ISB2
Standby Current
(One Port - TTL
Level Inputs)
COM'L
S
L
95
95
180
150
90
90
170
140
85
85
155
130
CE"A" = VIL and
(5)
CE"B" = VIH
, Active Port
(3)
Outputs Disabled, f=fMAX
MIL. &
IND.
S
L
95
95
240
210
90
90
215
180
85
85
190
160
SEMR
= SEM
L
= VIH
and
ISB3
Full Standby Current (Both
Ports - All
CMOS Level Inputs)
Both Ports CE
L
COM'L
S
L
1.0
0.2
15
5
1.0
0.2
15
5
1.0
0.2
15
5
CE
R
> VCC - 0.2V
IN > VCC - 0.2V or
IN < 0.2V, f = 0(4)
= SEM >VCC - 0.2V
V
V
MIL. &
IND.
S
L
1.0
0.2
30
10
1.0
0.2
30
10
1.0
0.2
30
10
SEM
R
L
ISB4
Full Standby Current
(One Port - All
CMOS Level Inputs)
COM'L
S
L
90
90
155
130
85
85
145
120
80
80
135
110
CE"A" < 0.2V and
CE"B" > VCC - 0.2V(5)
SEM
R
= SEM
L
>VCC - 0.2V
MIL. &
IND.
S
L
90
90
230
200
85
85
200
170
80
80
175
150
V
V
IN > VCC - 0.2V or
IN < 0.2V, Active Port
(3)
Outputs Disable d, f = fMAX
2954 tbl 11
NOTES:
1. 'X' in part numbers indicates power rating (S or L)
2. VCC = 5V, TA = +25°C, and are not production tested. ICCDC = 120mA(typ.)
3. At f = fMAX, address and I/O'S are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions” of input levels of GND to 3V.
4. f = 0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "B" is the opposite of port "A".
6.42
6
IDT7015S/L
High-Speed 8K x 9 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltageRange(4)
7015X12
7015X15
Com'l Only
7015X17
Com'l Only
Com'l Only
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
____
____
____
t
RC
AA
ACE
AOE
OH
LZ
HZ
PU
PD
SOP
SAA
Read Cycle Time
12
15
17
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
____
____
____
t
Address Access Time
12
12
15
15
17
17
Chip Enable Access Time(3)
____
____
____
____
____
____
t
t
Output Enable Access Time
8
10
10
____
____
____
t
Output Hold from Address Change
Output Low-Z Time(1,2)
3
3
3
____
____
____
t
3
3
3
Output High-Z Time(1,2)
10
10
10
____
____
____
t
t
Chip Enable to Power Up Time(2)
Chip Disable to Power Down Time(2)
Semaphore Flag Update Pulse (OE or SEM)
Semaphore Address Access Time
0
0
0
____
____
____
____
____
____
t
12
15
17
____
____
____
t
10
10
10
____
____
____
t
12
15
17
ns
2954 tbl 12a
7015X20
Com'l. Ind
& Military
7015X25
Com'l &
Military
7015X35
Com'l &
Military
Symbol
READ CYCLE
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
____
____
____
t
RC
AA
ACE
AOE
OH
LZ
HZ
PU
PD
SOP
SAA
Read Cycle Time
20
25
35
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
____
____
____
t
Address Access Time
20
20
25
25
35
35
Chip Enable Access Time(3)
Output Enable Access Time
Output Hold from Address Change
Output Low-Z Time(1,2)
____
____
____
____
____
____
t
t
12
13
20
____
____
____
t
3
3
3
____
____
____
t
3
3
3
Output High-Z Time(1,2)
12
15
20
____
____
____
t
t
Chip Enable to Power Up Time(2)
Chip Disable to Power Down Time(2)
Semaphore Flag Update Pulse (OE or SEM)
Semaphore Address Access Time
0
0
0
____
____
____
____
____
____
t
20
25
35
____
____
____
t
10
10
15
____
____
____
t
20
25
35
ns
2954 tbl 12b
NOTES:
1. Transition is measured 0mV from Low- or High-impedance voltage with load (Figures 1 and 2).
2. This parameter is guaranteed by device characterization but not tested.
3. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL.
4. 'X' in part numbers indicates power rating (S or L).
6.742
IDT7015S/L
High-Speed 8K x 9 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Waveform of Read Cycles(5)
tRC
ADDR
(4)
tAA
(4)
tACE
CE
OE
(4)
t
AOE
R/W
(1)
tOH
tLZ
(4)
DATAOUT
VALID DATA
(2)
tHZ
BUSYOUT
(3,4)
BDD
2954 drw 07
t
NOTES:
1. Timing depends on which signal is asserted last, OE or CE.
2. Timing depends on which signal is de-asserted first, CE or OE.
3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY
has no relation to valid output data.
4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBDD.
5. SEM = VIH.
Timing of Power-Up / Power-Down
CE
tPU
tPD
ICC
50%
50%
I
SB
,
2954 drw 08
6.42
8
IDT7015S/L
High-Speed 8K x 9 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltage(5)
7015X12
7015X15
Com'l Only
7015X17
Com'l Only
Com'l Only
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
WC
EW
AW
AS
WP
WR
DW
HZ
DH
WZ
OW
SWRD
SPS
Write Cycle Time
12
10
10
0
15
12
12
0
17
12
12
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
Chip Enable to End-of-Write(3)
Address Valid to End-of-Write
Address Set-up Time(3)
Write Pulse Width
t
t
t
10
2
12
2
12
0
t
Write Recovery Time
t
Data Valid to End-of-Write
Output High-Z Time(1,2)
Data Hold Time(4)
10
10
10
____
____
____
t
10
10
10
____
____
____
t
0
0
0
(1,2)
____
____
____
t
Write Enable to Output in High-Z
Output Active from End-of-Write(1, 2,4)
SEM Flag Write to Read Time
SEM Flag Contention Window
10
10
10
____
____
____
t
3
5
5
3
5
5
0
5
5
____
____
____
____
____
____
t
t
ns
2954 tbl 13a
7015X20
Com'l, Ind
& Military
7015X25
Com'l &
Military
7015X35
Com'l &
Military
Symbol
WRITE CYCLE
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
WC
EW
AW
AS
WP
WR
DW
HZ
DH
WZ
OW
SWRD
SPS
Write Cycle Time
20
15
15
0
25
20
20
0
35
30
30
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
Chip Enable to End-of-Write(3)
Address Valid to End-of-Write
Address Set-up Time(3)
Write Pulse Width
t
t
t
15
2
20
2
25
0
t
Write Recovery Time
Data Valid to End-of-Write
Output High-Z Time(1,2)
Data Hold Time(4)
t
15
15
15
____
____
____
t
12
15
20
____
____
____
t
0
0
0
(1,2)
____
____
____
t
Write Enable to Output in High-Z
12
15
20
t
Output Active from End-of-Write(1, 2,4)
SEM Flag Write to Read Time
SEM Flag Contention Window
3
5
5
3
5
5
3
5
5
____
____
____
____
____
____
____
____
____
t
t
ns
2954 tbl 13b
NOTES:
1. Transition is measured 0mV from Low- or High-impedance voltage with the Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization but not tested.
3. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time.
4. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage
and temperature, the actual tDH will always be smaller than the actual tOW.
5. 'X' in part numbers indicates power rating (S or L).
6.942
IDT7015S/L
High-Speed 8K x 9 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8)
t
WC
ADDRESS
(7)
t
HZ
OE
t
AW
CE or SEM(9)
(7)
t
HZ
(3)
(6)
(2)
t
WR
tAS
tWP
R/W
(7)
tLZ
t
OW
t
WZ
(4)
(4)
OUT
DATA
t
DH
t
DW
IN
DATA
,
2954 drw 09
Timing Waveform of Write Cycle No. 2, CE Controlled Timing(1,5)
t
WC
ADDRESS
tAW
(9)
CE or SEM
R/W
(3)
(6)
(2)
tWR
t
AS
tEW
t
DW
tDH
DATAIN
2954 drw 10
NOTES:
1. R/W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of a LOW CE and a LOW R/W for memory array writing cycle.
3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal is asserted last, CE or R/W.
7. This parameter is guaranteed by device characterization but is not production tested. Transition is measured 0mV from steady state with the Output Test Load
(Figure 2).
8. If OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be placed
on the bus for the required tDW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified
tWP.
9. To access RAM, CE = VIL and SEM = VIH. To access Semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition.
6.42
10
IDT7015S/L
High-Speed 8K x 9 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Semaphore Read after Write Timing, Either Side(1)
tOH
t
SAA
A0-A2
VALID ADDRESS
VALID ADDRESS
tWR
tACE
tAW
tEW
SEM
t
SOP
tDW
DATAIN
VALID
DATAOUT
VALID(2)
I/O
tAS
tDH
t
WP
R/W
tAOE
tSWRD
OE
Read Cycle
Write Cycle
2954 drw 11
NOTES:
1. CE = VIH for the duration of the above timing (both write and read cycle).
2. “DATAOUT VALID” represents all I/O's (I/O0-I/O8) equal to the semaphore value.
Timing Waveform of Semaphore Write Contention(1,3,4)
A0"A"-A2 "A"
MATCH
SIDE(2) "A"
R/W"A"
SEM"A"
tSPS
MATCH
A0"B"-A2 "B"
SIDE(2)
"B"
R/W"B"
SEM"B"
2954 drw 12
NOTES:
1. DOR = DOL =VIH, CER = CEL =VIH.
2. All timing is the same for left and right ports. Port“A” may be either left or right port. “B” is the opposite port from “A”.
3. This parameter is measured from R/W“A” or SEM“A” going high to R/W“B” or SEM“B” going HIGH.
4. If tSPS is not satisfied, there is no guarantee which side will obtain the semaphore flag.
61.412
IDT7015S/L
High-Speed 8K x 9 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltageRange(6)
7015X12
7015X15
Com'l Only
7015X17
Com'l Only
Com'l Only
Symbol
BUSY TIMING (M/S = VIH
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
)
____
____
____
____
____
____
____
____
____
____
____
____
t
BAA
BDA
BAC
BDC
APS
BDD
WH
12
12
12
15
15
15
17
17
17
ns
ns
ns
ns
ns
ns
ns
BUSY Access Time from Address
BUSY Disable Time from Address
BUSY Access Time from Chip Enable
BUSY Disable Time from Chip Enable
Arbitration Priority Set-up Time(2)
BUSY Disable to Valid Data(3)
t
t
t
12
15
17
____
____
____
t
5
5
5
____
____
____
t
15
18
18
(5)
____
____
____
t
Write Hold After BUSY
11
13
13
BUSY INPUT TIMING (M/S = VIL
)
____
____
____
____
____
____
BUSY Input to Write(4)
t
WB
0
0
0
ns
ns
(5)
tWH
Write Hold After BUSY
11
13
13
PORT-TO-PORT DELAY TIMING
____
____
____
____
____
____
t
WDD
Write Pulse to Data Delay(1)
25
20
30
25
40
35
ns
tDDD
Write Data Valid to Read Data Delay(1)
ns
2954 tbl 14a
7015X20
Com'l, Ind
& Military
7015X25
Com'l &
Military
7015X35
Com'l &
Military
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
BUSY TIMING (M/S = VIH
)
____
____
____
____
____
____
____
____
____
____
____
____
t
BAA
BDA
BAC
BDC
APS
BDD
WH
20
20
20
20
20
20
20
20
20
ns
ns
ns
ns
ns
ns
ns
BUSY Access Time from Address
BUSY Disable Time from Address
BUSY Access Time from Chip Enable
BUSY Disable Time from Chip Enable
Arbitration Priority Set-up Time(2)
BUSY Disable to Valid Data(3)
t
t
t
17
17
20
____
____
____
t
5
5
5
____
____
____
t
30
30
35
(5)
____
____
____
t
Write Hold After BUSY
15
17
25
BUSY INPUT TIMING (M/S = VIL
)
____
____
____
____
____
____
BUSY Input to Write(4)
t
WB
0
0
0
ns
ns
(5)
tWH
Write Hold After BUSY
15
17
25
PORT-TO-PORT DELAY TIMING
____
____
____
____
____
____
t
WDD
Write Pulse to Data Delay(1)
45
30
50
35
60
45
ns
tDDD
Write Data Valid to Read Data Delay(1)
ns
2954 tbl 14b
NOTES:
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Wave form of Write with Port-to-Port Read and BUSY (M/S = VIH)".
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited on Port "B" during contention on Port "A".
5. To ensure that a write cycle is completed on Port "B" after contention on Port "A".
6. 'X' in part numbers indicates power rating (S or L).
6.42
12
IDT7015S/L
High-Speed 8K x 9 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Read with BUSY(2,4,5) (M/S = VIH)
t
WC
MATCH
ADDR"A"
R/W"A"
t
WP
t
DH
tDW
VALID
DATAIN "A"
(1)
tAPS
MATCH
ADDR"B"
tBDD
t
BDA
BUSY"B"
t
WDD
DATAOUT "B"
VALID
(3)
t
DDD
NOTES:
2954 drw 13
1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S=VIL
2. CEL = CER = VIL
3. OE = VIL for the reading port.
4. If M/S=VIL (SLAVE), BUSY is an input. Then for this example, BUSY“A”=VIH and BUSY“B” input is shown above.
5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from Port "A".
Timing Waveform of Write with BUSY(3)
t
WP
R/W"A"
tWB
BUSY"B"
(1)
tWH
R/W"B"
(2)
2954 drw 14
NOTES:
1. tWH must be met for both BUSY input (SLAVE) and output (MASTER).
2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH.
3. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from Port "A".
61.432
IDT7015S/L
High-Speed 8K x 9 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Waveform of BUSY Arbitration Controlled by CE timing(1) (M/S = VIH)
ADDR"A"
and "B"
ADDRESSES MATCH
CE"A"
(2)
t
APS
CE"B"
tBAC
tBDC
BUSY"B"
2954 drw 15
Waveform of BUSY Arbitration Cycle Controlled by Address Match
Timing(1) (M/S = VIH)
ADDRESS "N"
ADDR"A"
(2)
tAPS
MATCHING ADDRESS "N"
ADDR"B"
tBAA
tBDA
BUSY"B"
2954 drw 16
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.
2. If tAPS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.
AC Electrical Characteristics Over the
Operating TemperatureandSupplyVoltageRange(1)
7015X12
Com'l Only
7015X15
Com'l Only
7015X17
Com'l Only
Symbol
Parameter
Min.
Max.
Min. Max.
Min.
Max.
Unit
INTERRUPT TIMING
____
____
____
____
____
____
t
AS
WR
INS
INR
Address Set-up Time
Write Recovery Time
Interrupt Set Time
0
0
0
ns
ns
ns
t
0
0
0
____
____
____
t
12
12
15
15
17
17
____
____
____
t
Interrupt Reset Time
ns
2954 tbl 15a
7015X20
Com'l, Ind
& Military
7015X25
Com'l &
Military
7015X35
Com'l &
Military
Symbol
INTERRUPT TIMING
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
____
____
____
____
____
____
t
AS
WR
INS
INR
Address Set-up Time
Write Recovery Time
Interrupt Set Time
0
0
0
ns
ns
ns
t
0
0
0
____
____
____
t
20
20
20
20
25
25
____
____
____
t
Interrupt Reset Time
ns
2954 tbl 15b
NOTES:
1. 'X' in part numbers indicates power rating (S or L).
6.42
14
IDT7015S/L
High-Speed 8K x 9 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Waveform of Interrupt Timing(1)
t
WC
INTERRUPT SET ADDRESS (2)
ADDR"A"
(4)
(3)
t
WR
tAS
CE"A"
R/W"A"
INT"B"
(3)
tINS
2954 drw 17
t
RC
INTERRUPT CLEAR ADDRESS (2)
ADDR"B"
CE"B"
(3)
tAS
OE"B"
(3)
t
INR
INT"B"
2954 drw 18
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.
2. See Interrupt Truth Table.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
Truth Table III — Interrupt Flag(1)
Left Port
Right Port
OE
R/W
L
A12L-A0L
R/WR
A
12R-A0R
Function
Set Right INT Flag
Reset Right INT Flag
Set Left INT Flag
Reset Left INT Flag
CEL
OEL
INTL
CER
R
INTR
L
X
X
X
L
X
X
L
X
1FFF
X
X
X
X
L
L
X
X
L
X
L(2)
H(3)
X
R
X
X
X
1FFF
1FFE
X
R
X
X
L(3)
H(2)
L
X
X
L
L
1FFE
X
X
L
2954 tbl 16
NOTES:
1. Assumes BUSYL = BUSYR = VIH.
2. If BUSYL = VIL, then no change.
3. If BUSYR = VIL, then no change.
61.452
IDT7015S/L
High-Speed 8K x 9 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Truth Table IV — Address BUSY
Arbitration
Inputs
Outputs
A
OL-A12L
(1)
(1)
A
OR-A12R
Function
Normal
Normal
Normal
CE
L
CE
R
BUSY
L
BUSYR
X
H
X
L
X
X
H
L
NO MATCH
MATCH
H
H
H
H
MATCH
H
H
MATCH
(2)
(2)
Write Inhibit(3)
2954 tbl 17
NOTES:
1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSYX outputs on the IDT7015 are
push-pull, not open drain outputs. On slaves the BUSYX input internally inhibits writes.
2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address
and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs can not be LOW simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored
when BUSYR outputs are driving LOW regardless of actual logic level on the pin.
Truth Table V — Example of Semaphore Procurement Sequence(1,2,3)
Functions
D0
- D15 Left
D0
- D15 Right
Status
No Action
1
0
0
1
1
0
1
1
1
0
1
1
1
1
0
0
1
1
0
1
1
1
Semaphore free
Left Port Writes "0" to Semaphore
Right Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "1" to Semaphore
Right Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
Left port has semaphore token
No change. Right side has no write access to semaphore
Right port obtains semaphore token
No change. Left port has no write access to semaphore
Left port obtains semaphore token
Semaphore free
Right port has semaphore token
Semaphore free
Left port has semaphore token
Semaphore free
2954 tbl 18
NOTES:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT7015.
2. There are eight semaphore flags written to via I/O0 and read from all I/Os (I/O0 - I/O8). These eight semaphores are addressed by A0 - A2.
3. CE = VIH, SEM = VIL to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table.
FunctionalDescription
(INTL) is asserted when the right port writes to memory location 1FFE
where a write is defined as the CE = R/W = VIL per Truth Table III. The
leftportclearstheinterruptbyanaddresslocation1FFEaccesswhenCER
=OER =VIL, R/W is a "don't care". Likewise, the right port interrupt flag
(INTR)isassertedwhentheleftportwritestomemorylocation1FFFand
tocleartheinterruptflag(INTR),therightportmustaccess memory location
1FFF. The message (9 bits) at 1FFE or 1FFF isuser-defined since it is
anaddressableSRAMlocation.Iftheinterruptfunctionisnotused,address
locations 1FFE and 1FFF are not used as mail boxes but are still part
of the random access memory. Refer to Table III for the interrupt
operation.
TheIDT7015providestwoportswithseparatecontrol,addressand
I/Opinsthatpermitindependentaccessforreadsorwritestoanylocation
inmemory.TheIDT7015hasanautomaticpowerdownfeaturecontrolled
by CE. The CE controls on-chip power down circuitry that permits the
respectiveporttogointoastandbymodewhennotselected(CEHIGH).
Whenaportisenabled,accesstotheentirememoryarrayispermitted.
Interrupts
Iftheuserchoosestheinterruptfunction,amemorylocation(mailbox
or message center) is assigned to each port. The left port interrupt flag
6.42
16
IDT7015S/L
High-Speed 8K x 9 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
BusyLogic
CE
CE
BusyLogicprovidesahardwareindicationthatbothportsoftheRAM
haveaccessedthesamelocationatthesametime.Italsoallowsoneofthe
twoaccessestoproceedandsignalstheothersidethattheRAMis“busy”.
TheBUSYpincanthenbeusedtostalltheaccessuntiltheoperationon
theothersideiscompleted.Ifawriteoperationhasbeenattemptedfrom
thesidethatreceivesaBUSYindication,thewritesignalisgatedinternally
topreventthewritefromproceeding.
MASTER
Dual Port
RAM
SLAVE
Dual Port
RAM
BUSY (L) BUSY (R)
BUSY (R)
BUSY (L)
MASTER
Dual Port
RAM
CE
SLAVE
Dual Port
RAM
CE
BUSY (R)
BUSY (L)
BUSY (L)
BUSY (R)
BUSY (R)
BUSY (L)
TheuseofBUSYlogicisnotrequiredordesirableforallapplications.
InsomecasesitmaybeusefultologicallyORtheBUSYoutputstogether
and use anyBUSYindication as an interrupt source to flag the event of
anillegalorillogicaloperation.IfthewriteinhibitfunctionofBUSYlogicis
notdesirable,theBUSYlogiccanbedisabledbyplacingthepartinslave
modewiththeM/Spin.OnceinslavemodetheBUSYpinoperatessolely
asawriteinhibitinputpin.Normaloperationcanbeprogrammedbytying
the BUSY pins HIGH. If desired, unintended write operations can be
prevented to a port by tying the BUSY pin for that port LOW.
TheBUSYoutputsontheIDT7015RAMinmastermode,arepush-
pulltypeoutputsanddonotrequirepullupresistorstooperate. Ifthese
RAMs are being expanded in depth, then the BUSY indication for the
resulting array requires the use of an external AND gate.
2954 drw 19
Figure 3. Busy and chip enable routing for both width and depth
expansion with IDT7015 RAMs.
leftportinnowayslowstheaccesstimeoftherightport. Bothportsare
identicalinfunctiontostandardCMOSStaticRAMandcanbereadfrom,
orwrittento,atthesametimewiththeonlypossibleconflictarisingfromthe
simultaneous writing of, or a simultaneous READ/WRITE of, a non-
semaphorelocation.Semaphoresareprotectedagainstsuchambiguous
situationsandmaybeusedbythesystemprogramtoavoidanyconflicts
inthenon-semaphoreportionoftheDual-PortRAM.Thesedeviceshave
anautomaticpower-downfeaturecontrolledbyCE,theDual-PortRAM
enable,andSEM,thesemaphoreenable.TheCEandSEMpinscontrol
on-chip power down circuitry that permits the respective port to go into
standbymodewhennotselected. Thisistheconditionwhichisshownin
Truth Table I where CE and SEM are both HIGH.
SystemswhichcanbestusetheIDT7015containmultipleprocessors
or controllers and are typically very HIGH-speed systems which are
softwarecontrolledorsoftwareintensive.Thesesystemscanbenefitfrom
aperformanceincreaseofferedbytheIDT7015'shardwaresemaphores,
whichprovidealockoutmechanismwithoutrequiringcomplexprogram-
ming.
Softwarehandshakingbetweenprocessorsoffersthemaximumin
systemflexibilitybypermittingsharedresourcestobeallocatedinvarying
configurations.TheIDT7015doesnotuseitssemaphoreflagstocontrol
anyresourcesthroughhardware,thusallowingthesystemdesignertotal
flexibilityinsystemarchitecture.
An advantage of using semaphores rather than the more common
methodsofhardwarearbitrationisthatwaitstatesareneverincurredin
either processor. This can prove to be a major advantage in very high-
speedsystems.
Width Expansion with Busy Logic
Master/SlaveArrays
WhenexpandinganIDT7015RAMarrayinwidthwhileusingBUSY
logic,onemasterpartisusedtodecidewhichsideoftheRAMarraywill
receiveaBUSYindication,andtooutputthatindication.Anynumberof
slavestobeaddressedinthesameaddressrangeasthemasterusethe
BUSYsignalasawriteinhibitsignal.ThusontheIDT7015RAMtheBUSY
pinisanoutputifthepartisusedasamaster(M/Spin=H),andtheBUSY
pinisaninputifthepartusedasaslave(M/Spin=L)asshowninFigure
3.
Iftwoormoremasterpartswereusedwhenexpandinginwidth,asplit
decisioncouldresultwithonemasterindicatingBUSYononesideofthe
arrayandanothermasterindicatingBUSYononeothersideofthearray.
Thiswouldinhibitthewriteoperationsfromoneportforpartofawordand
inhibitthewriteoperationsfromtheotherportfortheotherpartoftheword.
TheBUSYarbitration,onamaster,isbasedonthechipenableand
address signals only. It ignores whether an access is a read or write. In
a master/slave array, both address and chip enable must be valid long
enoughforaBUSYflagtobeoutputfromthemasterbeforetheactualwrite
pulsecanbeinitiatedwiththeR/Wsignal.Failuretoobservethistimingcan
result in a glitched internal write inhibit signal and corrupted data in the
slave.
How the Semaphore Flags Work
Thesemaphorelogicisasetofeightlatcheswhichareindependent
oftheDual-PortRAM.Theselatchescanbeusedtopassaflag,ortoken,
fromoneporttotheothertoindicatethatasharedresourceisinuse.The
semaphores provide a hardware assist for a use assignment method
called“TokenPassingAllocation.”Inthismethod,thestateofasemaphore
latchisusedasatokenindicatingthatsharedresourceisinuse.Iftheleft
processorwantstousethisresource,itrequeststhetokenbysettingthe
latch.Thisprocessorthenverifiesitssuccessinsettingthelatchbyreading
it. If it was successful, it proceeds to assume control over the shared
resource.Ifitwasnotsuccessfulinsettingthelatch,itdeterminesthatthe
rightsideprocessorhassetthelatchfirst, hasthetokenandisusingthe
sharedresource.Theleftprocessorcantheneitherrepeatedlyrequest
that semaphore’s status or remove its request for that semaphore to
Semaphores
TheIDT7015areextremelyfastDual-Port8Kx9StaticRAMswithan
additional8addresslocationsdedicatedtobinarysemaphoreflags.These
flagsalloweitherprocessorontheleftorrightsideoftheDual-PortRAM
toclaimaprivilegeovertheotherprocessorforfunctionsdefinedbythe
systemdesigner’ssoftware.Asanexample,thesemaphorecanbeused
byoneprocessortoinhibittheotherfromaccessingaportionoftheDual-
Port RAM or any other shared resource.
The Dual-Port RAM features a fast access time, and both ports are
completelyindependentofeachother.Thismeansthattheactivityonthe
61.472
IDT7015S/L
High-Speed 8K x 9 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
perform another task and occasionally attempt again to gain control semaphoreflagwillforceitssideofthesemaphoreflagLOWandtheother
of the token via the set and test sequence. Once the right side has sideHIGH.Thisconditionwillcontinueuntilaoneiswrittentothesame
relinquishedthetoken,theleftsideshouldsucceedingainingcontrol.
semaphorerequestlatch.Shouldtheotherside’ssemaphorerequestlatch
ThesemaphoreflagsareactiveLOW.Atokenisrequestedbywriting havebeenwrittentoazerointhemeantime,thesemaphoreflagwillflip
azerointoasemaphorelatchandisreleasedwhenthesamesidewrites overtotheothersideassoonasaoneiswrittenintothefirstside’srequest
aonetothatlatch.
latch.Thesecondside’sflagwillnowstayLOWuntilitssemaphorerequest
The eight semaphore flags reside within the IDT7015 in a separate latchiswrittentoaone.Fromthisitiseasytounderstandthat,ifasemaphore
memoryspacefromtheDual-PortRAM.Thisaddressspaceisaccessed is requested and the processor which requested it no longer needs the
byplacingaLOWinputontheSEMpin(whichactsasachipselectforthe resource, the entire system can hang up until a one is written into that
semaphore flags) and using the other control pins (Address, OE, and semaphorerequestlatch.
R/W) as they would be used in accessing a standard static RAM. Each
The critical case of semaphore timing is when both sides request a
oftheflagshasauniqueaddresswhichcanbeaccessedbyeitherside single token by attempting to write a zero into it at the same time. The
throughaddresspinsA0–A2.Whenaccessingthesemaphores,noneof semaphorelogicisspeciallydesignedtoresolvethisproblem.Ifsimulta-
theotheraddresspinshasanyeffect.
neousrequestsaremade,thelogicguaranteesthatonlyonesidereceives
Whenwritingtoasemaphore,onlydatapinD0 isused.Ifalowlevel thetoken.Ifonesideisearlierthantheotherinmakingtherequest,thefirst
iswrittenintoanunusedsemaphorelocation,thatflagwillbesettoazero sidetomaketherequestwillreceivethetoken.Ifbothrequestsarriveat
onthatsideandaoneontheotherside(seeTableV).Thatsemaphore thesametime,theassignmentwillbearbitrarilymadetooneportorthe
can now only be modified by the side showing the zero. When a one is other.
writtenintothesamelocationfromthesameside,theflagwillbesettoa
One caution that should be noted when using semaphores is that
one for both sides (unless a semaphore request from the other side is semaphoresalonedonotguaranteethataccesstoaresourceissecure.
pending)andthencanbewrittentobybothsides.Thefactthattheside Aswithanypowerfulprogrammingtechnique,ifsemaphoresaremisused
whichisabletowriteazerointoasemaphoresubsequentlylocksoutwrites or misinterpreted, a software error can easily happen.
from the other side is what makes semaphore flags useful in inter
Initializationofthesemaphoresisnotautomaticandmustbehandled
processor communications. (A thorough discussing on the use of viatheinitializationprogramatpower-up.Sinceanysemaphorerequest
this feature follows shortly.) A zero written into the same location from flagwhichcontainsazeromustberesettoaone,allsemaphoresonboth
the other side will be stored in the semaphore request latch for that sidesshouldhaveaonewrittenintothematinitializationfrombothsides
sideuntilthesemaphoreisfreedbythefirstside.
to assure that they will be free when needed.
Whenasemaphoreflagisread,itsvalueisspreadintoalldatabitsso
thataflagthatisaonereadsasaoneinalldatabitsandaflagcontaining
azeroreadsasallzeros.Thereadvalueislatchedintooneside’soutput
registerwhenthatside'ssemaphoreselect(SEM)andoutputenable(OE)
signalsgoactive.Thisservestodisallowthesemaphorefromchanging
stateinthemiddleofareadcycleduetoawritecyclefromtheotherside.
Becauseofthislatch,arepeatedreadofasemaphoreinatestloopmust
cause either signal (SEM or OE) to go inactive or the output will never
change.
UsingSemaphores—SomeExamples
Perhapsthesimplestapplicationofsemaphoresistheirapplicationas
resourcemarkersfortheIDT7015’sDual-PortRAM.Saythe8Kx9RAM
wastobedividedintotwo4Kx9blockswhichweretobededicatedatany
onetimetoservicingeithertheleftorrightport.Semaphore0couldbeused
toindicatethesidewhichwouldcontrolthelowersectionofmemory,and
Semaphore 1 could be defined as the indicator for the upper section of
memory.
AsequenceWRITE/READmustbeusedbythesemaphoreinorder
to guarantee that no system level contention will occur. A processor
requestsaccesstosharedresourcesbyattemptingtowriteazerointoa
semaphorelocation.Ifthesemaphoreisalreadyinuse,thesemaphore
requestlatchwillcontainazero,yetthesemaphoreflagwillappearasone,
afactwhichtheprocessorwillverifybythesubsequentread(seeTable
V).Asanexample,assumeaprocessorwritesazerototheleftportata
freesemaphorelocation.Onasubsequentread,theprocessorwillverify
thatithaswrittensuccessfullytothatlocationandwillassumecontrolover
the resource in question. Meanwhile, if a processor on the right side
attemptstowriteazerotothesamesemaphoreflagitwillfail, aswillbe
verifiedbythefactthataonewillbereadfromthatsemaphoreontheright
side during subsequent read. Had a sequence of READ/WRITE been
used instead,systemcontentionproblemscouldhaveoccurredduring
the gap between the read and write cycles.
Totakearesource, inthisexamplethelower4KofDual-PortRAM,
the processor on the left port could write and then read a zero in to
Semaphore0.Ifthistaskweresuccessfullycompleted(azerowasread
back rather than a one), the left processor would assume control of the
lower4K.Meanwhiletherightprocessorwasattemptingtogaincontrolof
theresourceaftertheleftprocessor,itwouldreadbackaoneinresponse
tothezeroithadattemptedtowriteintoSemaphore0. Atthispoint, the
softwarecouldchoosetotryandgaincontrolofthesecond4Ksectionby
writing,thenreadingazerointoSemaphore1.Ifitsucceededingaining
control,itwouldlockouttheleftside.
Once the left side was finished with its task, it would write a one to
Semaphore 0 and may then try to gain access to Semaphore 1. If
Semaphore1wasstilloccupiedbytherightside,theleftsidecouldundo
itssemaphorerequestandperformothertasksuntilitwasabletowrite,then
readazerointoSemaphore1.Iftherightprocessorperformsasimilartask
withSemaphore0,thisprotocolwouldallowthetwoprocessorstoswap
4K blocks of Dual-Port RAM with each other.
Itisimportanttonotethatafailedsemaphorerequestmustbefollowed
byeitherrepeatedreadsorbywritingaoneintothesamelocation. The
reasonforthisiseasilyunderstoodbylookingatthesimplelogicdiagram
ofthesemaphoreflaginFigure4.Twosemaphorerequestlatchesfeed
into a semaphore flag. Whichever latch is first to present a zero to the
The blocks do not have to be any particular size and can even be
variable, depending upon the complexity of the software using the
6.42
18
IDT7015S/L
High-Speed 8K x 9 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
semaphoreflags.AlleightsemaphorescouldbeusedtodividetheDual- segmentsatfullspeed.
Port RAM or other shared resources into eight parts. Semaphores can
Anotherapplicationisintheareaofcomplexdatastructures.Inthis
evenbeassigneddifferentmeaningsondifferentsidesratherthanbeing case,blockarbitrationisveryimportant.Forthisapplicationoneprocessor
given a common meaning as was shown in the example above.
mayberesponsibleforbuildingandupdatingadatastructure.Theother
Semaphores are a useful form of arbitration in systems like disk processorthenreadsandinterpretsthatdatastructure.Iftheinterpreting
interfaceswheretheCPUmustbelockedoutofasectionofmemoryduring processorreadsanincompletedatastructure,amajorerrorconditionmay
atransferandtheI/Odevicecannottolerateanywaitstates.Withtheuse exist.Therefore,somesortofarbitrationmustbeusedbetweenthetwo
ofsemaphores,oncethetwodeviceshasdeterminedwhichmemoryarea differentprocessors.Thebuildingprocessorarbitratesfortheblock,locks
was“off-limits”totheCPU,boththeCPUandtheI/Odevicescouldaccess itandthenisabletogoinandupdatethedatastructure.Whentheupdate
theirassignedportionsofmemorycontinuouslywithoutanywaitstates. is completed, the data structure block is released. This allows the
Semaphoresarealsousefulinapplicationswherenomemory“WAIT” interpretingprocessortocomebackandreadthecompletedatastructure,
stateisavailableononeorbothsides.Onceasemaphorehandshakehas therebyguaranteeingaconsistentdatastructure.
been performed, both processors can access their assigned RAM
L PORT
SEMAPHORE
R PORT
SEMAPHORE
REQUEST FLIP FLOP
REQUEST FLIP FLOP
0
D
0
D
D
D
Q
Q
WRITE
WRITE
SEMAPHORE
READ
SEMAPHORE
READ
,
2954 drw 20
Figure 4. IDT7015 Semaphore Logic
61.492
IDT7015S/L
High-Speed 8K x 9 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
OrderingInformation
NOTES:
1. Contact your local sales office for industrial temp range for other speeds, packages and powers.
2. Green parts available. For specific speeds, packages and powers contact your local sales office.
Datasheet Document History
01/11/99:
Initiateddatasheetdocumenthistory
Convertedtonewformat
Cosmeticandtypographicalcorrections
Addedadditionalnotestopinconfigurations
Changeddrawingformat
Pages 2 and 3
Page 1
06/03/99:
Corrected DSC number
11/10/99:
05/19/00:
Replaced IDT logo
Increasedstoragetemperatureparameter
ClarifiedTA parameter
Page 4
Page 6
DCElectricalparameters–changedwordingfrom"open"to"disabled"
Changed ±200mV to 0mV in notes
Added date revision for pin configurations
Removed Industrial temp footnote from all tables
Added Industrial temp for 20ns speed to DC and AC Electrical Characteristics
Added Industrial temp offering to 20ns ordering information
Replaced TM logo with ® logo
01/24/02:
Pages 2 & 3
Pages 4, 6, 7, 9 & 12
Pages 6, 7, 9, 12 & 14
Page 20
Pages 1 & 20
6.42
20
IDT7015S/L
High-Speed 8K x 9 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Datasheet Document History (con't)
04/04/06:
Page 1
Added green availability to features
Page 20
Page 20
Page 20
Added green indicator to ordering information
Removed "IDT" from orderable part number
Added Tape & Reel to Ordering Information
10/21/08:
08/18/14:
Page 2, 3 & 20
The package codes PN80-1, G68-1 & J68-1 changed to PN80, G68 & J68 to match
standard package codes
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
for Tech Support:
408-284-2794
DualPortHelp@idt.com
800-345-7015 or 408-284-8200
fax: 408-284-2775
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
62.412
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