7016S15PF [IDT]
TQFP-80, Tray;
| 型号： | 7016S15PF |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | TQFP-80, Tray |
| 文件： | 总20页 (文件大小：164K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HIGH-SPEED
16K X 9 DUAL-PORT
STATIC RAM
IDT7016S/L
◆
IDT7016 easily expands data bus width to 18 bits or more
using the Master/Slave select when cascading more than
one device
M/S = VIH for BUSY output flag on Master
M/S = VIL for BUSY input on Slave
Features
◆
True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
High-speed access
◆
◆
– Commercial:12/15/20/25/35ns(max.)
– Industrial:20ns (max.)
◆
◆
◆
Busy and Interrupt Flag
On-chip port arbitration logic
– Military:20/25/35ns(max.)
Low-power operation
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
TTL-compatible, single 5V (±10%) power supply
Available in ceramic 68-pin PGA, 68-pin PLCC, and an 80-
pin TQFP
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Green parts available, see ordering information
◆
– IDT7016S
◆
◆
◆
Active:750mW(typ.)
Standby: 5mW (typ.)
– IDT7016L
Active:750mW(typ.)
Standby: 1mW (typ.)
◆
◆
FunctionalBlockDiagram
OEL
OER
CER
CEL
R/WR
R/W
L
I/O0L- I/O8L
I/O0R-I/O8R
I/O
I/O
Control
Control
BUSY (1,2)
L
(1,2)
R
BUSY
A
13L
A
13R
0R
Address
Decoder
MEMORY
ARRAY
Address
Decoder
A
A
0L
14
14
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE
OE
L
L
CE
OE
R/W
R
R
R
R/W
L
SEM
L
SEM
R
M/S
(2)
(2)
INTL
INT
R
3190 drw 01
NOTES:
1. In MASTER mode: BUSY is an output and is a push-pull driver
In SLAVE mode: BUSY is input.
2. BUSY outputs and INT outputs are non-tri-stated push-pull drivers.
JANUARY 2009
1
©2009 IntegratedDeviceTechnology,Inc.
DSC 3190/10
IDT7016S/L
High-Speed 16K x 9 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Description
The IDT7016 is a high-speed 16K x 9 Dual-Port Static RAM. The
IDT7016 is designed to be used as stand-alone Dual-Port RAMs or as
acombinationMASTER/SLAVEDual-PortRAMfor18-bit-or-morewider
systems.UsingtheIDTMASTER/SLAVEDual-PortRAMapproachin18-
bitorwidermemorysystemapplicationsresultsinfull-speed,error-free
operationwithouttheneedforadditionaldiscretelogic.
featurecontrolledbyCEpermitstheon-chipcircuitryofeachporttoenter
a very low standby power mode.
FabricatedusingIDT’sCMOShigh-performancetechnology,these
devices typicallyoperate ononly750mWofpower.
TheIDT7016is packagedinaceramic68-pinPGA,a64-pinPLCC
and an 80-pinTQFP (Thin Quad Flatpack). Military grade product is
manufacturedincompliancewiththelatestrevisionofMIL-PRF-38535
QML,makingitideallysuitedtomilitarytemperatureapplicationsdemand-
ingthehighestlevelofperformanceandreliability.
This device provides two independent ports with separate control,
address,andI/Opinsthatpermitindependent,asynchronousaccessfor
reads or writes to any location in memory. An automatic power down
PinConfigurations(1,2,3)
11/19/01
INDEX
9
8
7
6
5
4
3
2
1
68 67 66 65 64 63 62 61
60
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
I/O2L
I/O3L
I/O4L
I/O5L
GND
I/O6L
I/O7L
A
A
A
A
A
A
5L
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
4L
3L
2L
1L
0L
IDT7016J
,
(4)
J68-1
INTL
BUSY
GND
M/S
BUSY
INT
L
VCC
68-Pin PLCC
GND
I/O0R
I/O1R
I/O2R
(5)
Top View
R
R
VCC
A
A
A
A
A
0R
I/O3R
I/O4R
I/O5R
I/O6R
1R
2R
3R
4R
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
3190 drw 02
Pin Names (7016)
Left Port
Right Port
Names
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. Package body is approximately .95 in x .95 in x .17 in.
4. This package code is used to reference the package diagram.
5. This text does not imply orientation of Part-marking.
Chip Enable
CE
R/W
OE
L
CE
R/W
OE
R
L
R
Read/Write Enable
Output Enable
Address
L
R
A0L - A13L
A0R - A13R
I/O0L - I/O8L
SEM
INT
BUSY
I/O0R - I/O8R
Data Input/Output
Semaphore Enable
Interrupt Flag
Busy Flag
L
SEM
INT
BUSY
M/S
R
L
R
L
R
Master or Slave Select
Power
V
CC
GND
Ground
3190 tbl 01
2
6.42
IDT7016S/L
High-Speed 16K x 9 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
PinConfigurations(1,2,3)(con't.)
11/19/01
INDEX
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
NC
1
2
NC
I/O2L
I/O3L
I/O4L
I/O5L
GND
I/O6L
I/O7L
A5L
A4L
A3L
A2L
A1L
A0L
3
4
5
6
7
IDT7016PF
(4)
INT
L
8
PN80-1
BUSY
L
9
VCC
GND
10
11
12
13
14
15
16
17
18
19
20
NC
GND
I/O0R
I/O1R
I/O2R
80-Pin TQFP
(5)
M/S
Top View
BUSY
R
INT
R
A
A
A
A
A
0R
1R
2R
3R
4R
VCC
I/O3R
I/O4R
I/O5R
I/O6R
NC
NC
NC
3190 drw 03
11/19/01
51
50
48
A
46
A
44
42
40
38
36
11
A4L
2L
0L BUSY
L
M/S INT
R
A1R
A3R
A
5L
53
A
52
49
47
A
45
INT
43
41
39
A
37
35
34
A
10
09
08
07
L
GND BUSY
R
A4R
7L
A3L
1L
0R
A2R
5R
A
6L
55
A
54
32
33
A
A7R
9L
6R
A
8L
57
A
56
A
30
31
A
A9R
8R
11L
10L
12L
59
58
A
28
29
A
IDT7016G
A11R
10R
12R
V
CC
(4)
G68-1
61
60
26
GND
27
A
68-Pin PGA
Top View
06
05
(5)
N/C
A
13L
63
62
24
N/C
25
A
13R
SEM
L
CE
L
65
64
22
SEM
23
CE
04
03
02
R
R
OE
L
R/W
L
67
I/O0L
66
20
OE
21
R/W
R
R
I/O8L
1
3
5
GND
7
9
GND
68
11
13
V
15
18
I/O7R
19
I/O8R
CC
I/O1L
I/O4L
I/O7L
I/O2L
I/O1R
I/O4R
,
NOTES:
2
4
6
8
10
12
14
16
17
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. PN80-1 package body is approximately
14mm x 14mm x 1.4mm.
01
I/O6L
I/O3L I/O5L
I/O0R I/O2R I/O3R I/O5R I/O6R
V
CC
A
B
C
D
E
F
G
H
J
K
L
INDEX
G68-1 package body is approximately
1.18 in x 1.18 in x .16 in.
3190 drw 04
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
6.432
IDT7016S/L
High-Speed 16K x 9 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Truth Table I: Non-Contention Read/Write Control
Inputs(1)
R/W
Outputs
I/O0-8
Mode
CE
H
L
OE
X
X
L
SEM
H
X
L
High-Z
DATAIN
DATAOUT
High-Z
Deselcted: Power-Down
Write to Memory
Read Memory
H
L
H
X
H
X
H
X
Outputs Disabled
3190 tbl 02
NOTE:
1.
Condition: A0L — A13L ≠ A0R — A13R
Truth Table II: Semaphore Read/Write Control(1)
Inputs
Outputs
R/W
H
I/O0-8
Mode
- I/O
CE
H
OE
L
SEM
L
DATAOUT
Read Semaphore Flag Data Out (I/O
Write I/O into Semaphore Flag
Not Allowed
0
8)
H
X
L
DATAIN
0
↑
____
L
X
X
L
3190 tbl 03
NOTE:
1. There are eight semaphore flags written to via I/O0 and read from all I/Os (I/O0-I/O8). These eight semaphores are addressed by A0 - A2.
AbsoluteMaximumRatings(1)
MaximumOperating
TemperatureandSupplyVoltage(1)
Symbol
Rating
Commercial
& Industrial
Military
Unit
Grade
Ambient
GND
Vcc
(2)
Temperature
V
TERM
Terminal Voltage
with Respect
to GND
-0.5 to +7.0
-0.5 to +7.0
V
Military
-55OC to +125OC
0OC to +70OC
0V
0V
0V
5.0V
5.0V
5.0V
+
+
+
10%
10%
Temperature
Under Bias
-55 to +125
-65 to +150
50
-65 to +135
-65 to +150
50
oC
oC
Commercial
Industrial
TBIAS
-40OC to +85OC
10%
Storage
Temperature
TSTG
3190 tbl 05
NOTES:
1. This is the parameter TA. This is the "instant on" case temperature.
DC Output
Current
mA
I
OUT
3190 tbl 04
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
RecommendedDCOperating
Conditions
Symbol
Parameter
Supply Voltage
GND Ground
Min.
Typ. Max. Unit
2. VTERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of VTERM > Vcc + 10%.
VCC
4.5
5.0
5.5
0
V
V
V
0
0
V
IH
Input High Voltage
Input Low Voltage
2.2
6.0(2)
0.8
____
-0.5(1)
V
____
VIL
3190 tbl 06
NOTES:
1. VIL > -1.5V for pulse width less than 10ns.
2. VTERM must not exceed Vcc + 10%.
4
6.42
IDT7016S/L
High-Speed 16K x 9 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Capacitance(1)
(TA = +25°C, f = 1.0mhz, for TQFP ONLY)
Symbol
Parameter
Input Capacitance
Output Capacitance
Conditions(2)
IN = 3dV
OUT = 3dV
Max. Unit
CIN
V
9
pF
COUT
V
10
pF
3190 tbl 07
NOTES:
1. This parameter is determined by device characteristics but is not production
tested.
2. 3dV references the interpolated capacitance when the input and output signals
switch from 0V to 3V or from 3V to 0V .
DC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range (VCC = 5.0V ± 10%)
7016S
7016L
Symbol
|ILI
|ILO
Parameter
Test Conditions
Min.
Max.
10
Min.
Max.
5
Unit
µA
µA
V
(1)
___
___
|
Input Leakage Current
V
CC = 5.5V, VIN = 0V to VCC
___
___
___
___
|
Output Leakage Current
Output Low Voltage
Output High Voltage
10
5
CE = VIH, VOUT = 0V to VCC
VOL
I
OL = +4mA
0.4
0.4
___
___
VOH
I
OH = -4mA
2.4
2.4
V
3190 tbl 08
NOTE:
1. At Vcc < 2.0V, Input leakages are undefined.
Output Loads and AC Test
Conditions
Input Pulse Levels
GND to 3.0V
3ns Max.
1.5V
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
1.5V
Output Load
Figures 1 and 2
3190 tbl 09
5V
5V
893Ω
893Ω
DATAOUT
BUSY
INT
DATAOUT
5pF*
30pF
347Ω
347Ω
,
3190 drw 06
Figure 1. AC Output Test Load
Figure 2. Output Test Load
(for tLZ, tHZ, tWZ, tOW)
*Including scope and jig.
6.452
IDT7016S/L
High-Speed 16K x 9 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1) (con't.) (VCC = 5.0V ± 10%)
7016X12
Com'l Only
7016X15
Com'l Only
Symbol
Parameter
Test Condition
Version
Typ.(2)
Max.
Typ.(2)
Max.
Unit
ICC
Dynamic Operating
Current
(Both Ports Active)
COM'L
S
L
170
170
325
275
170
170
310
260
mA
CE = VIL, Outputs Disabled
SEM = VIH
(3)
f = fMAX
____
____
____
____
____
____
____
____
MIL &
IND
S
L
I
SB1
Standby Current
(Both Ports - TTL
Level Inputs)
COM'L
S
L
25
25
70
60
25
25
60
50
mA
mA
mA
mA
CE
SEM
f = fMAX
R
= CE
L
= VIH
= VIH
R
= SEM
L
(3)
____
____
____
____
____
____
____
____
MIL &
IND
S
L
(5)
ISB2
Standby Current
(One Port - TTL
Level Inputs)
COM'L
S
L
105
105
200
170
105
105
190
160
CE"A" = VIL and CE"B" = VIH
Active Port Outputs Disabled,
(3)
f=fMAX
____
____
____
____
____
____
____
____
MIL &
IND
S
L
SEM
R
= SEM
L
= VIH
and
ISB3
Full Standby Current
(Both Ports - All CMOS
Level Inputs)
Both Ports CE
CE > VCC - 0.2V
IN > VCC - 0.2V or
IN < 0.2V, f = 0(4)
SEM = SEM > VCC - 0.2V
L
COM'L
S
L
1.0
0.2
15
5
1.0
0.2
15
5
R
V
____
____
____
____
____
____
____
____
MIL &
IND
S
L
V
R
L
ISB4
Full Standby Current
(One Port - All CMOS
Level Inputs)
COM'L
S
L
100
100
180
150
100
100
170
140
CE < 0.2V and
CE"BA" > VCC - 0.2V
(5)
SEM
R
= SEML > VCC - 0.2V
____
____
____
____
____
____
____
____
MIL &
IND
S
L
V
IN > VCC - 0.2V or VIN < 0.2V
Active Port Outputs Disabled
(3)
f = fMAX
3190 tbl 10
7016X20
Com'l, Ind
& Military
7016X25
Com'l &
Military
7016X35
Com'l &
Military
Symbol
Parameter
Test Condition
Version
COM'L
Typ.(2)
Max.
Typ.(2)
Max.
Typ.(2)
Max.
Unit
ICC
Dynamic Operating Current
(Both Ports Active)
S
L
160
160
290
240
155
155
265
220
150
150
250
210
mA
CE = VIL, Outputs Disabled
SEM = VIH
(3)
f = fMAX
MIL &
IND
S
L
160
160
380
310
155
155
340
280
150
150
300
250
I
SB1
Standby Current
(Both Ports - TTL
Level Inputs)
COM'L
S
L
20
20
60
50
16
16
60
50
13
13
60
50
mA
mA
mA
mA
CE
R
SEM
= CE = VIH
R
= SLEM
L
= VIH
(3)
f = fMAX
MIL &
IND
S
L
20
20
80
65
16
16
80
65
13
13
80
65
(5)
ISB2
Standby Current
(One Port - TTL
Level Inputs)
COM'L
S
L
95
95
180
150
90
90
170
140
85
85
155
130
CE"A" = VIL and CE"B" = VIH
Active Port Outputs Disabled,
(3)
f=fMAX
SEM
MIL &
IND
S
L
95
95
240
210
90
90
215
180
85
85
190
160
R
= SEM
L
= VIH
and
ISB3
Full Standby Current
(Both Ports - All CMOS
Level Inputs)
Both Ports CE
CE > VCC - 0.2V
IN > VCC - 0.2V or
IN < 0.2V, f = 0(4)
SEM = SEM > VCC - 0.2V
L
COM'L
S
L
1.0
0.2
15
5
1.0
0.2
15
5
1.0
0.2
15
5
R
V
V
MIL &
IND
S
L
1.0
0.2
30
10
1.0
0.2
30
10
1.0
0.2
30
10
R
L
ISB4
Full Standby Current
(One Port - All CMOS Level
Inputs)
COM'L
S
L
90
90
155
130
85
85
145
120
80
80
135
110
CE < 0.2V and
CE"BA" > VCC - 0.2V
(5)
SEM
R
= SEML > VCC - 0.2V
MIL &
IND
S
L
90
90
230
200
85
85
200
170
80
80
175
150
V
IN > VCC - 0.2V or VIN < 0.2V
Active Port Outputs Disabled
(3)
f = fMAX
3190 tbl 11
NOTES:
1. 'X' in part numbers indicates power rating (S or L)
2. VCC = 5V, TA = +25°C, and are not production tested. ICCDC = 120mA(typ.)
3. At f = fMAX, address and I/Os are cycling at the maximum frequency read cycle of 1/tRC.
4. f = 0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "B" is the opposite of Port "A".
6
6.42
IDT7016S/L
High-Speed 16K x 9 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltageRange(4)
7016X12
Com'l Only
7016X15
Com'l Only
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
READ CYCLE
____
____
t
RC
AA
ACE
AOE
OH
LZ
HZ
PU
PD
SOP
SAA
Read Cycle Time
12
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
____
____
t
Address Access Time
12
12
15
15
Chip Enable Access Time(3)
Output Enable Access Time
Output Hold from Address Change
Output Low-Z Time(1,2)
____
____
____
____
t
t
8
10
____
____
t
3
3
____
____
t
3
3
Output High-Z Time(1,2)
10
10
____
____
t
t
Chip Enable to Power Up Time(2)
Chip Disable to Power Down Time(2)
0
0
____
____
____
____
t
12
15
____
____
t
Semaphore Flag Update Pulse (OE or SEM)
10
10
____
____
t
Semaphore Address Access Time
12
15
ns
3190 tbl 12a
7016X20
Com'l, Ind
& Military
7016X25
Com'l &
Military
7016X35
Com'l &
Military
Symbol
READ CYCLE
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
____
____
____
t
RC
AA
ACE
AOE
OH
LZ
HZ
PU
PD
SOP
SAA
Read Cycle Time
20
25
35
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
____
____
____
t
Address Access Time
20
20
25
25
35
35
Chip Enable Access Time(3)
Output Enable Access Time
Output Hold from Address Change
Output Low-Z Time(1,2)
____
____
____
____
____
____
t
t
12
13
20
____
____
____
t
3
3
3
____
____
____
t
3
3
3
Output High-Z Time(1,2)
12
15
20
____
____
____
t
t
Chip Enable to Power Up Time(2)
Chip Disable to Power Down Time(2)
Semaphore Flag Update Pulse (OE or SEM)
Semaphore Address Access Time
0
0
0
____
____
____
____
____
____
t
20
25
35
____
____
____
t
10
10
10
____
____
____
t
20
25
35
ns
3190 tbl 12b
NOTES:
1. Transition is measured 0mV from Low- or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization but not production tested.
3. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL.
4. 'X' in part numbers indicates power rating (S or L).
6.472
IDT7016S/L
High-Speed 16K x 9 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Waveform of Read Cycles(5)
tRC
ADDR
(4)
t
AA
(4)
t
ACE
CE
OE
(4)
t
AOE
R/W
DATAOUT
BUSYOUT
NOTES:
(1)
t
OH
tLZ
(4)
VALID DATA
(2)
t
HZ
(3,4)
3190 drw 07
t
BDD
1. Timing depends on which signal is asserted last, OE or CE.
2. Timing depends on which signal is de-asserted first, CE or OE.
3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY
has no relation to valid output data.
4. Start of valid data depends on which timing becomes effective last: tAOE, tACE, tAA or tBDD.
5. SEM = VIH.
Timing of Power-Up / Power-Down
CE
t
PU
tPD
I
CC
50%
50%
I
SB
,
3190 drw 08
8
6.42
IDT7016S/L
High-Speed 16K x 9 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltage(5)
7016X12
Com'l Only
7016X15
Com'l Only
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
WC
EW
AW
AS
WP
WR
DW
HZ
DH
WZ
OW
SWRD
SPS
Write Cycle Time
12
10
10
0
15
12
12
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
Chip Enable to End-of-Write(3)
Address Valid to End-of-Write
Address Set-up Time(3)
Write Pulse Width
t
t
t
10
2
12
2
t
Write Recovery Time
Data Valid to End-of-Write
Output High-Z Time(1,2)
Data Hold Time(4)
t
10
10
____
____
t
10
10
____
____
t
0
0
(1,2)
____
____
t
Write Enable to Output in High-Z
Output Active from End-of-Write(1, 2,4)
SEM Flag Write to Read Time
SEM Flag Contention Window
10
10
____
____
t
3
5
5
3
5
5
____
____
____
____
t
t
ns
3190 tbl 13a
7016X20
Com'l, Ind
& Military
7016X25
Com'l &
Military
7016X35
Com'l &
Military
Symbol
WRITE CYCLE
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
WC
EW
AW
AS
WP
WR
DW
HZ
DH
WZ
OW
SWRD
SPS
Write Cycle Time
20
15
15
0
25
20
20
0
35
30
30
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
Chip Enable to End-of-Write(3)
Address Valid to End-of-Write
Address Set-up Time(3)
Write Pulse Width
t
t
t
15
2
20
2
25
2
t
Write Recovery Time
Data Valid to End-of-Write
Output High-Z Time(1,2)
Data Hold Time(4)
t
15
15
15
____
____
____
t
12
15
20
____
____
____
t
0
0
0
(1,2)
____
____
____
t
Write Enable to Output in High-Z
12
15
20
t
Output Active from End-of-Write(1, 2,4)
SEM Flag Write to Read Time
SEM Flag Contention Window
3
5
5
3
5
5
3
5
5
____
____
____
____
____
____
____
____
____
t
t
ns
3190 tbl 13b
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization but not production tested.
3. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time.
4. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage
and temperature, the actual tDH will always be smaller than the actual tOW.
5. 'X' in part numbers indicates power rating (S or L).
6.492
IDT7016S/L
High-Speed 16K x 9 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8)
t
WC
ADDRESS
(7)
t
HZ
OE
t
AW
CE or SEM(9)
(3)
(2)
(6)
t
WR
t
AS
tWP
R/W
(7)
t
LZ
t
OW
t
WZ
(4)
(4)
OUT
DATA
t
DW
t
DH
IN
DATA
3190 drw 09
Timing Waveform of Write Cycle No. 2, CE Controlled Timing(1,5)
t
WC
ADDRESS
t
AW
CE or SEM(9)
R/W
(6)
AS
(3)
(2)
t
WR
t
tEW
t
DW
tDH
DATAIN
3190 drw 10
NOTES:
1. R/W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of a LOW CE and a LOW R/W for memory array writing cycle.
3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal is asserted last, CE or R/W.
7. This parameter is guaranteed by device characterization but is not production tested. Transition is measured 0mV from steady state with the Output Test Load (Figure
2).
8. If OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be
placed on the bus for the required tDW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as
the specified tWP.
9. To access RAM, CE = VIL and SEM = VIH. To access Semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition.
10
6.42
IDT7016S/L
High-Speed 16K x 9 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Semaphore Read after Write Timing, Either Side(1)
tSAA
VALID ADDRESS
VALID ADDRESS
t
A0-A2
tWR
tAW
ACE
tEW
SEM
t
OH
t
DW
tSOP
DATAIN
VALID
DATAOUT
VALID(2)
I/O
tAS
tWP
tDH
R/W
tAOE
tSWRD
OE
Read Cycle
Write Cycle
3190 drw 11
NOTES:
1. CE = VIH for the duration of the above timing (both write and read cycle).
2. “DATAOUT VALID” represents all I/O's (I/O0-I/O8) equal to the semaphore value.
Timing Waveform of Semaphore Write Condition(1,3,4)
A0"A"-A2 "A"
MATCH
SIDE(2) "A"
R/W"A"
SEM"A"
tSPS
A0"B"-A2 "B"
MATCH
SIDE(2)
"B"
R/W"B"
SEM"B"
3190 drw 12
NOTES:
1. DOR = DOL =VIH, CER = CEL =VIH.
2. All timing is the same for left and right ports. Port“A” may be either left or right port. “B” is the opposite port from “A”.
3. This parameter is measured from R/W“A” or SEM“A” going HIGH to R/W“B” or SEM“B” going HIGH.
4. If tSPS is not satisfied, there is no guarantee which side will obtain the semaphore flag.
6.1412
IDT7016S/L
High-Speed 16K x 9 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltageRange(6)
7016X12
Com'l Only
7016X15
Com'l Only
Symbol
BUSY TIMING (M/S = VIH
Parameter
Min.
Max.
Min.
Max.
Unit
)
____
____
____
____
____
____
____
____
t
BAA
BDA
BAC
BDC
APS
BDD
WH
12
12
12
15
15
15
ns
ns
ns
ns
ns
ns
ns
BUSY Access Time from Address Match
t
BUSY Disable Time from Address Not Matched
BUSY Access Time from Chip Enable Low
BUSY Disable Time from Chip Enable High
Arbitration Priority Set-up Time(2)
t
t
12
15
____
____
t
5
5
____
____
BUSY Disable to Valid Data(3)
t
15
18
t
Write Hold After BUSY(5)
11
13
____
____
BUSY INPUT TIMING (M/S = VIL
)
____
____
____
____
BUSY Input to Write(4)
Write Hold After BUSY(5)
t
WB
0
0
ns
ns
tWH
11
13
PORT-TO-PORT DELAY TIMING
____
____
____
____
t
WDD
Write Pulse to Data Delay(1)
25
20
30
25
ns
tDDD
Write Data Valid to Read Data Delay(1)
ns
3190 tbl 14a
7016X20
Com'l, Ind
& Military
7016X25
Com'l &
Military
7016X35
Com'l &
Military
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
BUSY TIMING (M/S = VIH
)
____
____
____
____
____
____
____
____
____
____
____
____
t
BAA
BDA
BAC
BDC
APS
BDD
WH
20
20
20
20
20
20
20
20
20
ns
ns
ns
ns
ns
ns
ns
BUSY Access Time from Address Match
BUSY Disable Time from Address Not Matched
BUSY Access Time from Chip Enable Low
BUSY Disable Time from Chip Enable High
Arbitration Priority Set-up Time(2)
BUSY Disable to Valid Data(3)
t
t
t
17
17
20
____
____
____
t
5
5
5
____
____
____
t
30
30
35
t
Write Hold After BUSY(5)
15
17
25
____
____
____
BUSY INPUT TIMING (M/S = VIL
)
____
____
____
____
____
____
BUSY Input to Write(4)
Write Hold After BUSY(5)
t
WB
0
0
0
ns
ns
tWH
15
17
25
PORT-TO-PORT DELAY TIMING
____
____
____
____
____
____
t
WDD
Write Pulse to Data Delay(1)
45
30
50
35
60
45
ns
tDDD
Write Data Valid to Read Data Delay(1)
ns
3190 tbl 14b
NOTES:
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveformof Write with Port-to-Port Read and BUSY (M/S = VIH)".
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited on Port "B" during contention on Port "A".
5. To ensure that a write cycle is completed on Port "B" after contention on Port "A".
6. 'X' in part numbers indicates power rating (S or L).
12
6.42
IDT7016S/L
High-Speed 16K x 9 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Read with BUSY(2,4,5) (M/S = VIH)
tWC
MATCH
ADDR"A"
tWP
R/W"A"
t
DH
t
DW
VALID
DATAIN "A"
(1)
t
APS
MATCH
ADDR"B"
t
BDD
tBDA
BUSY"B"
t
WDD
DATAOUT "B"
VALID
(3)
t
DDD
3190 drw 13
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S=VIL.
2. CEL = CER = VIL.
3. OE = VIL for the reading port.
4. If M/S=VIL (SLAVE), BUSY is an input. Then for this example BUSY“A” = VIH and BUSY“B” input is shown above.
5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from Port "A".
Timing Waveform of Write with BUSY(3)
tWP
R/W"A"
t
WB
BUSY"B"
(1)
t
WH
R/W"B"
(2)
,
3190 drw 14
NOTES:
1. tWH must be met for both BUSY input (SLAVE) and output (MASTER).
2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH.
3. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from Port "A".
6.1432
IDT7016S/L
High-Speed 16K x 9 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Waveform of BUSY Arbitration Controlled by CE Timing(1) (M/S = VIH)
ADDR"A"
and "B"
ADDRESSES MATCH
CE"A"
(2)
tAPS
CE"B"
tBAC
t
BDC
BUSY"B"
3190 drw 15
Waveform of BUSY Arbitration Cycle Controlled by Address Match
Timing(1) (M/S = VIH)
ADDR"A"
ADDR"B"
BUSY"B"
ADDRESS "N"
(2)
tAPS
MATCHING ADDRESS "N"
t
BAA
tBDA
3190 drw 16
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.
2. If tAPS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltageRange(1)
7016X12
7016X15
Com'l Only
Com'l Only
Symbol
Parameter
Min.
Max.
Min. Max.
Unit
INTERRUPT TIMING
____
____
____
____
t
AS
WR
INS
INR
Address Set-up Time
Write Recovery Time
Interrupt Set Time
0
0
ns
ns
ns
t
0
0
____
____
t
12
12
15
15
____
____
t
Interrupt Reset Time
ns
3190 tbl 15a
7016X20
Com'l, Ind
& Military
7016X25
Com'l &
Military
7016X35
Com'l &
Military
Symbol
INTERRUPT TIMING
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
____
____
____
____
____
____
t
AS
WR
INS
INR
Address Set-up Time
Write Recovery Time
Interrupt Set Time
0
0
0
ns
ns
ns
t
0
0
0
____
____
____
t
20
20
20
20
25
25
____
____
____
t
Interrupt Reset Time
ns
3190 tbl 15b
NOTES:
1. 'X' in part numbers indicates power rating (S or L).
14
6.42
IDT7016S/L
High-Speed 16K x 9 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Waveform of Interrupt Timing(1)
tWC
INTERRUPT SET ADDRESS (2)
ADDR"A"
(4)
(3)
tWR
t
AS
CE"A"
R/W"A"
INT"B"
(3)
tINS
3190 drw 17
t
RC
INTERRUPT CLEAR ADDRESS (2)
ADDR"B"
CE"B"
(3)
tAS
OE"B"
(3)
tINR
INT"B"
3190 drw 18
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.
2. See Interrupt truth table.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
Truth Table III — Interrupt Flag(1)
Left Port
Right Port
OE
R/WL
A13L-A0L
R/WR
A
13R-A0R
Function
Set Right INT Flag
Reset Right INT Flag
Set Left INT Flag
Reset Left INT Flag
CEL
OEL
INTL
CER
R
INTR
(2)
L
L
X
X
L
X
X
X
L
3FFF
X
X
X
X
X
L
L
X
X
L
X
3FFF
3FFE
X
L
R
(3)
X
X
H
R
(3)
X
X
L
L
X
X
X
X
L
(2)
X
3FFE
H
X
L
3190 tbl 16
NOTES:
1. Assumes BUSYL = BUSYR = VIH.
2. If BUSYL = VIL, then no change.
3. If BUSYR = VIL, then no change.
6.1452
IDT7016S/L
High-Speed 16K x 9 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Truth Table IV — Address BUSY
Arbitration
Inputs
Outputs
A
OL-A13L
(1)
(1)
A
OR-A13R
Function
Normal
Normal
Normal
CE
L
CE
R
BUSY
L
BUSYR
X
H
X
L
X
X
H
L
NO MATCH
MATCH
H
H
H
H
MATCH
H
H
(3)
MATCH
(2)
(2)
Write Inhibit
3190 tbl 17
NOTES:
1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSYX outputs on the IDT7016 are
push-pull, not open drain outputs. On slaves the BUSYX input internally inhibits writes.
2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address
and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs can not be LOW simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored
when BUSYR outputs are driving LOW regardless of actual logic level on the pin.
Truth Table V — Example of Semaphore Procurement Sequence(1,2,3)
Functions
D0
- D8
Left
D0
- D8
Right
Status
No Action
1
0
0
1
1
0
1
1
1
0
1
1
1
1
0
0
1
1
0
1
1
1
Semaphore free
Left Port Writes "0" to Semaphore
Right Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "1" to Semaphore
Right Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
Left port has semaphore token
No change. Right side has no write access to semaphore
Right port obtains semaphore token
No change. Left port has no write access to semaphore
Left port obtains semaphore token
Semaphore free
Right port has semaphore token
Semaphore free
Left port has semaphore token
Semaphore free
3190 tbl 18
NOTES:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT7016.
2. There are eight semaphore flags written to via I/O0 and read from all I/Os (I/O0 - I/O8). These eight semaphores are addressed by A0 - A2.
e. CE = VIH, SEM = VIL to access the semaphores. Refer to the semaphore Read/Write Truth Table.
FunctionalDescription
where a write is defined as the CE = R/W =VIL per Truth Table III. The
leftportclearstheinterruptbyanaddresslocation3FFEaccesswhenCER
=OER =VIL, R/W is a "don't care". Likewise, the right port interrupt flag
(INTR)isassertedwhentheleftportwritestomemorylocation3FFFand
to clear the interrupt flag (INTR), the right port must access memory
location 3FFF. The message (9 bits) at 3FFE or 3FFF is user-defined
sinceitisinanaddressableSRAMlocation.Iftheinterruptfunctionisnot
used,addresslocations3FFEand3FFF arenotusedasmailboxesbut
arestill partoftherandomaccessmemory.RefertoTruthTableIIIforthe
interruptoperation.
TheIDT7016providestwoportswithseparatecontrol,addressand
I/Opinsthatpermitindependentaccessforreadsorwritestoanylocation
inmemory.TheIDT7016hasanautomaticpowerdownfeaturecontrolled
by CE. The CE controls on-chip power down circuitry that permits the
respectiveporttogointoastandbymodewhennotselected(CEHIGH).
Whenaportisenabled,accesstotheentirememoryarrayispermitted.
Interrupts
Iftheuserchoosestheinterruptfunction,amemorylocation(mailbox
ormessagecenter)is assignedtoeachport. Theleftportinterruptflag
(INTL) is asserted when the right port writes to memory location 3FFE
16
6.42
IDT7016S/L
High-Speed 16K x 9 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
BusyLogic
CE
MASTER
Dual Port
RAM
CE
BusyLogicprovidesahardwareindicationthatbothportsoftheRAM
haveaccessedthesamelocationatthesametime.Italsoallowsoneofthe
twoaccessestoproceedandsignalstheothersidethattheRAMis“busy”.
TheBUSYpincanthenbeusedtostalltheaccessuntiltheoperationon
theothersideiscompleted.Ifawriteoperationhasbeenattemptedfrom
thesidethatreceivesaBUSYindication,thewritesignalisgatedinternally
topreventthewritefromproceeding.
SLAVE
Dual Port
RAM
BUSY (R)
BUSY (L)
BUSY (L) BUSY (R)
MASTER
Dual Port
RAM
CE
SLAVE
Dual Port
RAM
CE
BUSY (R)
BUSY (L) BUSY (R)
BUSY (L) BUSY (R)
BUSY (L)
TheuseofBUSYlogicisnotrequiredordesirableforallapplications.
InsomecasesitmaybeusefultologicallyORtheBUSYoutputstogether
anduse anyBUSYindicationas aninterruptsource toflagthe eventof
anillegalorillogicaloperation.IfthewriteinhibitfunctionofBUSYlogicis
notdesirable,theBUSYlogiccanbedisabledbyplacingthepartinslave
modewiththeM/Spin.OnceinslavemodetheBUSYpinoperatessolely
asawriteinhibitinputpin.Normaloperationcanbeprogrammedbytying
the BUSY pins HIGH. If desired, unintended write operations can be
prevented to a port by tying the BUSY pin for that port LOW.
TheBUSYoutputsontheIDT7016RAMinmastermode,arepush-
pulltypeoutputsanddonotrequirepullupresistorstooperate.Ifthese
RAMs are being expanded in depth, then the BUSY indication for the
resulting array requires the use of an external AND gate.
,
3190 drw 19
Figure 3. Busy and chip enable routing for both width and depth
expansion with IDT7016 RAMs.
leftportinnowayslows theaccess timeoftherightport.Bothports are
identicalinfunctiontostandardCMOSStaticRAMandcanbereadfrom,
orwrittento,atthesametimewiththeonlypossibleconflictarisingfromthe
simultaneous writing of, or a simultaneous READ/WRITE of, a non-
semaphorelocation.Semaphoresareprotectedagainstsuchambiguous
situationsandmaybeusedbythesystemprogramtoavoidanyconflicts
inthenon-semaphoreportionoftheDual-PortRAM.Thesedeviceshave
anautomaticpower-downfeaturecontrolledbyCE,theDual-PortRAM
enable,andSEM,thesemaphoreenable.TheCEandSEMpinscontrol
on-chippowerdowncircuitrythatpermits the respective porttogointo
standbymodewhennotselected. Thisistheconditionwhichisshownin
Truth Table I where CE and SEM are both HIGH.
SystemswhichcanbestusetheIDT7016containmultipleprocessors
or controllers and are typically very high-speed systems which are
softwarecontrolledorsoftwareintensive.Thesesystemscanbenefitfrom
aperformanceincreaseofferedbytheIDT7016'shardwaresemaphores,
whichprovidealockoutmechanismwithoutrequiringcomplexprogram-
ming.
Softwarehandshakingbetweenprocessors offers themaximumin
systemflexibilitybypermittingsharedresourcestobeallocatedinvarying
configurations.TheIDT7016doesnotuseitssemaphoreflagstocontrol
anyresourcesthroughhardware,thusallowingthesystemdesignertotal
flexibilityinsystemarchitecture.
An advantage of using semaphores rather than the more common
methodsofhardwarearbitrationisthatwaitstatesareneverincurredin
either processor. This can prove to be a major advantage in very high-
speedsystems.
WidthExpansionBusyLogic
Master/SlaveArrays
WhenexpandinganIDT7016RAMarrayinwidthwhileusingBUSY
logic,onemasterpartisusedtodecidewhichsideoftheRAMarraywill
receiveaBUSYindication,andtooutputthatindication.Anynumberof
slavestobeaddressedinthesameaddressrangeasthemasterusethe
BUSYsignalasawriteinhibitsignal.ThusontheIDT7016RAMtheBUSY
pinisanoutputifthepartisusedasamaster(M/Spin=H),andtheBUSY
pin is an input if the part used as a slave (M/S pin = L) as shown in
Figure 3.
Iftwoormoremasterpartswereusedwhenexpandinginwidth,asplit
decisioncouldresultwithonemasterindicatingBUSYononesideofthe
arrayandanothermasterindicatingBUSYononeothersideofthearray.
Thiswouldinhibitthewriteoperationsfromoneportforpartofawordand
inhibitthewriteoperationsfromtheotherportfortheotherpartoftheword.
TheBUSYarbitration,onamaster,isbasedonthechipenableand
address signals only. Itignores whetheranaccess is a readorwrite. In
a master/slave array, bothaddress andchipenable mustbe validlong
enoughforaBUSYflagtobeoutputfromthemasterbeforetheactualwrite
pulsecanbeinitiatedwiththeR/Wsignal.Failuretoobservethistimingcan
resultina glitchedinternalwrite inhibitsignalandcorrupteddata inthe
slave.
How the Semaphore Flags Work
Thesemaphorelogicisasetofeightlatcheswhichareindependent
oftheDual-PortRAM.Theselatchescanbeusedtopassaflag,ortoken,
fromoneporttotheothertoindicatethatasharedresourceisinuse.The
semaphores provide a hardware assist for a use assignment method
called“TokenPassingAllocation.”Inthismethod,thestateofasemaphore
latchisusedasatokenindicatingthatsharedresourceisinuse.Iftheleft
processorwantstousethisresource,itrequeststhetokenbysettingthe
latch.Thisprocessorthenverifiesitssuccessinsettingthelatchbyreading
it. If it was successful, it proceeds to assume control over the shared
resource.Ifitwasnotsuccessfulinsettingthelatch,itdeterminesthatthe
rightsideprocessorhassetthelatchfirst, hasthetokenandisusingthe
sharedresource.Theleftprocessorcantheneitherrepeatedlyrequest
that semaphore’s status or remove its request for that semaphore to
Semaphores
The IDT7016 are extremely fast Dual-Port 16Kx9 Static RAMs with
anadditional8addresslocationsdedicatedtobinarysemaphoreflags.
TheseflagsalloweitherprocessorontheleftorrightsideoftheDual-Port
RAMtoclaimaprivilegeovertheotherprocessorforfunctionsdefinedby
thesystemdesigner’ssoftware.Asanexample,thesemaphorecanbe
usedbyoneprocessortoinhibittheotherfromaccessingaportionofthe
Dual-Port RAM or any other shared resource.
The Dual-PortRAMfeatures a fastaccess time, andbothports are
completelyindependentofeachother.Thismeansthattheactivityonthe
6.1472
IDT7016S/L
High-Speed 16K x 9 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
performanothertaskandoccasionallyattemptagaintogaincontrolofthe semaphoreflagwillforceitssideofthesemaphoreflagLOWandtheother
tokenviathesetandtestsequence.Oncetherightsidehasrelinquished sideHIGH.Thisconditionwillcontinueuntilaoneiswrittentothesame
thetoken,theleftsideshouldsucceedingainingcontrol.
semaphorerequestlatch.Shouldtheotherside’ssemaphorerequestlatch
ThesemaphoreflagsareactiveLOW.Atokenisrequestedbywriting havebeenwrittentoazerointhemeantime,thesemaphoreflagwillflip
azerointoasemaphorelatchandisreleasedwhenthesamesidewrites overtotheothersideassoonasaoneiswrittenintothefirstside’srequest
aonetothatlatch.
latch.Thesecondside’sflagwillnowstayLOWuntilitssemaphorerequest
The eightsemaphore flags reside withinthe IDT7016ina separate latchiswrittentoaone.Fromthisitiseasytounderstandthat,ifasemaphore
memoryspacefromtheDual-PortRAM.This addressspaceisaccessed is requestedandthe processorwhichrequesteditnolongerneeds the
byplacingaLOWinputontheSEMpin(whichactsasachipselectforthe resource, the entire system can hang up until a one is written into that
semaphore flags) and using the other control pins (Address, OE, and semaphorerequestlatch.
R/W)as theywouldbe usedinaccessinga standardstaticRAM. Each
The criticalcase ofsemaphore timingis whenbothsides requesta
oftheflagshasauniqueaddresswhichcanbeaccessedbyeitherside single token by attempting to write a zero into it at the same time. The
throughaddresspinsA0–A2.Whenaccessingthesemaphores,noneof semaphorelogicisspeciallydesignedtoresolvethisproblem.Ifsimulta-
theotheraddresspinshasanyeffect.
neousrequestsaremade,thelogicguaranteesthatonlyonesidereceives
Whenwritingtoasemaphore,onlydatapinD0 isused.Ifalowlevel thetoken.Ifonesideisearlierthantheotherinmakingtherequest,thefirst
iswrittenintoanunusedsemaphorelocation,thatflagwillbesettoazero sidetomaketherequestwillreceivethetoken.Ifbothrequestsarriveat
on that side and a one on the other side (see Truth Table V). That thesametime,theassignmentwillbearbitrarilymadetooneportorthe
semaphorecannowonlybemodifiedbythesideshowingthezero.When other.
aoneiswrittenintothesamelocationfromthesameside,theflagwillbe
One caution that should be noted when using semaphores is that
settoaoneforbothsides(unlessasemaphorerequestfromtheotherside semaphoresalonedonotguaranteethataccesstoaresourceissecure.
ispending)andthencanbewrittentobybothsides.Thefactthattheside Aswithanypowerfulprogrammingtechnique,ifsemaphoresaremisused
which is able to write a zero into a semaphore subsequently locks out ormisinterpreted, a software errorcaneasilyhappen.
writes from the other side is what makes semaphore flags useful in
Initializationofthesemaphoresisnotautomaticandmustbehandled
interprocessorcommunications.(Athoroughdiscussionontheuseofthis viatheinitializationprogramatpower-up.Sinceanysemaphorerequest
featurefollowsshortly.)Azerowrittenintothesamelocationfromtheother flagwhichcontainsazeromustberesettoaone,allsemaphoresonboth
side willbe storedinthe semaphore requestlatchforthatside untilthe sidesshouldhaveaonewrittenintothematinitializationfrombothsides
semaphoreisfreedbythefirstside.
to assure that they will be free when needed.
Whenasemaphoreflagisread,itsvalueisspreadintoalldatabitsso
thataflagthatisaonereadsasaoneinalldatabitsandaflagcontaining
azeroreadsasallzeros.Thereadvalueislatchedintooneside’soutput
registerwhenthatside'ssemaphoreselect(SEM)andoutputenable(OE)
signalsgoactive.Thisservestodisallowthesemaphorefromchanging
stateinthemiddleofareadcycleduetoawritecyclefromtheotherside.
Becauseofthislatch,arepeatedreadofasemaphoreinatestloopmust
cause either signal (SEM or OE) to go inactive or the output will never
change.
UsingSemaphores—SomeExamples
Perhapsthesimplestapplicationofsemaphoresistheirapplicationas
resourcemarkersfortheIDT7016’sDual-PortRAM.Saythe16Kx9RAM
wastobedividedintotwo8Kx9blockswhichweretobededicatedatany
onetimetoservicingeithertheleftorrightport.Semaphore0couldbeused
toindicatethesidewhichwouldcontrolthelowersectionofmemory,and
Semaphore 1couldbe definedas the indicatorforthe uppersectionof
memory.
AsequenceWRITE/READmustbeusedbythesemaphoreinorder
to guarantee that no system level contention will occur. A processor
requestsaccesstosharedresourcesbyattemptingtowriteazerointoa
semaphorelocation.Ifthesemaphoreisalreadyinuse,thesemaphore
requestlatchwillcontainazero,yetthesemaphoreflagwillappearasone,
afactwhichtheprocessorwillverifybythesubsequentread(seeTruth
TableV).Asanexample,assumeaprocessorwritesazerototheleftport
atafreesemaphorelocation.Onasubsequentread,theprocessorwill
verifythatithaswrittensuccessfullytothatlocationandwillassumecontrol
overtheresourceinquestion.Meanwhile,ifaprocessorontherightside
attempts towriteazerotothesamesemaphoreflagitwillfail,as willbe
verifiedbythefactthataonewillbereadfromthatsemaphoreontheright
side during subsequent read. Had a sequence of READ/WRITE been
used instead,systemcontentionproblemscouldhaveoccurredduring
the gap between the read and write cycles.
Totakearesource,inthis examplethelower8KofDual-PortRAM,
the processor on the left port could write and then read a zero in to
Semaphore0.Ifthistaskweresuccessfullycompleted(azerowasread
backratherthana one), the leftprocessorwouldassume controlofthe
lower8K.Meanwhiletherightprocessorwasattemptingtogaincontrolof
theresourceaftertheleftprocessor,itwouldreadbackaoneinresponse
tothezeroithadattemptedtowriteintoSemaphore0.Atthis point,the
softwarecouldchoosetotryandgaincontrolofthesecond8Ksectionby
writing,thenreadingazerointoSemaphore1.Ifitsucceededingaining
control,itwouldlockouttheleftside.
Once the left side was finished with its task, it would write a one to
Semaphore 0 and may then try to gain access to Semaphore 1. If
Semaphore1wasstilloccupiedbytherightside,theleftsidecouldundo
itssemaphorerequestandperformothertasksuntilitwasabletowrite,then
readazerointoSemaphore1.Iftherightprocessorperformsasimilartask
withSemaphore0,thisprotocolwouldallowthetwoprocessorstoswap
8Kblocks ofDual-PortRAMwitheachother.
Itisimportanttonotethatafailedsemaphorerequestmustbefollowed
byeitherrepeatedreadsorbywritingaoneintothesamelocation.The
reasonforthisiseasilyunderstoodbylookingatthesimplelogicdiagram
ofthesemaphoreflaginFigure4.Twosemaphorerequestlatchesfeed
into a semaphore flag. Whichever latch is first to present a zero to the
The blocks do not have to be any particular size and can even be
variable, depending upon the complexity of the software using the
18
6.42
IDT7016S/L
High-Speed 16K x 9 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
semaphoreflags.AlleightsemaphorescouldbeusedtodividetheDual- segmentsatfullspeed.
PortRAMorothersharedresources intoeightparts. Semaphores can
Anotherapplicationisintheareaofcomplexdatastructures.Inthis
evenbeassigneddifferentmeaningsondifferentsidesratherthanbeing case,blockarbitrationisveryimportant.Forthisapplicationoneprocessor
given a common meaning as was shown in the example above.
mayberesponsibleforbuildingandupdatingadatastructure.Theother
Semaphores are a useful form of arbitration in systems like disk processorthenreadsandinterpretsthatdatastructure.Iftheinterpreting
interfaceswheretheCPUmustbelockedoutofasectionofmemoryduring processorreadsanincompletedatastructure,amajorerrorconditionmay
atransferandtheI/Odevicecannottolerateanywaitstates.Withtheuse exist.Therefore,somesortofarbitrationmustbeusedbetweenthetwo
ofsemaphores,oncethetwodeviceshasdeterminedwhichmemoryarea differentprocessors.Thebuildingprocessorarbitratesfortheblock,locks
was“off-limits”totheCPU,boththeCPUandtheI/Odevicescouldaccess itandthenisabletogoinandupdatethedatastructure.Whentheupdate
theirassignedportionsofmemorycontinuouslywithoutanywaitstates. is completed, the data structure block is released. This allows the
Semaphoresarealsousefulinapplicationswherenomemory“WAIT” interpretingprocessortocomebackandreadthecompletedatastructure,
stateisavailableononeorbothsides.Onceasemaphorehandshakehas therebyguaranteeingaconsistentdatastructure.
been performed, both processors can access their assigned RAM
L PORT
SEMAPHORE
R PORT
SEMAPHORE
REQUEST FLIP FLOP
REQUEST FLIP FLOP
0
D
0
D
D
D
Q
Q
WRITE
WRITE
SEMAPHORE
READ
SEMAPHORE
,
READ
3190 drw 20
Figure 4. IDT7016 Semaphore Logic
6.1492
IDT7016S/L
High-Speed 16K x 9 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
OrderingInformation
A
XXXXX
A
999
A
A
Device
Type
Power Speed
Package
Process/
Temperature
Range
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
Military (-55°C to +125°C)
Blank
I(1)
B
Compliant to MIL-PRF-38535 QML
G(2)
Green
80-pin TQFP (PN80-1)
68-pin PGA (G68-1)
68-pin PLCC (J68-1)
PF
G
J
12
15
20
25
35
Commercial Only
Commercial Only
Com'l, Ind & Military
Commercial & Military
Commercial & Military
Speed in Nanoseconds
Standard Power
Low Power
S
L
7016
144K (16K x 9) Dual-Port RAM
3190 drw 21
NOTES:
1. Contact your local sales office for industrial temp range for other speeds, packages and powers.
2. Green parts available. For specific speeds, packages and powers contact your local sales office.
DatasheetDocumentHistory
01/11/99:
Initiateddatasheetdocumenthistory
Convertedtonewformat
Cosmeticandtypographicalcorrections
Pages 2 and 3
Page 1
Addedadditionalnotestopinconfigurations
Changeddrawingformat
CorrectedDSCnumber
06/03/99
11/10/99:
05/19/00:
Replaced IDT logo
Increasedstoragetemperatureparameter
ClarifiedTAparameter
Page 4
Page 6
DCElectricalparameters–changedwordingfromopentodisabled
Changed±200mVto0mVinnotes
01/10/02:
Pages 2 & 3
Pages 4, 6, 7, 9 & 12
Pages 6, 7, 9, 12 & 14
Page 20
Pages 1 & 20
Page 1
Addeddaterevisionforpinconfigurations
RemovedIndustrialtempfootnotefromalltables
AddedIndustrialtempfor20nsspeedtoDCandACElectricalCharacteristics
AddedIndustrialtempofferingto20nsorderinginformation
Replaced TM logo with ® logo
Addedgreenavailabilitytofeatures
Addedindicatortoorderinginformation
Removed "IDT" from orderable part number
04/04/06:
01/09/09:
Page 20
Page 20
CORPORATE HEADQUARTERS
for SALES:
for Tech Support:
6024 Silver Creek Valley Road
San Jose, CA 95138
800-345-7015 or 408-284-8200
fax: 408-284-2775
www.idt.com
408-284-2794
DualPortHelp@idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
20
6.42
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