7016S35PFGB_技术文档

HIGH-SPEED

16K X 9 DUAL-PORT

STATIC RAM

IDT7016S/L

◆

IDT7016 easily expands data bus width to 18 bits or

Features

more using the Master/Slave select when cascading

more than one device

M/S = VIH for BUSY output flag on Master

M/S = VIL for BUSY input on Slave

Busy and Interrupt Flag

On-chip port arbitration logic

Full on-chip hardware support of semaphore signaling

between ports

Fully asynchronous operation from either port

TTL-compatible, single 5V (±10%) power supply

Available in ceramic 68-pin PGA, 68-pin PLCC, and an

80-pin TQFP

Industrial temperature range (–40°C to +85°C) is

available for selected speeds

Green parts available, see ordering information

◆

True Dual-Ported memory cells which allow simulta-

neous reads of the same memory location

High-speed access

◆

– Commercial:12/15/20/25/35ns (max.)

– Industrial: 20ns (max.)

◆

– Military: 20/25/35ns (max.)

Low-power operation

◆

– IDT7016S

◆

Active: 750mW (typ.)

Standby: 5mW (typ.)

– IDT7016L

Active: 750mW (typ.)

Standby: 1mW (typ.)

◆

Functional Block Diagram

OEL

OER

CER

CEL

R/WR

R/W

L

I/O0L- I/O8L

I/O0R-I/O8R

I/O

Control

BUSY ^(1,2)

L

(1,2)

BUSY

R

A

13L

A

13R

0R

Address

Decoder

MEMORY

ARRAY

Address

Decoder

A

0L

14

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

CE

OE

L

CE

OE

R/W

R

R/W

L

SEM

L

SEM

R

M/S

(2)

INTL

INT

R

3190 drw 01

NOTES:

1. In MASTER mode: BUSY is an output and is a push-pull driver

InSLAVEmode:BUSYisinput.

2. BUSYoutputsandINToutputsarenon-tri-statedpush-pulldrivers.

OCTOBER2014

1

DSC 3190/11

IDT7016S/L

High-Speed 16K x 9 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

Description

The IDT7016 is a high-speed 16K x 9 Dual-Port Static RAM. The

IDT7016 is designed to be used as stand-alone Dual-Port RAMs or

as a combination MASTER/SLAVE Dual-Port RAM for 18-bit-or-

more wider systems. Using the IDT MASTER/SLAVE Dual-Port

RAM approach in 18-bit or wider memory system applications

results in full-speed, error-free operation without the need for addi-

tional discrete logic.

access for reads or writes to any location in memory. An automatic

power down feature controlled by CE permits the on-chip circuitry of

each port to enter a very low standby power mode.

Fabricated using IDT’s CMOS high-performance technology,

these devices typically operate on only 750mW of power.

The IDT7016 is packaged in a ceramic 68-pin PGA, a 64-pin

PLCC and an 80-pinTQFP (Thin Quad Flatpack). Military grade

product is manufactured in compliance with the latest revision of

MIL-PRF-38535 QML, making it ideally suited to military tempera-

ture applications demanding the highest level of performance and

reliability.

This device provides two independent ports with separate con-

trol, address, and I/O pins that permit independent, asynchronous

Pin Configurations^(1,2,3)

Pin Names

Left Port

Right Port

Names

NOTES:

1. All VCC pins must be connected to power supply.

2. AllGNDpinsmustbeconnectedtogroundsupply.

3. Package body is approximately .95 in x .95 in x .17 in.

4. This package code is used to reference the package diagram.

5. ThistextdoesnotimplyorientationofPart-marking.

Chip Enable

CE

R/W

OE

L

CE

R/W

OE

R

L

R

Read/Write Enable

Output Enable

Address

L

R

A

0L - A13L

A

0R - A13R

I/O0R - I/O8R

SEM

INT

BUSY

M/S

I/O^0L- I/O8L

SEM

INT

BUSY

Data Input/Output

Semaphore Enable

Interrupt Flag

Busy Flag

L

R

L

R

L

R

Master or Slave Select

Power

V

CC

GND

Ground

3190 tbl 01

2

6.42

IDT7016S/L

High-Speed 16K x 9 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

Pin Configurations^(1,2,3)(con't.)

NOTES:

1. All V^CCpins must be connected to power supply.

2. All GND pins must be connected to ground supply.

3. PN80-1 package body is approximately

14mm x 14mm x 1.4mm.

G68-1 package body is approximately

1.18 in x 1.18 in x .16 in.

4. This package code is used to reference the package diagram.

5. This text does not indicate orientation of the actual part-marking.

6.432

IDT7016S/L

High-Speed 16K x 9 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

Truth Table I: Non-Contention Read/Write Control

Inputs⁽¹⁾

R/W

Outputs

I/O^0-8

Mode

CE

H

L

OE

X

SEM

H

X

L

High-Z

DATA^IN

DATAOUT

High-Z

Deselcted: Power-Down

Write to Memory

Read Memory

X

H

L

H

X

L

H

X

H

X

Outputs Disabled

3190 tbl 02

NOTE:

1. Condition: A0L — A13L ≠ A0R — A13R

Truth Table II: Semaphore Read/Write Control⁽¹⁾

Inputs

Outputs

R/W

H

I/O0-8

Mode

- I/O

CE

H

OE

L

SEM

L

DATAOUT

Read Semaphore Flag Data Out (I/O

Write I/O into Semaphore Flag

Not Allowed

0

8)

H

X

DATAIN

0

↑

____

L

X

3190 tbl 03

NOTE:

1. There are eight semaphore flags written to via I/O0 and read from all I/Os (I/O0-I/O8). These eight semaphores are addressed by A0 - A2.

Absolute Maximum Ratings⁽¹⁾

Maximum Operating

Temperature and Supply Volt-

Symbol

Rating

Commercial

& Industrial

Military

Unit

(1)

age

Grade

Ambient

GND

Vcc

(2)

Temperature

V

TERM

Terminal Voltage

with Respect

to GND

-0.5 to +7.0

V

Military

-55^OC to +125^OC

0^OC to +70^OC

0V

5.0V

+

10%

Temperature

Under Bias

-55 to +125

-65 to +150

50

-65 to +135

-65 to +150

50

^oC

Commercial

Industrial

T

BIAS

-40^OC to +85^OC

10%

Storage

Temperature

T

STG

3190 tbl 05

NOTES:

1. ThisistheparameterTA. Thisisthe"instanton"casetemperature.

DC Output

Current

mA

I

OUT

3190 tbl 04

NOTES:

1. StressesgreaterthanthoselistedunderABSOLUTEMAXIMUMRATINGSmaycause

permanentdamagetothedevice.Thisisastressratingonlyandfunctionaloperation

of the device at these or any other conditions above

thoseindicatedintheoperationalsectionsofthisspecificationisnotimplied.Exposure

toabsolutemaximumratingconditionsforextendedperiodsmayaffectreliability.

2. VTERM mustnot exceedVcc+10%formorethan25%ofthecycletimeor10nsmaximum,

and is limited to <20mA for the period of VTERM> Vcc + 10%.

Recommended DC Operating

Conditions

Symbol

Parameter

Min.

Typ.

Max. Unit

V

CC

Supply Voltage

4.5

5.0

5.5

0

V

GND

Ground

0

____

V

IH

IL

Input High Voltage

Input Low Voltage

2.2

6.0⁽²⁾

0.8

____

V

-0.5⁽¹⁾

V

3190 tbl 06

NOTES:

1. VIL >-1.5V for pulse width less than 10ns.

2. VTERM must not exceed Vcc + 10%.

4

6.42

IDT7016S/L

High-Speed 16K x 9 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

Capacitance⁽¹⁾

(TA = +25°C, f = 1.0mhz, for TQFP ONLY)

Symbol

Parameter

Input Capacitance

Output Capacitance

Conditions^{(2 )}

IN = 3dV

OUT = 3dV

Max. Unit

CIN

V

9

pF

COUT

V

10

pF

3190 tbl 07

NOTES:

1. Thisparameterisdeterminedbydevicecharacteristicsbutisnotproductiontested.

2. 3dVreferencestheinterpolatedcapacitancewhentheinputandoutputsignalsswitch

from 0V to 3V or from 3V to 0V .

DC Electrical Characteristics Over the

Operating Temperature and Supply Voltage Range (VCC = 5.0V ± 10%)

7016S

7016L

Symbol

|I^LI

|I^LO

Parameter

Input Leakage Current⁽¹⁾

Output Leakage Current

Output Low Voltage

Test Conditions

Min.

Max.

10

Min.

Max.

Unit

µA

V

___

|

V

CC = 5.5V, VIN = 0V to VCC

5

___

|

10

CE = V^IH, VOUT = 0V to VCC

OL = +4mA

OH = -4mA

V

OL

OH

I

0.4

___

V

Output High Voltage

I

2.4

V

3190 tbl 08

NOTE:

1. At Vcc <2.0V, Inputleakagesareundefined.

Output Loads and AC Test

Conditions

Input Pulse Levels

GND to 3.0V

3ns Max.

1.5V

Input Rise/Fall Times

Input Timing Reference Levels

Output Reference Levels

Output Load

1.5V

Figures 1 and 2

3190 tbl 09

5V

893Ω

DATAOUT

BUSY

INT

DATAOUT

5pF*

30pF

347Ω

,

3190 drw 06

Figure 1. AC Output Test Load

Figure 2. Output Test Load

(for tLZ, tHZ, tWZ, tOW)

*Including scope and jig.

6.452

IDT7016S/L

High-Speed 16K x 9 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range⁽¹⁾(con't.) (VCC = 5.0V ± 10%)

7016X12

Com'l Only

7016X15

Com'l Only

Symbol

Parameter

Test Condition

Version

Typ.⁽²⁾

Max.

Typ.⁽²⁾

Max.

Unit

ICC

Dynamic Operating

Current

(Both Ports Active)

COM'L

S

L

170

325

275

170

310

260

mA

CE = VIL, Outputs Disabled

SEM = VIH

(3)

f = fMAX

____

MIL &

IND

S

L

I

SB1

Standby Current

(Both Ports - TTL

Level Inputs)

COM'L

S

L

25

70

60

25

60

50

mA

CE

SEM

f = fMAX

R

= CE

L

= VIH

R

= SEM

L

(3)

____

MIL &

IND

S

L

(5)

ISB2

Standby Current

(One Port - TTL

Level Inputs)

COM'L

S

L

105

200

170

105

190

160

CE^"A"= VIL and CE"B" = VIH

Active Port Outputs Disabled,

(3)

f=fMAX

____

MIL &

IND

S

L

SEM

R

= SEM

L

= VIH

ISB3

Full Standby Current

(Both Ports - All CMOS

Level Inputs)

Both Ports CE

L

and

COM'L

S

L

1.0

0.2

15

5

1.0

0.2

15

5

CE

R

> VCC - 0.2V

IN > VCC - 0.2V or

IN < 0.2V, f = 0⁽⁴⁾

= SEM > VCC - 0.2V

V

____

MIL &

IND

S

L

SEMR

L

ISB4

Full Standby Current

(One Port - All CMOS

Level Inputs)

COM'L

S

L

100

180

150

100

170

140

CE^"A"< 0.2V and

CE^"B"> VCC - 0.2V⁽⁵⁾

SEM

R

= SEML > VCC - 0.2V

____

MIL &

IND

S

L

V

IN > VCC - 0.2V or VIN < 0.2V

Active Port Outputs Disabled

f = fMAX

(3)

3190 tbl 10

7016X20

Com'l, Ind

& Military

7016X25

Com'l &

Military

7016X35

Com'l &

Military

Symbol

Parameter

Test Condition

Version

COM'L

Typ.⁽²⁾

Max.

Typ.⁽²⁾

Max.

Typ.⁽²⁾

Max.

Unit

ICC

Dynamic Operating Current

(Both Ports Active)

S

L

160

290

240

155

265

220

150

250

210

mA

CE = V^IL, Outputs Disabled

SEM = V^IH

(3)

f = fMAX

MIL &

IND

S

L

160

380

310

155

340

280

150

300

250

I

SB1

Standby Current

(Both Ports - TTL

Level Inputs)

COM'L

S

L

20

60

50

16

60

50

13

60

50

mA

CE

R

SEM

= CE = VIH

R

= S^LEM

L

= VIH

(3)

f = fMAX

MIL &

IND

S

L

20

80

65

16

80

65

13

80

65

(5)

ISB2

Standby Current

(One Port - TTL

Level Inputs)

COM'L

S

L

95

180

150

90

170

140

85

155

130

CE^"A"= VIL and CE"B" = VIH

Active Port Outputs Disabled,

(3)

f=f^MAX

SEM

MIL &

IND

S

L

95

240

210

90

215

180

85

190

160

R

= SEM

L

= VIH

ISB3

Full Standby Current

(Both Ports - All CMOS

Level Inputs)

Both Ports CE

L

and

COM'L

S

L

1.0

0.2

15

5

1.0

0.2

15

5

1.0

0.2

15

5

CE

R

> VCC - 0.2V

IN > VCC - 0.2V or

IN < 0.2V, f = 0⁽⁴⁾

= SEM > VCC - 0.2V

V

MIL &

IND

S

L

1.0

0.2

30

10

1.0

0.2

30

10

1.0

0.2

30

10

SEM

R

L

ISB4

Full Standby Current

(One Port - All CMOS Level

Inputs)

COM'L

S

L

90

155

130

85

145

120

80

135

110

CE"A" < 0.2V and

CE^"B"> VCC - 0.2V⁽⁵⁾

SEM

R

= SEML > VCC - 0.2V

MIL &

IND

S

L

90

230

200

85

200

170

80

175

150

V

IN > VCC - 0.2V or VIN < 0.2V

Active Port Outputs Disabled

(3)

f = f^MAX

3190 tbl 11

NOTES:

1. 'X' in part numbers indicates power rating (S or L)

2. VCC = 5V, TA = +25°C, and are not production tested. ICCDC = 120mA(typ.)

3. Atf=fMAX, address and I/Os are cycling at the maximum frequency read cycle of 1/tRC.

4. f = 0 means no address or control lines change.

5. Port "A" may be either left or right port. Port "B" is the opposite of Port "A".

6

6.42

IDT7016S/L

High-Speed 16K x 9 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

AC Electrical Characteristics Over the

Operating Temperature and Supply Voltage Range⁽⁴⁾

7016X12

7016X15

Com'l Only

Symbol

Parameter

Min.

Max.

Min.

Max.

Unit

READ CYCLE

____

t

RC

AA

ACE

AOE

OH

LZ

HZ

PU

PD

SOP

SAA

Read Cycle Time

12

15

ns

____

t

Address Access Time

12

15

Chip Enable Access Time⁽³⁾

Output Enable Access Time

Output Hold from Address Change

Output Low-Z Time^(1,2)

____

t

8

10

____

t

3

____

t

3

Output High-Z Time^(1,2)

10

____

t

Chip Enable to Power Up Time⁽²⁾

Chip Disable to Power Down Time⁽²⁾

0

____

t

12

15

____

t

Semaphore Flag Update Pulse (OE or SEM)

10

____

t

Semaphore Address Access Time

12

15

ns

3190 tbl 12a

7016X20

Com'l, Ind

& Military

7016X25

Com'l &

Military

7016X35

Com'l &

Military

Symbol

READ CYCLE

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

____

t

RC

AA

ACE

AOE

OH

LZ

HZ

PU

PD

SOP

SAA

Read Cycle Time

20

25

35

ns

____

t

Address Access Time

20

25

35

Chip Enable Access Time⁽³⁾

Output Enable Access Time

Output Hold from Address Change

Output Low-Z Time^(1,2)

____

t

12

13

20

____

t

3

____

t

3

Output High-Z Time^(1,2)

12

15

20

____

t

Chip Enable to Power Up Time⁽²⁾

Chip Disable to Power Down Time⁽²⁾

Semaphore Flag Update Pulse (OE or SEM)

Semaphore Address Access Time

0

____

t

20

25

35

____

t

10

____

t

20

25

35

ns

3190 tbl 12b

NOTES:

1. Transition is measured 0mV from Low- or High-impedance voltage with Output Test Load (Figure 2).

2. Thisparameterisguaranteedbydevicecharacterizationbutnotproductiontested.

3. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL.

4. 'X' in part numbers indicates power rating (S or L).

6.472

IDT7016S/L

High-Speed 16K x 9 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

Waveform of Read Cycles⁽⁵⁾

tRC

ADDR

(4)

t

AA

(4)

ACE

CE

OE

(4)

t

AOE

R/W

DATA_OUT

BUSYOUT

NOTES:

(1)

t

OH

tLZ

(4)

VALID DATA

(2)

t

HZ

(3,4)

3190 drw 07

t

BDD

1. Timing depends on which signal is asserted last,OEor CE.

2. Timing depends on which signal is de-asserted first, CEor OE.

3. tBDDdelayisrequiredonlyincaseswheretheoppositeportiscompletingawriteoperationtothesameaddresslocation. ForsimultaneousreadoperationsBUSY hasnorelation

tovalidoutputdata.

4. Startofvaliddatadependsonwhichtimingbecomeseffectivelast:tAOE,tACE,tAA ortBDD.

5. SEM = VIH.

Timing of Power-Up / Power-Down

CE

t

PU

tPD

I

CC

50%

I

SB

,

3190 drw 08

8

6.42

IDT7016S/L

High-Speed 16K x 9 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

AC Electrical Characteristics Over the

Operating Temperature and Supply Voltage⁽⁵⁾

7016X12

Com'l Only

7016X15

Com'l Only

Symbol

Parameter

Min.

Max.

Min.

Max.

Unit

WRITE CYCLE

____

t

WC

EW

AW

AS

WP

WR

DW

HZ

DH

WZ

OW

SWRD

SPS

Write Cycle Time

12

10

0

15

12

0

ns

t

Chip Enable to End-of-Write⁽³⁾

Address Valid to End-of-Write

Address Set-up Time⁽³⁾

Write Pulse Width

t

10

2

12

2

t

Write Recovery Time

Data Valid to End-of-Write

Output High-Z Time^(1,2)

Data Hold Time⁽⁴⁾

t

10

____

t

10

____

t

0

(1,2)

____

t

Write Enable to Output in High-Z

Output Active from End-of-Write^{(1, 2,4)}

SEM Flag Write to Read Time

SEM Flag Contention Window

10

____

t

3

5

3

5

____

t

ns

3190 tbl 13a

7016X20

Com'l, Ind

& Military

7016X25

Com'l &

Military

7016X35

Com'l &

Military

Symbol

WRITE CYCLE

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

____

t

WC

EW

AW

AS

WP

WR

DW

HZ

DH

WZ

OW

SWRD

SPS

Write Cycle Time

20

15

0

25

20

0

35

30

0

ns

t

Chip Enable to End-of-Write⁽³⁾

Address Valid to End-of-Write

Address Set-up Time⁽³⁾

Write Pulse Width

t

15

2

20

2

25

2

t

Write Recovery Time

Data Valid to End-of-Write

Output High-Z Time^(1,2)

Data Hold Time⁽⁴⁾

t

15

____

t

12

15

20

____

t

0

(1,2)

____

t

Write Enable to Output in High-Z

12

15

20

t

Output Active from End-of-Write^{(1, 2,4)}

SEM Flag Write to Read Time

SEM Flag Contention Window

3

5

3

5

3

5

____

t

ns

3190 tbl 13b

NOTES:

1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).

2. Thisparameterisguaranteedbydevicecharacterizationbutnotproductiontested.

3. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time.

4. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage

andtemperature,theactualtDH willalwaysbesmallerthantheactualtOW.

5. 'X' in part numbers indicates power rating (S or L).

6.492

IDT7016S/L

High-Speed 16K x 9 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

Timing Waveform of Write Cycle No. 1, R/W Controlled Timing^(1,5,8)

t

WC

ADDRESS

(7)

t

HZ

OE

t

AW

CE or SEM⁽⁹⁾

(3)

(2)

(6)

t

WR

t

AS

tWP

R/W

(7)

t

LZ

t

OW

t

WZ

(4)

OUT

DATA

t

DW

t

DH

IN

DATA

3190 drw 09

Timing Waveform of Write Cycle No. 2, CE Controlled Timing^(1,5)

t

WC

ADDRESS

t

AW

CE or SEM⁽⁹⁾

R/W

(6)

AS

(3)

(2)

t

WR

t

tEW

t

DW

tDH

DATAIN

3190 drw 10

NOTES:

1. R/W or CE must be HIGH during all address transitions.

2. A write occurs during the overlap (tEW or tWP) of a LOW CE and a LOW R/W for memory array writing cycle.

3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle.

4. Duringthisperiod, theI/Opinsareintheoutputstateandinputsignalsmustnotbeapplied.

5. IftheCEorSEMLOWtransitionoccurssimultaneouslywithoraftertheR/WLOWtransition,theoutputsremainintheHigh-impedancestate.

6. Timing depends on which enable signal is asserted last, CE or R/W.

7. Thisparameterisguaranteedbydevicecharacterizationbutisnotproductiontested. Transitionismeasured0mVfromsteadystatewiththeOutputTestLoad(Figure2).

8. If OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be

placedonthebusfortherequiredtDW.IfOEisHIGHduringanR/Wcontrolledwritecycle, thisrequirementdoesnotapplyandthewritepulsecanbeasshortasthespecifiedtWP.

9. To access RAM, CE = VIL andSEM = VIH. To access Semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition.

10

6.42

IDT7016S/L

High-Speed 16K x 9 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

Timing Waveform of Semaphore Read after Write Timing, Either

Side⁽¹⁾

tSAA

VALID ADDRESS

t

A0-A2

tWR

tAW

ACE

tEW

SEM

t

OH

t

DW

tSOP

DATAIN

VALID

DATAOUT

VALID⁽²⁾

I/O

tAS

tWP

tDH

R/W

tAOE

tSWRD

OE

Read Cycle

Write Cycle

3190 drw 11

NOTES:

1. CE = VIH for the duration of the above timing (both write and read cycle).

2. “DATAOUT VALID” represents all I/O's (I/O0-I/O8) equal to the semaphore value.

Timing Waveform of Semaphore Write Condition^(1,3,4)

A0"A"-A2 "A"

MATCH

SIDE⁽²⁾"A"

R/W"A"

SEM"A"

tSPS

A0"B"-A2 "B"

MATCH

SIDE⁽²⁾

"B"

R/W"B"

SEM"B"

3190 drw 12

NOTES:

1. DOR = DOL =VIH, CER = CEL =VIH.

2. All timing is the same for left and right ports. Port“A” may be either left or right port. “B” is the opposite port from “A”.

3. This parameter is measured from R/W^“A”or SEM“A” going HIGH to R/W“B” or SEM“B” going HIGH.

4. IftSPS isnotsatisfied,thereisnoguaranteewhichsidewillobtainthesemaphoreflag.

6.1412

IDT7016S/L

High-Speed 16K x 9 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

AC Electrical Characteristics Over the

Operating Temperature and Supply Voltage Range⁽⁶⁾

7016X12

7016X15

Com'l Only

Symbol

BUSY TIMING (M/S = V^IH

Parameter

Min.

Max.

Min.

Max.

Unit

)

____

t

BAA

BDA

BAC

BDC

APS

BDD

WH

12

15

ns

BUSY Access Time from Address Match

t

BUSY Disable Time from Address Not Matched

BUSY Access Time from Chip Enable Low

BUSY Disable Time from Chip Enable High

Arbitration Priority Set-up Time⁽²⁾

t

12

15

____

t

5

____

BUSY Disable to Valid Data⁽³⁾

t

15

18

(5)

____

t

Write Hold After BUSY

11

13

BUSY INPUT TIMING (M/S = V^IL

)

____

BUSY Input to Write⁽⁴⁾

t

WB

0

ns

(5)

tWH

Write Hold After BUSY

11

13

PORT-TO-PORT DELAY TIMING

____

t

WDD

Write Pulse to Data Delay⁽¹⁾

25

20

30

25

ns

tDDD

Write Data Valid to Read Data Delay⁽¹⁾

ns

3190 tbl 14a

7016X20

Com'l, Ind

& Military

7016X25

Com'l &

Military

7016X35

Com'l &

Military

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

BUSY TIMING (M/S = VIH

)

____

t

BAA

BDA

BAC

BDC

APS

BDD

WH

20

ns

BUSY Access Time from Address Match

BUSY Disable Time from Address Not Matched

BUSY Access Time from Chip Enable Low

BUSY Disable Time from Chip Enable High

Arbitration Priority Set-up Time⁽²⁾

BUSY Disable to Valid Data⁽³⁾

t

17

20

____

t

5

____

t

30

35

(5)

____

t

Write Hold After BUSY

15

17

25

BUSY INPUT TIMING (M/S = V^IL

)

____

BUSY Input to Write⁽⁴⁾

t

WB

0

ns

(5)

tWH

Write Hold After BUSY

15

17

25

PORT-TO-PORT DELAY TIMING

____

t

WDD

Write Pulse to Data Delay⁽¹⁾

45

30

50

35

60

45

ns

tDDD

Write Data Valid to Read Data Delay⁽¹⁾

ns

3190 tbl 14b

NOTES:

1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveformof Write with Port-to-Port Read and BUSY(M/S= VIH)".

2. To ensure that the earlier of the two ports wins.

3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual).

4. To ensure that the write cycle is inhibited on Port "B" during contention on Port "A".

5. To ensure that a write cycle is completed on Port "B" after contention on Port "A".

6. 'X' in part numbers indicates power rating (S or L).

12

6.42

IDT7016S/L

High-Speed 16K x 9 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

Timing Waveform of Read with BUSY^(2,4,5)(M/S = VIH)

tWC

MATCH

ADDR"A"

tWP

R/W"A"

t

DH

t

DW

VALID

DATAIN "A"

(1)

t

APS

MATCH

ADDR"B"

t

BDD

tBDA

BUSY"B"

t

WDD

DATAOUT "B"

VALID

(3)

t

DDD

3190 drw 13

NOTES:

1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S=VIL.

2. CE^L= CER = VIL.

3. OE = VIL for the reading port.

4. If M/S=VIL (SLAVE), BUSY is an input. Then for this example BUSY“A” = VIH and BUSY“B” input is shown above.

5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from Port "A".

Timing Waveform of Write with BUSY⁽³⁾

tWP

R/W"A"

t

WB

BUSY"B"

(1)

t

WH

R/W"B"

(2)

3190 drw 14

NOTES:

1. tWH mustbemetforbothBUSYinput(SLAVE)andoutput(MASTER).

2. BUSYis asserted on port "B" blocking R/W^"B", until BUSY"B" goesHIGH.

3. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from Port "A".

6.1432

IDT7016S/L

High-Speed 16K x 9 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

Waveform of BUSY Arbitration Controlled by CE Timing⁽¹⁾(M/S = VIH)

ADDR"A"

and "B"

ADDRESSES MATCH

CE"A"

(2)

tAPS

CE"B"

tBAC

t

BDC

BUSY"B"

3190 drw 15

Waveform of BUSY Arbitration Cycle Controlled by Address Match

Timing⁽¹⁾(M/S = VIH)

ADDR"A"

ADDR"B"

BUSY"B"

ADDRESS "N"

(2)

tAPS

MATCHING ADDRESS "N"

t

BAA

tBDA

3190 drw 16

NOTES:

1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.

2. If tAPS is not satisfied, theBUSY signal will be asserted on one side or another but there is no guarantee on which sideBUSY will be asserted.

AC Electrical Characteristics Over the

Operating Temperature and Supply Voltage Range⁽¹⁾

7016X12

7016X15

Com'l Only

Symbol

Parameter

Min.

Max.

Min. Max.

Unit

INTERRUPT TIMING

____

t

AS

WR

INS

INR

Address Set-up Time

Write Recovery Time

Interrupt Set Time

0

ns

t

0

____

t

12

15

____

t

Interrupt Reset Time

ns

3190 tbl 15a

7016X20

Com'l, Ind

& Military

7016X25

Com'l &

Military

7016X35

Com'l &

Military

Symbol

INTERRUPT TIMING

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

____

t

AS

WR

INS

INR

Address Set-up Time

Write Recovery Time

Interrupt Set Time

0

ns

t

0

____

t

20

25

____

t

Interrupt Reset Time

ns

3190 tbl 15b

NOTE:

1. 'X' in part numbers indicates power rating (S or L).

14

6.42

IDT7016S/L

High-Speed 16K x 9 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

Waveform of Interrupt Timing⁽¹⁾

tWC

INTERRUPT SET ADDRESS ⁽²⁾

ADDR"A"

(4)

(3)

tWR

t

AS

CE"A"

R/W"A"

INT"B"

(3)

tINS

3190 drw 17

t

RC

INTERRUPT CLEAR ADDRESS ⁽²⁾

ADDR"B"

CE"B"

(3)

tAS

OE"B"

(3)

tINR

INT"B"

3190 drw 18

NOTES:

1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.

2. SeeInterrupttruthtable.

3. Timing depends on which enable signal (CE or R/W) is asserted last.

4. Timing depends on which enable signal (CE or R/W) is de-asserted first.

Truth Table III — Interrupt Flag⁽¹⁾

Left Port

Right Port

OE

R/W

L

A13L-A0L

R/WR

A

13R-A0R

Function

Set Right INT Flag

Reset Right INT Flag

Set Left INT Flag

Reset Left INT Flag

CEL

OEL

INTL

CER

R

INTR

L

X

L

X

L

X

3FFF

X

L

X

L

X

L⁽²⁾

H⁽³⁾

X

R

X

3FFF

3FFE

X

R

X

L⁽³⁾

H⁽²⁾

L

X

L

3FFE

X

L

3190 tbl 16

NOTES:

1. Assumes BUSY^L= BUSYR = VIH.

2. If BUSY^L= VIL, then no change.

3. If BUSY^R= VIL, then no change.

6.1452

IDT7016S/L

High-Speed 16K x 9 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

Truth Table IV — Address BUSY

Arbitration

Inputs

Outputs

A

OL-A13L

(1 )

(1)

A

OR-A13R

Function

Normal

CE

L

CE

R

BUSY

L

BUSYR

X

H

X

L

X

H

L

NO MATCH

MATCH

H

MATCH

H

MATCH

(2)

Write Inhibit^{(3 )}

3190 tbl 17

NOTES:

1. PinsBUSY^LandBUSYR arebothoutputswhenthepartisconfiguredasamaster. Bothareinputswhenconfiguredasaslave.BUSYX outputsontheIDT7016arepush-pull, not

opendrainoutputs.OnslavestheBUSY^Xinputinternallyinhibitswrites.

2. "L"iftheinputstotheoppositeportwerestablepriortotheaddressandenableinputsofthisport. "H"iftheinputsto theoppositeportbecamestableaftertheaddressandenable

inputsofthisport.IftAPS isnotmet, eitherBUSYL orBUSYR =LOWwillresult. BUSYL andBUSYR outputscannotbe LOWsimultaneously.

3. WritestotheleftportareinternallyignoredwhenBUSY^LoutputsaredrivingLOWregardlessofactuallogiclevelonthepin.WritestotherightportareinternallyignoredwhenBUSYR

outputs are drivingLOW regardless of actual logic level on the pin.

Truth Table V — Example of Semaphore Procurement Sequence^(1,2,3)

Functions

D0

- D8

Left

D0

- D8

Right

Status

No Action

1

0

1

0

1

Semaphore free

Left Port Writes "0" to Semaphore

Right Port Writes "0" to Semaphore

Left Port Writes "1" to Semaphore

Left Port Writes "0" to Semaphore

Right Port Writes "1" to Semaphore

Left Port Writes "1" to Semaphore

Right Port Writes "0" to Semaphore

Right Port Writes "1" to Semaphore

Left Port Writes "0" to Semaphore

Left Port Writes "1" to Semaphore

0

1

0

1

0

1

Left port has semaphore token

No change. Right side has no write access to semaphore

Right port obtains semaphore token

No change. Left port has no write access to semaphore

Left port obtains semaphore token

Semaphore free

Right port has semaphore token

Semaphore free

Left port has semaphore token

Semaphore free

3190 tbl 18

NOTES:

1. This table denotes a sequence of events for only one of the eight semaphores on the IDT7016.

2. There are eight semaphore flags written to via I/O0 and read from all I/Os (I/O0 - I/O8). These eight semaphores are addressed by A0 - A2.

e. CE= VIH, SEM= VIL to access the semaphores. Refer to the semaphore Read/Write Truth Table.

Functional Description

interrupt flag (INTL) is asserted when the right port writes to memory

location 3FFE where a write is defined as the CE = R/W = VIL per

Truth Table III. The left port clears the interrupt by an address location

3FFE access when CER =OER =VIL, R/W is a "don't care". Likewise,

the right port interrupt flag (INTR) is asserted when the left port writes

to memory location 3FFF and to clear the interrupt flag (INTR), the

right port must access memory location 3FFF. The message (9 bits)

at 3FFE or 3FFF is user-defined since it is in an addressable SRAM

location. If the interrupt function is not used, address locations 3FFE

and 3FFF are not used as mail boxes but are still part of the random

The IDT7016 provides two ports with separate control, address

and I/O pins that permit independent access for reads or writes to any

location in memory. The IDT7016 has an automatic power down

feature controlled by CE. The CE controls on-chip power down

circuitry that permits the respective port to go into a standby mode

when not selected (CE HIGH). When a port is enabled, access to the

entire memory array is permitted.

Interrupts

If the user chooses the interrupt function, a memory location access memory. Refer to Truth Table III for the interrupt opera-

(mail box or message center) is assigned to each port. The left port tion.

16

6.42

IDT7016S/L

High-Speed 16K x 9 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

Busy Logic

CE

MASTER

Dual Port

RAM

Busy Logic provides a hardware indication that both ports of the

RAM have accessed the same location at the same time. It also

allows one of the two accesses to proceed and signals the other side

that the RAM is “busy”. The BUSY pin can then be used to stall the

access until the operation on the other side is completed. If a write

operation has been attempted from the side that receives a BUSY

indication, the write signal is gated internally to prevent the write from

proceeding.

CE

SLAVE

Dual Port

RAM

BUSY (R)

BUSY (L)

BUSY (L) BUSY (R)

MASTER

Dual Port

RAM

CE

SLAVE

Dual Port

RAM

CE

BUSY (R)

BUSY (L) BUSY (R)

BUSY (L)

The use of BUSY logic is not required or desirable for all

applications. In some cases it may be useful to logically OR the

BUSY outputs together and use any BUSY indication as an interrupt

source to flag the event of an illegal or illogical operation. If the write

inhibit function of BUSY logic is not desirable, the BUSY logic can be

disabled by placing the part in slave mode with the M/S pin. Once in

slave mode the BUSY pin operates solely as a write inhibit input pin.

Normal operation can be programmed by tying the BUSY pins

HIGH. If desired, unintended write operations can be prevented to a

port by tying the BUSY pin for that port LOW.

The BUSY outputs on the IDT7016 RAM in master mode, are

push-pull type outputs and do not require pull up resistors to operate.

If these RAMs are being expanded in depth, then the BUSY

indication for the resulting array requires the use of an external AND

gate.

3190 drw 19

Figure 3. Busy and chip enable routing for both width and depth expansion

with IDT7016 RAMs.

example, the semaphore can be used by one processor to inhibit

the other from accessing a portion of the Dual-Port RAM or any other

shared resource.

The Dual-Port RAM features a fast access time, and both ports

are completely independent of each other. This means that the

activity on the left port in no way slows the access time of the right port.

Both ports are identical in function to standard CMOS Static RAM and

can be read from, or written to, at the same time with the only possible

conflict arising from the simultaneous writing of, or a simultaneous

READ/WRITE of, a non-semaphore location. Semaphores are

protected against such ambiguous situations and may be used by

the system program to avoid any conflicts in the non-semaphore

portion of the Dual-Port RAM. These devices have an automatic

power-down feature controlled by CE, the Dual-Port RAM enable,

and SEM, the semaphore enable. The CE and SEM pins control on-

chip power down circuitry that permits the respective port to go into

standby mode when not selected. This is the condition which is

shown in Truth Table I where CE and SEM are both HIGH.

Systems which can best use the IDT7016 contain multiple

processors or controllers and are typically very high-speed systems

which are software controlled or software intensive. These systems

can benefit from a performance increase offered by the IDT7016's

hardware semaphores, which provide a lockout mechanism without

requiring complex programming.

Software handshaking between processors offers the maximum

in system flexibility by permitting shared resources to be allocated in

varying configurations. The IDT7016 does not use its semaphore

flags to control any resources through hardware, thus allowing the

system designer total flexibility in system architecture.

An advantage of using semaphores rather than the more

common methods of hardware arbitration is that wait states are

never incurred in either processor. This can prove to be a major

advantage in very high-speed systems.

Width Expansion Busy Logic

Master/Slave Arrays

When expanding an IDT7016 RAM array in width while using

BUSY logic, one master part is used to decide which side of the RAM

array will receive a BUSYindication, and to output that indication. Any

number of slaves to be addressed in the same address range as the

master use the BUSY signal as a write inhibit signal. Thus on the

IDT7016 RAM the BUSY pin is an output if the part is used as a

master (M/S pin = H), and the BUSY pin is an input if the part used

as a slave (M/S pin = L) as shown in Figure 3.

If two or more master parts were used when expanding in width,

a split decision could result with one master indicating BUSY on one

side of the array and another master indicating BUSY on one other

side of the array. This would inhibit the write operations from one port

for part of a word and inhibit the write operations from the other port

for the other part of the word.

The BUSY arbitration, on a master, is based on the chip enable

and address signals only. It ignores whether an access is a read or

write. In a master/slave array, both address and chip enable must

be valid long enough for a BUSY flag to be output from the master

before the actual write pulse can be initiated with the R/W signal.

Failure to observe this timing can result in a glitched internal write

inhibit signal and corrupted data in the slave.

How the Semaphore Flags Work

The semaphore logic is a set of eight latches which are indepen-

dent of the Dual-Port RAM. These latches can be used to pass a flag,

or token, from one port to the other to indicate that a shared resource

is in use. The semaphores provide a hardware assist for a use

assignmentmethodcalled“TokenPassingAllocation.”Inthismethod,

the state of a semaphore latch is used as a token indicating that

shared resource is in use. If the left processor wants to use this

Semaphores

The IDT7016 are extremely fast Dual-Port 16Kx9 Static RAMs

with an additional 8 address locations dedicated to binary sema-

phore flags. These flags allow either processor on the left or right side

of the Dual-Port RAM to claim a privilege over the other processor

for functions defined by the system designer’s software. As an

6.1472

IDT7016S/L

High-Speed 16K x 9 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

resource, it requests the token by setting the latch. This processor resource in question. Meanwhile, if a processor on the right side

then verifies its success in setting the latch by reading it. If it was attempts to write a zero to the same semaphore flag it will fail, as will

successful, it proceeds to assume control over the shared resource. be verified by the fact that a one will be read from that semaphore on

If it was not successful in setting the latch, it determines that the right the right side during subsequent read. Had a sequence of READ/

side processor has set the latch first, has the token and is using the WRITE been used instead, system contention problems could have

shared resource. The left processor can then either repeatedly occurred during the gap between the read and write cycles.

request that semaphore’s status or remove its request for that

It is important to note that a failed semaphore request must be

semaphore to perform another task and occasionally attempt again followed by either repeated reads or by writing a one into the same

to gain control of the token via the set and test sequence. Once the location. The reason for this is easily understood by looking at the

right side has relinquished the token, the left side should succeed in simple logic diagram of the semaphore flag in Figure 4.Two

gaining control.

semaphore request latches feed into a semaphore flag. Whichever

The semaphore flags are active LOW. A token is requested by latch is first to present a zero to the semaphore flag will force its side

writing a zero into a semaphore latch and is released when the same of the semaphore flag LOW and the other side HIGH. This condition

side writes a one to that latch.

will continue until a one is written to the same semaphore request

The eight semaphore flags reside within the IDT7016 in a latch. Should the other side’s semaphore request latch have been

separate memory space from the Dual-Port RAM. This address written to a zero in the meantime, the semaphore flag will flip over to

space is accessed by placing a LOW input on the SEM pin (which the other side as soon as a one is written into the first side’s request

acts as a chip select for the semaphore flags) and using the other latch. The second side’s flag will now stay LOW until its semaphore

control pins (Address, OE, and R/W) as they would be used in request latch is written to a one. From this it is easy to understand that,

accessing a standard static RAM. Each of the flags has a unique if a semaphore is requested and the processor which requested it no

address which can be accessed by either side through address pins longer needs the resource, the entire system can hang up until a one

A0 – A2. When accessing the semaphores, none of the other is written into that semaphore request latch.

address pins has any effect.

The critical case of semaphore timing is when both sides request

When writing to a semaphore, only data pin D0 is used. If a low a single token by attempting to write a zero into it at the same time.

level is written into an unused semaphore location, that flag will be set The semaphore logic is specially designed to resolve this problem.

to a zero on that side and a one on the other side (see Truth Table If simultaneous requests are made, the logic guarantees that only

V). That semaphore can now only be modified by the side showing one side receives the token. If one side is earlier than the other in

the zero. When a one is written into the same location from the same making the request, the first side to make the request will receive the

side, the flag will be set to a one for both sides (unless a semaphore token. If both requests arrive at the same time, the assignment will

request from the other side is pending) and then can be written to by be arbitrarily made to one port or the other.

both sides. The fact that the side which is able to write a zero into a

One caution that should be noted when using semaphores is that

semaphore subsequently locks out writes from the other side is what semaphores alone do not guarantee that access to a resource is

makes semaphore flags useful in interprocessor communications. secure. As with any powerful programming technique, if sema-

(A thorough discussion on the use of this feature follows shortly.) A phores are misused or misinterpreted, a software error can easily

zero written into the same location from the other side will be stored happen.

in the semaphore request latch for that side until the semaphore is

freed by the first side.

Initialization of the semaphores is not automatic and must be

handled via the initialization program at power-up. Since any

When a semaphore flag is read, its value is spread into all data semaphore request flag which contains a zero must be reset to a

bits so that a flag that is a one reads as a one in all data bits and a one, all semaphores on both sides should have a one written into

flag containing a zero reads as all zeros. The read value is latched them at initialization from both sides to assure that they will be free

into one side’s output register when that side's semaphore select when needed.

(SEM) and output enable (OE) signals go active. This serves to

disallow the semaphore from changing state in the middle of a read

cycle due to a write cycle from the other side. Because of this latch,

Perhaps the simplest application of semaphores is their applica-

a repeated read of a semaphore in a test loop must cause either

UsingSemaphores-SomeExamples

tion as resource markers for the IDT7016’s Dual-Port RAM. Say the

16K x 9 RAM was to be divided into two 8K x 9 blocks which were to

signal (SEM or OE) to go inactive or the output will never change.

A sequence WRITE/READ must be used by the semaphore in

be dedicated at any one time to servicing either the left or right port.

order to guarantee that no system level contention will occur. A

Semaphore 0 could be used to indicate the side which would control

processor requests access to shared resources by attempting to

the lower section of memory, and Semaphore 1 could be defined as

write a zero into a semaphore location. If the semaphore is already

the indicator for the upper section of memory.

in use, the semaphore request latch will contain a zero, yet the

To take a resource, in this example the lower 8K of Dual-Port

semaphore flag will appear as one, a fact which the processor will

RAM, the processor on the left port could write and then read a zero

verify by the subsequent read (see Truth Table V). As an example,

in to Semaphore 0. If this task were successfully completed (a zero

assume a processor writes a zero to the left port at a free semaphore

was read back rather than a one), the left processor would assume

location. On a subsequent read, the processor will verify that it has

control of the lower 8K. Meanwhile the right processor was attempt-

written successfully to that location and will assume control over the

18

6.42

IDT7016S/L

High-Speed 16K x 9 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

ing to gain control of the resource after the left processor, it would interfaces where the CPU must be locked out of a section of memory

read back a one in response to the zero it had attempted to write into during a transfer and the I/O device cannot tolerate any wait states.

Semaphore 0. At this point, the software could choose to try and gain With the use of semaphores, once the two devices has determined

control of the second 8K section by writing, then reading a zero into which memory area was “off-limits” to the CPU, both the CPU and the

Semaphore 1. If it succeeded in gaining control, it would lock out the I/O devices could access their assigned portions of memory con-

left side.

Once the left side was finished with its task, it would write a one to

tinuously without any wait states.

Semaphores are also useful in applications where no memory

Semaphore 0 and may then try to gain access to Semaphore 1. If “WAIT” state is available on one or both sides. Once a semaphore

Semaphore 1 was still occupied by the right side, the left side could handshake has been performed, both processors can access their

undo its semaphore request and perform other tasks until it was able assigned RAM segments at full speed.

to write, then read a zero into Semaphore 1. If the right processor

Another application is in the area of complex data structures. In

performs a similar task with Semaphore 0, this protocol would allow this case, block arbitration is very important. For this application one

the two processors to swap 8K blocks of Dual-Port RAM with each processor may be responsible for building and updating a data

other.

structure. The other processor then reads and interprets that data

The blocks do not have to be any particular size and can even structure. If the interpreting processor reads an incomplete data

be variable, depending upon the complexity of the software using the structure, a major error condition may exist. Therefore, some sort

semaphore flags. All eight semaphores could be used to divide the of arbitration must be used between the two different processors. The

Dual-Port RAM or other shared resources into eight parts. Sema- building processor arbitrates for the block, locks it and then is able

phores can even be assigned different meanings on different sides to go in and update the data structure. When the update is com-

rather than being given a common meaning as was shown in the pleted, the data structure block is released. This allows the interpret-

example above.

ing processor to come back and read the complete data structure,

Semaphores are a useful form of arbitration in systems like disk

thereby guaranteeing a consistent data structure.

L PORT

R PORT

SEMAPHORE

REQUEST FLIP FLOP

SEMAPHORE

REQUEST FLIP FLOP

0

D

0

D

Q

WRITE

SEMAPHORE

READ

SEMAPHORE

,

READ

3190 drw 20

Figure 4. IDT7016 Semaphore Logic

6.1492

IDT7016S/L

High-Speed 16K x 9 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

Ordering Information

NOTES:

1. Contactyourlocalsalesofficeforindustrialtemprangeforotherspeeds,packagesandpowers.

2. Greenpartsavailable.Forspecificspeeds,packagesandpowerscontactyourlocalsalesoffice.

Datasheet Document History

01/11/99:

Initiated datasheet document history

Converted to new format

Cosmetic and typographical corrections

Added additional notes to pin configurations

Changed drawing format

Pages 2 and 3

Page 1

06/03/99

Corrected DSC number

11/10/99:

05/19/00:

Replaced IDT logo

Increased storage temperature parameter

Clarified TA parameter

Page 4

Page 6

DC Electrical parameters–changed wording from open to disabled

Changed ±200mV to 0mV in notes

01/10/02:

Pages 2 & 3

Pages 4, 6, 7, 9 & 12

Pages 6, 7, 9, 12 & 14

Page 20

Pages 1 & 20

Page 1

Added date revision for pin configurations

Removed Industrial temp footnote from all tables

Added Industrial temp for 20ns speed to DC and AC Electrical Characteristics

Added Industrial temp offering to 20ns ordering information

Replaced TM logo with ® logo

Added green availability to features

Added indicator to ordering information

Removed "IDT" from orderable part number

04/04/06:

01/09/09:

Page 20

20

6.42

IDT7016S/L

High-Speed 16K x 9 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

Datasheet Document History (con't)

10/03/14: Page 20

Page 2, 3, 4 & 20

Added Tape and Reel to Ordering Information

The package codes PN80-1, G68-1 & J68-1 changed to PN80, G68 & J68 respectively

to match standard package codes

10/10/14: Page 20

Corrected two typos

CORPORATE HEADQUARTERS

6024 Silver Creek Valley Road

San Jose, CA 95138

for SALES:

for Tech Support:

800-345-7015 or 408-284-8200 408-284-2794

fax: 408-284-2775

www.idt.com

DualPortHelp@idt.com

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

6.2412


型号：	7016S35PFGB
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	HIGH-SPEED 16K X 9 DUAL-PORT STATIC RAM
文件：	总21页 (文件大小：351K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

7016S35PFGB [IDT]

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