7025S55FGI8_技术文档

HIGH-SPEED

IDT7025S/L

8K x 16 DUAL-PORT

STATIC RAM

LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018

◆

IDT7025 easily expands data bus width to 32 bits or more

using the Master/Slave select when cascading more than

one device

M/S = H for BUSY output flag on Master

M/S = L for BUSY input on Slave

Interrupt Flag

On-chip port arbitration logic

Full on-chip hardware support of semaphore signaling

between ports

Fully asynchronous operation from either port

Battery backup operation—2V data retention

TTL-compatible, single 5V (±10%) power supply

Available in 84-pin PGA, Flatpack, PLCC, and 100-pin Thin

Quad Flatpack

Features

◆

True Dual-Ported memory cells which allow simultaneous

reads of the same memory location

High-speed access

◆

– Military:20/25/35/55/70ns(max.)

– Industrial: 55ns (max.)

◆

– Commercial:15/17/20/25/35/55ns(max.)

Low-power operation

◆

– IDT7025S

◆

Active:750mW(typ.)

Standby: 5mW (typ.)

– IDT7025L

Active:750mW(typ.)

Standby: 1mW (typ.)

Separate upper-byte and lower-byte control for multiplexed

◆

Industrial temperature range (–40°C to +85°C) is available

for selected speeds

Green parts available, see ordering information

bus compatibility

FunctionalBlockDiagram

R/W

R

R/W

L

UB

LB

R

LB

L

CEL

L

CER

OE

R

I/O8L-I/O15L

I/O0L-I/O7L

I/O8R-I/O15R

I/O

Control

I/O

Control

I/O0R-I/O7R

(1,2)

R

BUSY

L

A

12R

0R

A

12L

Address

Decoder

MEMORY

ARRAY

Address

Decoder

A

0L

A

13

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

CE

OE

R/W

L

CE

OE

R/W

R

L

R

L

R

SEM

L

SEM

R

(2)

INT ⁽²⁾

L

INTR

M/S

2683 drw 01

NOTES:

1. (MASTER): BUSY is output; (SLAVE): BUSY is input.

2. BUSY outputs and INT outputs are non-tri-stated push-pull.

MARCH 2018

1

DSC 2683/12

IDT7025S/L

High-Speed 8K x 16 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

featurecontrolledbyChipEnable(CE)permitstheon-chipcircuitryofeach

port to enter a very low standby power mode.

FabricatedusingIDT’sCMOShigh-performancetechnology,these

devices typically operate on only 750mW of power. Low-power (L)

versionsofferbatterybackupdataretentioncapabilitywithtypical power

consumptionof500µWfroma2Vbattery.

The IDT7025 is packaged in a ceramic 84-pin PGA, an 84-pin

Flatpack, PLCC, and a 100-pin TQFP. Military grade product is manu-

facturedincompliancewiththelatestrevisionofMIL-PRF-38535QML,

makingitideallysuitedtomilitarytemperatureapplicationsdemandingthe

highestlevelofperformanceandreliability.

Description

The IDT7025 is a high-speed 8K x 16 Dual-Port Static RAM. The

IDT7025isdesignedtobeusedasastand-alone128K-bitDual-PortRAM

orasacombinationMASTER/SLAVEDual-PortRAMfor32-bitormore

wordsystems.UsingtheIDTMASTER/SLAVEDual-PortRAMapproach

in32-bitorwidermemorysystemapplicationsresultsinfull-speed,error-

freeoperationwithouttheneedforadditionaldiscretelogic.

This device provides two independent ports with separate control,

address,andI/Opinsthatpermitindependent,asynchronousaccessfor

reads or writes to any location in memory. An automatic power down

PinConfigurations^(1,2,3)

INDEX

11/06/01

11 10

9

8

7

6

5

4

3

2

1 84 83 82 81 80 79 78 77 76 75

74

A

7L

6L

5L

4L

3L

2L

1L

0L

I/O8L

I/O9L

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

73

72

71

70

69

68

I/O10L

I/O11L

I/O12L

I/O13L

GND

IDT7025J or F

J84-1⁽⁴⁾

I/O14L

I/O15L

67

66

65

64

63

62

61

60

59

58

57

56

55

54

INT

L

F84-2⁽⁴⁾

BUSY

GND

M/S

L

V

CC

84-Pin PLCC/Flatpack

Top View⁽⁵⁾

GND

I/O0R

I/O1R

I/O2R

BUSY

R

INT

R

V

CC

A

0R

I/O3R

I/O4R

I/O5R

I/O6R

I/O7R

I/O8R

1R

2R

3R

4R

5R

6R

33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53

2683 drw 02

Index

11/06/01

100 9998 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76

1

N/C

75

2

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

3

4

N/C

5

I/O10L

I/O11L

I/O12L

I/O13L

GND

I/O14L

I/O15L

A5L

A4L

A3L

A2L

A1L

A0L

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

IDT7025PF

PN100-1⁽⁴⁾

INTL

VCC

BUSY

GND

M/S

BUSY

INTR

L

100-Pin TQFP

Top View⁽⁵⁾

GND

I/O0R

I/O1R

I/O2R

R

A

0R

VCC

NOTES:

1R

2R

3R

4R

I/O3R

I/O4R

I/O5R

I/O6R

N/C

1. All VCC pins must be connected to power supply.

2. All GND pins must be connected to ground supply.

3. J84-1 package body is approximately 1.15 in x 1.15 in x .17 in.

F84-2 package body is approximately 1.17 in x 1.17 in x .11 in.

PN100-1 package body is approximately 14mm x 14mm x 1.4mm.

4. This package code is used to reference the package diagram.

5. This text does not indicate orientation of the actual part-marking.

N/C

26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

.

2683 drw 03

6.422

IDT7025S/L

High-Speed 8K x 16 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

Pin Configurations^(1,2,3)(con't.)

11/06/01

63

I/O7L

66

I/O10L

67

I/O11L

69

I/O13L

72

I/O15L

75

I/O0R

76

I/O1R

79

I/O3R

81

I/O5R

82

I/O6R

61

I/O5L

64

I/O8L

65

I/O9L

68

I/O12L

71

I/O14L

70

60

I/O4L

62

I/O6L

58

I/O2L

59

I/O3L

55

I/O0L

56

I/O1L

57

54

51

48

46

45

42

11

10

09

08

07

06

05

04

03

02

01

A

11L

A

10L

A

7L

OE

L

SEM

L

LB

L

49

50

47

44

43

41

40

A

9L

A

8L

A

5L

UB

L

CE

L

A

12L

53

52

39

R/W

L

GND

VCC

A

6L

3L

0L

A

4L

38

37

A

2L

73

33

35

34

BUSY

L

A

V

CC

INT

L

IDT7025G

G84-3⁽⁴⁾

74

32

31

36

GND

M/S

GND

A

1L

84-Pin PGA

Top View⁽⁵⁾

77

I/O2R

80

I/O4R

83

I/O7R

78

28

29

30

V

CC

A

0R

INT

R

BUSYR

26

27

A

2R

A

1R

3R

7

11

12

23

25

SEM

R

GND

A5R

A

1

2

5

8

10

14

17

20

22

24

I/O9R

I/O10R I/O13R I/O15R

R/W

R

A

11R

A

8R

A

6R

9R

A

4R

7R

UB

R

84

I/O8R

3

4

6

9

15

13

16

18

19

21

I/O11R I/O12R I/O14R

A

10R

A

OE

R

LB

R

CER

A

12R

.

A

B

C

D

E

F

G

H

J

K

L

2683 drw 04

Index

NOTES:

1. All VCC pins must be connected to power supply.

2. All GND pins must be connected to ground supply.

3. Package body is approximately 1.12 in x 1.12 in x .16 in.

4. This package code is used to reference the package diagram.

5. This text does not indicate orientation of the actual part-marking.

6.342

IDT7025S/L

High-Speed 8K x 16 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

PinNames

Left Port

Right Port

Names

Chip Enable

CE

R/W

OE

L

CE

R/W

OE

R

L

R

Read/Write Enable

Output Enable

Address

L

R

A

0L - A12L

A

0R - A12R

I/O0L - I/O15L

I/O0R - I/O15R

Data Input/Output

Semaphore Enable

Upper Byte Select

Lower Byte Select

Interrupt Flag

SEM

UB

LB

INT

BUSY

L

SEM

UB

LB

INT

BUSY

M/S

R

L

R

L

R

L

R

Busy Flag

L

R

Master or Slave Select

Power

V

CC

GND

Ground

2683 tbl 01

6.442

IDT7025S/L

High-Speed 8K x 16 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

Truth Table I: Non-Contention Read/Write Control

Inputs⁽¹⁾

Outputs

R/W

X

I/O^8-15

High-Z

DATA^IN

High-Z

DATA^IN

I/O0-7

High-Z

DATA^IN

DATAIN

High-Z

DATA^OUT

DATAOUT

High-Z

Mode

CE

H

X

L

OE

X

L

UB

X

H

L

LB

X

H

L

SEM

H

Deselected

X

H

Both Bytes Deselected

L

H

Write to Upper Byte Only

Write to Lower Byte Only

Write to Both Bytes

L

H

L

H

L

H

L

H

X

L

H

L

H

DATA^OUT

High-Z

Read Upper Byte Only

Read Lower Byte Only

Read Both Bytes

L

H

L

H

L

H

DATA^OUT

High-Z

X

H

X

Outputs Disabled

2683 tbl 02

NOTE:

1. A0L — A12L ≠ A0R — A12R.

Truth Table II: Semaphore Read/Write Control⁽¹⁾

Inputs

Outputs

R/W

H

I/O^8-15

I/O0-7

Mode

CE

H

X

OE

L

UB

X

LB

X

SEM

L

DATAOUT

DATA^OUT

DATA^IN

DATAOUT

DATAIN

Read Semaphore Flag Data Out

H

L

H

X

H

X

H

X

↑

X

Write I/O

0

into Semaphore Flag

X

H

L

H

X

DATA^IN

DATAIN

Write I/O

↑

____

L

X

Not Allowed

____

L

X

L

2683 tbl 03

NOTES:

1. There are eight semaphore flags written to via I/O0 and read from I/O0 - I/O15. These eight semaphores are addressed by A0 - A2.

6.542

IDT7025S/L

High-Speed 8K x 16 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

AbsoluteMaximumRatings⁽¹⁾

MaximumOperatingTemperature

andSupplyVoltage⁽¹⁾

Symbol

Rating

Commercial

& Industrial

Military

Unit

Grade

GND

Vcc

(2)

Ambient Temperature

-55^OC to +125^OC

0^OC to +70^OC

V

TERM

Terminal Voltage

with Respect

to GND

-0.5 to +7.0

V

Military

0V

5.0V

+

10%

T

BIAS

Temperature

Under Bias

-55 to +125

-65 to +150

50

-65 to +135

-65 to +150

50

^oC

Commercial

Industrial

5.0V

10%

-40^OC to +85^OC

10%

TSTG

Storage

Temperature

2683 tbl 05

NOTES:

1. This is parameter TA. This is the "instant on" case temperature.

DC Output

Current

mA

IOUT

2683 tbl 04

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may

cause permanent damage to the device. This is a stress rating only and

functional operation of the device at these or any other conditions above those

indicated in the operational sections of this specification is not implied. Exposure

to absolute maximum rating conditions for extended periods may affect

reliability.

RecommendedDCOperating

Conditions

2. VTERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns

maximum, and is limited to < 20 mA for the period over VTERM > Vcc + 10%.

Symbol

Parameter

Min.

Typ.

Max. Unit

V

CC

Supply Voltage

4.5

5.0

5.5

0

V

GND

Ground

0

V

IH

IL

Input High Voltage

Input Low Voltage

2.2

6.0⁽²⁾

0.8

____

Capacitance⁽¹⁾(TA = +25°C, f = 1.0mhz)

-0.5⁽¹⁾

V

____

V

Symbol

Parameter

Input Capacitance

Output Capacitance

Conditions⁽²⁾

IN = 3dV

OUT = 3dV

Max. Unit

2683 tbl 06

NOTES:

CIN

V

9

pF

1. VIL > -1.5V for pulse width less than 10ns.

2. VTERM must not exceed Vcc + 10%.

COUT

V

10

pF

2683 tbl 07

NOTES:

1. This parameter is determined by device characterization but is not production

tested. For TQFP package only.

2. 3dV references the interpolated capacitance when the input and output signals

switch from 0V to 3V or from 3V to 0V.

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range (VCC = 5.0V ± 10%)

7025S

7025L

Symbol

Parameter

Input Leakage Current⁽¹⁾

Output Leakage Current

Output Low Voltage

Test Conditions

CC = 5.5V, VIN = 0V to VCC

OUT = 0V to VCC

Min.

Max.

10

Min.

Max.

Unit

µA

V

___

|ILI|

V

5

___

|I^LO

|

10

V

OL

OH

I

OL = +4mA

0.4

___

V

Output High Voltage

I

OH = -4mA

2.4

V

2683 tbl 08

NOTE:

1. At Vcc < 2.0V input leakages are undefined.

6.462

IDT7025S/L

High-Speed 8K x 16 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

DC Electrical Characteristics Over the 0perating

Temperature and Supply Voltage Range⁽¹⁾(VCC = 5.0V ± 10%)

7025X15

7025X17

7025X20

Com'l, Ind

& Military

7025X25

Com'l &

Military

Com'l Only

Symbol

Parameter

Test Condition

Version

COM'L

Typ.⁽²⁾

Max.

Typ.⁽²⁾

Max.

Typ.⁽²⁾

Max.

Typ.⁽²⁾

Max.

Unit

mA

ICC

Dynamic Operating

Current

(Both Ports Active)

S

L

170

310

260

170

310

260

160

290

240

155

265

220

CE = VIL, Outputs Disabled

SEM = VIH

(3)

f = fMAX

____

MIL &

IND

S

L

160

370

320

155

340

280

mA

I

SB1

Standby Current

(Both Ports - TTL

Level Inputs)

COM'L

S

L

20

60

50

20

60

50

20

60

50

16

60

50

CE

SEM

f = fMAX

L

= CE

R

= VIH

R

= SEM

L

(3)

____

MIL &

IND

S

L

20

90

70

16

80

65

(5)

ISB2

Standby Current

(One Port - TTL

Level Inputs)

COM'L

S

L

105

190

160

105

190

160

95

180

150

90

170

140

CE^"A"= VIL and CE"B" = VIH

Active Port Outputs Disabled,

(3)

f=fMAX

____

MIL &

IND

S

L

95

240

210

90

215

180

SEM

R

= SEML = VIH

mA

I

SB3

Full Standby Current

(Both Ports -

COM'L

S

L

1.0

0.2

15

5

1.0

0.2

15

5

1.0

0.2

15

5

1.0

0.2

15

5

CE

L

and CE

IN > VCC - 0.2V or

IN < 0.2V, f = 0⁽⁴⁾

= SEM > VCC - 0.2V

R > VCC - 0.2V,

V

CMOS Level Inputs)

____

MIL &

IND

S

L

1.0

0.2

30

10

1.0

0.2

30

10

SEM

R

L

ISB4

Full Standby Current

(One Port -

CMOS Level Inputs)

COM'L

S

L

100

170

140

100

170

140

90

155

130

85

145

120

CE^"A"< 0.2V and

CE^"B"> VCC - 0.2V⁽⁵⁾

SEM

R

= SEML > VCC - 0.2V

____

MIL &

IND

S

L

90

225

200

85

200

170

V

IN > VCC - 0.2V or VIN < 0.2V

Active Port Outputs Disabled,

(3)

f = fMAX

2683 tbl 09a

7025X35

Com'l &

Military

7025X55

Com'l, Ind

& Military

7025X70

Military Only

Symbol

Parameter

Test Condition

Version

Typ.⁽²⁾

Max.

Typ.⁽²⁾

Max.

Typ.⁽²⁾

Max.

Unit

____

ICC

Dynamic Operating

Current

(Both Ports Active)

COM'L

S

150

250

210

150

250

210

mA

CE = VIL, Outputs Disabled

SEM = VIH

L

(3)

f = fMAX

MIL &

IND

S

L

150

300

250

150

300

250

140

300

250

____

I

SB1

Standby Current

(Both Ports - TTL

Level Inputs)

COM'L

S

L

13

60

50

13

60

50

mA

CE

SEM

f = fMAX

L

= CE

R

= VIH

R

= SEM

L

(3)

MIL &

IND

S

L

13

80

65

13

80

65

10

80

65

(5)

____

ISB2

Standby Current

(One Port - TTL

Level Inputs)

COM'L

S

L

85

155

130

85

155

130

CE^"A"= VIL and CE"B" = VIH

Active Port Outputs Disabled,

(3)

f=fMAX

MIL &

IND

S

L

85

190

160

85

190

160

80

190

160

SEM

R

= SEML = VIH

____

I

SB3

Full Standby Current

(Both Ports -

COM'L

S

L

1.0

0.2

15

5

1.0

0.2

15

5

mA

CE

L

and CE

IN > VCC - 0.2V or

IN < 0.2V, f = 0⁽⁴⁾

= SEM > VCC - 0.2V

R > VCC - 0.2V,

V

CMOS Level Inputs)

MIL &

IND

S

L

1.0

0.2

30

10

1.0

0.2

30

10

1.0

0.2

30

10

SEM

R

L

____

ISB4

Full Standby Current

(One Port -

CMOS Level Inputs)

COM'L

S

L

80

135

110

80

135

110

CE^"A"< 0.2V and

CE^"B"> V - 0.2V⁽⁵⁾

SEM

R

= S^CE^CM

L > VCC - 0.2V

MIL &

IND

S

L

80

175

150

80

175

150

75

175

150

V

IN > VCC - 0.2V or VIN < 0.2V

Active Port Outputs Disabled,

(3)

f = fMAX

2683 tbl 09b

NOTES:

1. 'X' in part number indicates power rating (S or L)

2. VCC = 5V, TA = +25°C, and are not production tested. Icc dc = 120mA (TYP)

3. At f = fMAX, address and I/O'S are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions” of input levels of GND to 3V.

4. f = 0 means no address or control lines change.

5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".

6.742

IDT7025S/L

High-Speed 8K x 16 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

Data Retention Characteristics Over All Temperature Ranges

(L Version Only)

Symbol

Parameter

Test Condition

Min.

Typ.⁽¹⁾

Max.

Unit

V

___

V

DR

V

CC for Data Retention

V

CC = 2V

2.0

___

ICCDR

Data Retention Current

µA

CE > VHC

IN > VHC or < VLC

MIL. & IND.

COM'L.

100

4000

___

V

100

1500

(3)

___

t

CDR

Chip Deselect to Data Retention Time

Operation Recovery Time

0

ns

SEM > VHC

(3)

(2)

___

tR

t

RC

ns

2683 tbl 10

NOTES:

1. TA = +25°C, VCC = 2V, and are not production tested.

2. tRC = Read Cycle Time

3. This parameter is guaranteed by device characterization, but is not production tested.

4. At Vcc < 2.0V input leakages are undefined.

Data Retention Waveform

DATA RETENTION MODE

VDR

≥

4.5V

VCC

2V

tCDR

tR

VDR

VIH

CE

2683 drw 05

AC Test Conditions

Input Pulse Levels

GND to 3.0V

5ns Max.

1.5V

Input Rise/Fall Times

Input Timing Reference Levels

Output Reference Levels

Output Load

1.5V

Figures 1 and 2

2683 tbl 11

5V

893Ω

DATAOUT

BUSY

INT

DATAOUT

30pF

347Ω

5pF*

347Ω

2683 drw 06

Figure 2. Output Test Load

(for t^LZ, tHZ, tWZ, tOW)

* including scope and jig.

Figure 1. AC Output Test Load

6.482

IDT7025S/L

High-Speed 8K x 16 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

AC Electrical Characteristics Over the

OperatingTemperatureandSupplyVoltageRange⁽⁴⁾

7025X15

7025X17

7025X20

Com'l, Ind

& Military

7025X25

Com'l &

Military

Com'l Only

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Unit

READ CYCLE

____

t

RC

AA

ACE

ABE

AOE

OH

LZ

HZ

PU

PD

SOP

SAA

Read Cycle Time

15

17

20

25

ns

____

t

Address Access Time

15

17

20

25

____

Chip Enable Access Time⁽³⁾

Byte Enable Access Time⁽³⁾

t

ns

Output Enable Access Time⁽³⁾

t

10

12

13

____

t

Output Hold from Address Change

3

____

Output Low-Z Time^(1,2)

t

3

____

Output High-Z Time^(1,2)

t

10

12

15

____

Chip Enable to Power Up Time^(1,2)

t

0

____

Chip Disable to Power Down Time^(1,2)

t

15

17

20

25

____

t

Semaphore Flag Update Pulse (OE or SEM)

10

____

Semaphore Address Access⁽³⁾

t

15

17

20

25

ns

2683 tbl 12a

7025X35

Com'l &

Military

7025X55

Com'l, Ind

& Military

7025X70

Military Only

Symbol

READ CYCLE

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

____

t

RC

AA

ACE

ABE

AOE

OH

LZ

HZ

PU

PD

SOP

SAA

Read Cycle Time

35

55

70

ns

____

t

Address Access Time

35

55

70

Chip Enable Access Time⁽³⁾

Byte Enable Access Time⁽³⁾

Output Enable Access Time⁽³⁾

Output Hold from Address Change

Output Low-Z Time^(1,2)

____

t

20

30

35

____

t

3

____

t

3

Output High-Z Time^(1,2)

15

25

30

____

t

Chip Enable to Power Up Time^(1,2)

Chip Disable to Power Down Time^(1,2)

Semaphore Flag Update Pulse (OE or SEM)

Semaphore Address Access⁽³⁾

0

____

t

35

50

____

t

15

____

t

35

55

70

ns

2683 tbl 12b

NOTES:

1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).

2. This parameter is guaranteed by device characterazation, but is not production tested.

3. To access RAM, CE = VIL, UB or LB = VIL, and SEM = VIH. To access semephore, CE = VIH or UB & LB = VIH, and SEM = VIL.

4. 'X' in part number indicates power rating (S or L).

6.942

IDT7025S/L

High-Speed 8K x 16 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

Waveform of Read Cycles⁽⁵⁾

tRC

ADDR

(4)

t

AA

(4)

ACE

CE

OE

(4)

tAOE

(4)

t

ABE

UB, LB

R/W

(1)

tOH

tLZ

VALID DATA⁽⁴⁾

DATAOUT

BUSYOUT

(2)

tHZ

(3,4)

2683 drw 07

t

BDD

NOTES:

1. Timing depends on which signal is asserted last, OE, CE, LB, or UB.

2. Timing depends on which signal is de-asserted first, CE, OE, LB, or UB.

3. tBDD delay is required only in case where opposite port is completing a write operation to the same address location for simultaneous read operations BUSY

has no relation to valid output data.

4. Start of valid data depends on which timing becomes effective last tABE, tAOE, tACE, tAA or tBDD.

5. SEM = VIH.

Timing of Power-Up Power-Down

CE

tPU

tPD

I

CC

SB

50%

I

.

2683 drw 08

6.1402

IDT7025S/L

High-Speed 8K x 16 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

AC Electrical Characteristics Over the

OperatingTemperatureandSupplyVoltage⁽⁵⁾

7025X15

7025X17

Com'l Only

7025X20

Com'l, Ind

& Military

7025X25

Com'l &

Military

Com'l Only

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Unit

WRITE CYCLE

____

t

WC

EW

AW

AS

WP

WR

DW

HZ

DH

WZ

OW

SWRD

SPS

Write Cycle Time

15

12

0

17

12

0

20

15

0

25

20

0

ns

t

Chip Enable to End-of-Write⁽³⁾

Address Valid to End-of-Write

Address Set-up Time⁽³⁾

Write Pulse Width

t

12

0

12

0

15

0

20

0

t

Write Recovery Time

t

Data Valid to End-of-Write

Output High-Z Time^(1,2)

Data Hold Time⁽⁴⁾

10

15

____

t

10

12

15

____

t

0

(1,2)

____

t

Write Enable to Output in High-Z

Output Active from End-of-Write^{(1, 2,4)}

SEM Flag Write to Read Time

SEM Flag Contention Window

10

12

15

____

t

0

5

0

5

0

5

0

5

____

t

ns

2683 tbl 13a

7025X35

Com'l &

Military

7025X55

Com'l, Ind

& Military

7025X70

Military Only

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

WRITE CYCLE

____

tWC

tEW

tAW

tAS

Write Cycle Time

35

30

0

55

45

0

70

50

0

ns

Chip Enable to End-of-Write⁽³⁾

Address Valid to End-of-Write

Address Set-up Time⁽³⁾

Write Pulse Width

tWP

tWR

tDW

tHZ

25

0

40

0

50

0

Write Recovery Time

Data Valid to End-of-Write

Output High-Z Time^(1,2)

Data Hold Time⁽⁴⁾

15

30

40

____

15

25

30

____

tDH

0

(1,2)

____

tWZ

Write Enable to Output in High-Z

15

25

30

tOW

tSWRD

tSPS

Output Active from End-of-Write^(1,2,4)

SEM Flag Write to Read Time

SEM Flag Contention Window

0

5

0

5

0

5

____

ns

2683 tbl 13b

NOTES:

1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).

2. This parameter is guaranteed by device characterization, but is not production tested.

3. To access RAM, CE = VIL, UB or LB = VIL, SEM = VIH. To access semaphore, CE = VIH or UB & LB = VIH, and SEM = VIL. Either condition must be valid for the

entire tEW time.

4. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage

and temperature, the actual tDH will always be smaller than the actual tOW.

5. 'X' in part number indicates power rating (S or L).

61.412

IDT7025S/L

High-Speed 8K x 16 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

Timing Waveform of Write Cycle No. 1, R/W Controlled Timing^(1,5,8)

t

WC

ADDRESS

(7)

tHZ

OE

tAW

CE or SEM⁽⁹⁾

UB or LB⁽⁹⁾

(3)

(2)

(6)

tWP

tWR

tAS

R/W

DATAOUT

DATAIN

(7)

t

WZ

tOW

(4)

tDW

tDH

2683 drw 09

Timing Waveform of Write Cycle No. 2, CE, UB, LB Controlled Timing^(1,5)

tWC

ADDRESS

tAW

CE or SEM⁽⁹⁾

(3)

(2)

(6)

AS

tWR

t

EW

t

UB or LB⁽⁹⁾

R/W

DATAIN

tDW

tDH

2683 drw 10

NOTES:

1. R/W or CE or UB & LB = VIH during all address transitions.

2. A write occurs during the overlap (tEW or tWP) of a UB or LB = VIL and a CE = VIL and a R/W = VIL for memory array writing cycle.

3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going to VIH to the end-of-write cycle.

4. During this period, the I/O pins are in the output state and input signals must not be applied.

5. If the CE or SEM LOW = VIL transition occurs simultaneously with or after the R/W = VIL transition, the outputs remain in the HIGH impedance state.

6. Timing depends on which enable signal is asserted last, CE, R/W, or byte control.

7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with Output Test Load

(Figure 2).

8. If OE = VIL during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be

placed on the bus for the required tDW. If OE = VIH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the

specified tWP.

9. To access RAM, CE = VIL, UB or LB = VIL, and SEM = VIH. To access Semaphore, CE = VIH or UB & LB = VIH, and SEM = VIL. tEW must be met

for either condition.

6.1422

IDT7025S/L

High-Speed 8K x 16 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

Timing Waveform of Semaphore Read after Write Timing, Either Side⁽¹⁾

tSAA

tOH

A0 - A2

VALID ADDRESS

tAW

tWR

tACE

t

EW

SEM

t

SOP

t

DW

OUT

(2)

DATA

DATAIN VALID

DATA

0

VALID

tAS

WP

tDH

R/W

t

AOE

t

SWRD

OE

tSOP

Write Cycle

Read Cycle

2683 drw 11

NOTE:

1. CE = VIH or UB & LB = VIH for the duration of the above timing (both write and read cycle).

2. "DATAOUT VALID" represents all I/O's (I/O0-I/O15) equal to the semaphore value.

Timing Waveform of Semaphore Write Contention^(1,3,4)

A0"A"-A2"A"

MATCH

SIDE⁽²⁾

"A"

R/W"A"

SEM"A"

t

SPS

A0"B"-A2"B"

MATCH

SIDE⁽²⁾

"B"

R/W"B"

SEM"B"

2683 drw 12

NOTES:

1. DOR = DOL = VIL, CER = CEL = VIH, or both UB & LB = VIH.

2. All timing is the same for left and right port. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.

3. This parameter is measured from R/W"A" or SEM"A" going HIGH to R/W"B" or SEM"B" going HIGH.

4. If tSPS is not satisfied, there is no guarantee which side will obtain the semaphore flag.

61.432

IDT7025S/L

High-Speed 8K x 16 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

AC Electrical Characteristics Over the

OperatingTemperatureSupplyVoltageRange⁽⁶⁾

7025X15

7025X17

7025X20

Com'l, Ind

& Military

7025X25

Com'l &

Military

Com'l Ony

Com'l Only

Symbol

BUSY TIMING (M/S = V^IH

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Unit

)

____

t

BAA

BDA

BAC

BDC

APS

BDD

WH

15

17

20

ns

BUSY Access Time from Address Match

BUSY Disable Time from Address Not Matched

BUSY Access Time from Chip Enable LOW

BUSY Disable Time from Chip Enable HIGH

Arbitration Priority Set-up Time⁽²⁾

t

15

17

____

t

5

____

BUSY Disable to Valid Data⁽³⁾

t

18

30

(5)

____

t

Write Hold After BUSY

12

13

15

17

BUSY TIMING (M/S = V^IL

)

____

BUSY Input to Write⁽⁴⁾

t

WB

0

ns

(5)

tWH

Write Hold After BUSY

12

13

15

17

PORT-TO-PORT DELAY TIMING

____

t

WDD

Write Pulse to Data Delay⁽¹⁾

30

25

30

25

45

35

50

35

ns

tDDD

Write Data Valid to Read Data Delay⁽¹⁾

ns

2683 tbl 14a

7025X35

Com'l &

Military

7025X55

Com'l, Ind

& Military

7025X70

Military Only

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

BUSY TIMING (M/S = V^IH

)

____

t

BAA

BDA

BAC

BDC

APS

BDD

WH

20

45

40

45

40

ns

BUSY Access Time from Address Match

BUSY Disable Time from Address Not Matched

BUSY Access Time from Chip Enable LOW

BUSY Disable Time from Chip Enable HIGH

Arbitration Priority Set-up Time⁽²⁾

t

20

35

____

t

5

____

BUSY Disable to Valid Data⁽³⁾

t

35

40

45

(5)

____

t

Write Hold After BUSY

25

BUSY TIMING (M/S = VIL

)

____

BUSY Input to Write⁽⁴⁾

t

WB

0

ns

(5)

tWH

Write Hold After BUSY

25

PORT-TO-PORT DELAY TIMING

____

t

WDD

Write Pulse to Data Delay⁽¹⁾

60

45

80

65

95

80

ns

tDDD

Write Data Valid to Read Data Delay⁽¹⁾

ns

2683 tbl 14b

NOTES:

1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write Port-to-Port Read and BUSY (M/S = VIH)".

2. To ensure that the earlier of the two ports wins.

3. tBDD is a calculated parameter and is the greater of 0ns, tWDD – tWP (actual) or tDDD – tDW (actual).

4. To ensure that the write cycle is inhibited on Port "B" during contention with Port "A".

5. To ensure that a write cycle is completed on Port "B" after contention with Port "A".

6. 'X' in part number indicates power rating (S or L).

6.1442

IDT7025S/L

High-Speed 8K x 16 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

Timing Waveform of Write Port-to-Port Read and BUSY^(2,4,5)(M/S = VIH)

tWC

MATCH

ADDR"A"

t

WP

R/W"A"

tDW

tDH

VALID

DATAIN "A"

(1)

tAPS

MATCH

ADDR"B"

tBAA

tBDA

tBDD

BUSY"B"

tWDD

VALID

DATAOUT "B"

(3)

tDDD

2683 drw 13

NOTES:

1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (slave).

2. CE^L= CER = VIL.

3. OE = VIL for the reading port.

4. If M/S = VIL (SLAVE), then BUSY is an input. Therefore in this example BUSY"A" = VIH and BUSY"B" input is shown.

5. All timing is the same for left and right ports. Port "A" may be either the left of right port. Port "B" is the opposite port from Port "A".

Timing Waveform of Write with BUSY

tWP

R/W"A"

(3)

tWB

BUSY"B"

(1)

tWH

R/W^"B"

(2)

2683 drw 14

NOTES:

1. tWH must be met for both BUSY input (slave) output master.

2. BUSY is asserted on port "B" Blocking R/W^"B", until BUSY"B" goes HIGH.

3. tWB is only for the 'Slave' Version.

61.452

IDT7025S/L

High-Speed 8K x 16 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

Waveform of BUSY Arbitration Controlled by CE Timing⁽¹⁾(M/S = VIH)

ADDR"A"

ADDRESSES MATCH

and "B"

CE"A"

(2)

tAPS

CE"B"

tBAC

tBDC

BUSY"B"

2683 drw 15

Waveform of BUSY Arbitration Cycle Controlled by Address Match

Timing⁽¹⁾(M/S = VIH)

ADDR"A"

ADDR"B"

BUSY"B"

ADDRESS "N"

(2)

tAPS

MATCHING ADDRESS "N"

tBAA

tBDA

2683 drw 16

NOTES:

1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.

2. If tAPS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.

AC Electrical Characteristics Over the

OperatingTemperatureandSupplyVoltageRange⁽¹⁾

7025X15

7025X17

7025X20

Com'l, Ind

& Military

7025X25

Com'l &

Military

Com'l Only

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Unit

INTERRUPT TIMING

____

t

AS

WR

INS

INR

Address Set-up Time

Write Recovery Time

Interrupt Set Time

0

ns

t

0

____

t

15

20

____

t

Interrupt Reset Time

ns

2683 tbl 15a

7025X35

Com'l &

Military

7025X55

Com'l, Ind

& Military

7025X70

Military Only

Symbol

INTERRUPT TIMING

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

____

t

AS

WR

INS

INR

Address Set-up Time

Write Recovery Time

Interrupt Set Time

0

ns

t

0

____

t

25

40

50

____

t

Interrupt Reset Time

ns

2683 tbl 15b

NOTES:

1. 'X' in part number indicates power rating (S or L).

6.1462

IDT7025S/L

High-Speed 8K x 16 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

Waveform of Interrupt Timing⁽¹⁾

tWC

INTERRUPT SET ADDRESS⁽²⁾

ADDR"A"

(4)

(3)

tAS

tWR

CE"A"

R/W"A"

INT"B"

(3)

tINS

2683 drw 17

tRC

INTERRUPT CLEAR ADDRESS ⁽²⁾

ADDR"B"

CE"B"

(3)

tAS

OE"B"

(3)

INR

t

INT"B"

2683 drw 18

NOTES:

1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.

2. See Interrupt Flag Truth Table.

3. Timing depends on which enable signal (CE or R/W) is asserted last.

4. Timing depends on which enable signal (CE or R/W) is de-asserted first.

TruthTables

Truth Table I — Interrupt Flag⁽¹⁾

Left Port

Right Port

R/W

L

A

0L-A12L

R/W

R

A

0R-A12R

Function

Set Right INT Flag

Reset Right INT Flag

Set Left INT Flag

Reset Left INT Flag

CE

L

OE

L

INT

L

CE

R

OE

R

INTR

L

X

L

X

L

X

1FFF

X

L

X

L⁽²⁾

H⁽³⁾

X

R

X

L

1FFF

1FFE

X

R

X

L⁽³⁾

H⁽²⁾

L

X

L

1FFE

X

L

2689 tbl 16

NOTES:

1. Assumes BUSY^L= BUSYR = VIH.

2. If BUSY^L= VIL, then no change.

3. If BUSY^R= VIL, then no change.

4. INT^Rand INTL must be initialized at power-up.

61.472

IDT7025S/L

High-Speed 8K x 16 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

Truth Table II — Address BUSY

Arbitration

Inputs

Outputs

A

0L-A12L

(1)

A

0R-A12R

Function

Normal

CE

L

CE

R

BUSY

L

BUSYR

X

H

X

L

X

H

L

NO MATCH

MATCH

H

MATCH

H

MATCH

(2)

Write Inhibit⁽³⁾

2683 tbl 17

NOTES:

1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. BUSY are inputs when configured as a slave. BUSYx outputs on the IDT7025

are push pull, not open drain outputs. On slaves the BUSY asserted internally inhibits write.

2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address

and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs cannot be LOW simultaneously.

3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored

when BUSY^Routputs are driving LOW regardless of actual logic level on the pin.

Truth Table III — Example of Semaphore Procurement Sequence^(1,2,3)

Functions

D0

- D15 Left

D0

- D15 Right

Status

No Action

1

0

1

0

1

0

1

0

1

0

1

Semaphore free

Left Port Writes "0" to Semaphore

Right Port Writes "0" to Semaphore

Left Port Writes "1" to Semaphore

Left Port Writes "0" to Semaphore

Right Port Writes "1" to Semaphore

Left Port Writes "1" to Semaphore

Right Port Writes "0" to Semaphore

Right Port Writes "1" to Semaphore

Left Port Writes "0" to Semaphore

Left Port Writes "1" to Semaphore

Left port has semaphore token

No change. Right side has no write access to semaphore

Right port obtains semaphore token

No change. Left port has no write access to semaphore

Left port obtains semaphore token

Semaphore free

Right port has semaphore token

Semaphore free

Left port has semaphore token

Semaphore free

2683 tbl 18

NOTES:

1. This table denotes a sequence of events for only one of the eight semaphores on the IDT7025.

2. There are eight semaphore flags written to via I/O0 and read from all I/0's. These eight semaphores are addressed by A0 - A2.

3. CE = VIH, SEM = VIL, to access the semaphores. Refer to the Semaphore Read/Write Truth Table.

FunctionalDescription

(HEX),whereawriteisdefinedastheCE^R=R/WR=VIL perTruthTable

I. The left port clears the interrupt by an address location 1FFE access

when CE^L= OEL = VIL, R/WL is a "don't care". Likewise, the right port

interruptflag(INTR)isassertedwhentheleftportwritestomemorylocation

1FFF(HEX)andtocleartheinterruptflag(INTR),therightportmustaccess

the memory location 1FFF, The message (16 bits) at 1FFE or 1FFF is

user-defined, since it is an addressable SRAM location. If the interrupt

functionisnotused, addresslocations1FFEand1FFFarenotusedas

mailboxes,butaspartoftherandomaccessmemory.RefertoTruthTable

Ifortheinterruptoperation.

TheIDT7025providestwoportswithseparatecontrol,addressand

I/Opinsthatpermitindependentaccessforreadsorwritestoanylocation

inmemory.TheIDT7025hasanautomaticpowerdownfeaturecontrolled

by CE. The CE controls on-chip power down circuitry that permits the

respectiveporttogointoastandbymodewhennotselected(CE=VIH).

Whenaportisenabled,accesstotheentirememoryarrayispermitted.

Interrupts

Iftheuserchoosestheinterruptfunction,amemorylocation(mailbox

ormessagecenter)isassignedtoeachport. Theleftportinterruptflag

(INTL) is asserted when the right port writes to memory location 1FFE

6.1482

IDT7025S/L

High-Speed 8K x 16 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

BusyLogic

BusyLogicprovidesahardwareindicationthatbothportsoftheRAM

haveaccessedthesamelocationatthesametime.Italsoallowsoneofthe

twoaccessestoproceedandsignalstheothersidethattheRAMis“busy”.

TheBUSYpincanthenbeusedtostalltheaccessuntiltheoperationon

theothersideiscompleted.Ifawriteoperationhasbeenattemptedfrom

thesidethatreceivesaBUSYindication,thewritesignalisgatedinternally

topreventthewritefromproceeding.

CE

MASTER

Dual Port

RAM

SLAVE

Dual Port

RAM

BUSY

L

BUSY

L

BUSYR

BUSY

R

MASTER

Dual Port

RAM

CE

SLAVE

Dual Port

RAM

CE

BUSY

R

BUSY

L

BUSY

L

BUSY

R

BUSYR

BUSY

L

TheuseofBUSYlogicisnotrequiredordesirableforallapplications.

InsomecasesitmaybeusefultologicallyORtheBUSYoutputstogether

and use any BUSYindication as an interrupt source to flag the event of

anillegalorillogicaloperation.IfthewriteinhibitfunctionofBUSYlogicis

notdesirable,theBUSYlogiccanbedisabledbyplacingthepartinslave

modewiththeM/Spin.OnceinslavemodetheBUSYpinoperatessolely

asawriteinhibitinputpin.Normaloperationcanbeprogrammedbytying

the BUSY pins HIGH. If desired, unintended write operations can be

prevented to a port by tying the BUSY pin for that port LOW.

TheBUSYoutputsontheIDT7025RAMinmastermode,arepush-

pulltypeoutputsanddonotrequirepullupresistorstooperate. Ifthese

RAMs are being expanded in depth, then the BUSY indication for the

resulting array requires the use of an external AND gate.

2683 drw 19

Figure 3. Busy and chip enable routing for both width and depth

expansion with IDT7025 RAMs.

leftportinnowayslowstheaccesstimeoftherightport. Bothportsare

identicalinfunctiontostandardCMOSStaticRAMandcanbereadfrom,

orwrittento,atthesametimewiththeonlypossibleconflictarisingfromthe

simultaneous writing of, or a simultaneous READ/WRITE of, a non-

semaphorelocation.Semaphoresareprotectedagainstsuchambiguous

situationsandmaybeusedbythesystemprogramtoavoidanyconflicts

inthenon-semaphoreportionoftheDual-PortRAM.Thesedeviceshave

anautomaticpower-downfeaturecontrolledbyCE,theDual-PortRAM

enable,andSEM,thesemaphoreenable.TheCEandSEMpinscontrol

on-chip power down circuitry that permits the respective port to go into

standbymodewhennotselected.Thisistheconditionwhichisshownin

Truth Table I where CE and SEM are both = VIH.

SystemswhichcanbestusetheIDT7025containmultipleprocessors

or controllers and are typically very high-speed systems which are

softwarecontrolledorsoftwareintensive.Thesesystemscanbenefitfrom

a performance increase offered by the IDT7025's hardware sema-

phores,whichprovidealockoutmechanismwithoutrequiringcomplex

programming.

Softwarehandshakingbetweenprocessorsoffersthemaximumin

systemflexibilitybypermittingsharedresourcestobeallocatedinvarying

configurations.TheIDT7025doesnotuseitssemaphoreflagstocontrol

anyresourcesthroughhardware,thusallowingthesystemdesignertotal

flexibilityinsystemarchitecture.

An advantage of using semaphores rather than the more common

methodsofhardwarearbitrationisthatwaitstatesareneverincurredin

either processor. This can prove to be a major advantage in very high-

speedsystems.

Width Expansion with Busy Logic

Master/SlaveArrays

WhenexpandinganIDT7025RAMarrayinwidthwhileusingBUSY

logic,onemasterpartisusedtodecidewhichsideoftheRAMarraywill

receiveaBUSYindication,andtooutputthatindication.Anynumberof

slaves to be addressed in the same address range as the master, use

theBUSYsignalasawriteinhibitsignal.ThusontheIDT7025RAMthe

BUSYpinisanoutputifthepartisusedasamaster(M/Spin=VIH),and

theBUSYpinisaninputifthepartusedasaslave(M/Spin=VIL)asshown

in Figure 3.

Iftwoormoremasterpartswereusedwhenexpandinginwidth,asplit

decisioncouldresultwithonemasterindicatingBUSYononesideofthe

arrayandanothermasterindicatingBUSYononeothersideofthearray.

Thiswouldinhibitthewriteoperationsfromoneportforpartofawordand

inhibitthewriteoperationsfromtheotherportfortheotherpartoftheword.

TheBUSYarbitration,onamaster,isbasedonthechipenableand

address signals only. It ignores whether an access is a read or write. In

a master/slave array, both address and chip enable must be valid long

enoughforaBUSYflagtobeoutputfromthemasterbeforetheactualwrite

pulsecanbeinitiatedwitheithertheR/Wsignalorthebyteenables.Failure

toobservethistimingcanresultinaglitchedinternalwriteinhibitsignaland

corrupteddataintheslave.

How the Semaphore Flags Work

Thesemaphorelogicisasetofeightlatcheswhichareindependent

oftheDual-PortRAM.Theselatchescanbeusedtopassaflag,ortoken,

fromoneporttotheothertoindicatethatasharedresourceisinuse.The

semaphores provide a hardware assist for a use assignment method

called“TokenPassingAllocation.”Inthismethod,thestateofasemaphore

latchisusedasatokenindicatingthatsharedresourceisinuse.Iftheleft

processorwantstousethisresource,itrequeststhetokenbysettingthe

latch.Thisprocessorthenverifiesitssuccessinsettingthelatchbyreading

it. If it was successful, it proceeds to assume control over the shared

resource.Ifitwasnotsuccessfulinsettingthelatch,itdeterminesthatthe

rightsideprocessorhassetthelatchfirst, hasthetokenandisusingthe

sharedresource.Theleftprocessorcantheneitherrepeatedlyrequest

Semaphores

TheIDT7025isanextremelyfastDual-Port8Kx16CMOSStaticRAM

withanadditional8addresslocationsdedicatedtobinarysemaphoreflags.

TheseflagsalloweitherprocessorontheleftorrightsideoftheDual-Port

RAMtoclaimaprivilegeovertheotherprocessorforfunctionsdefinedby

thesystemdesigner’ssoftware.Asanexample,thesemaphorecanbe

usedbyoneprocessortoinhibittheotherfromaccessingaportionofthe

Dual-Port RAM or any other shared resource.

The Dual-Port RAM features a fast access time, and both ports are

completelyindependentofeachother.Thismeansthattheactivityonthe

61.492

IDT7025S/L

High-Speed 8K x 16 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

that semaphore’s status or remove its request for that semaphore to into a semaphore flag. Whichever latch is first to present a zero to the

performanothertaskandoccasionallyattemptagaintogaincontrolofthe semaphoreflagwillforceitssideofthesemaphoreflagLOWandtheother

tokenviathesetandtestsequence.Oncetherightsidehasrelinquished sideHIGH.Thisconditionwillcontinueuntilaoneiswrittentothesame

thetoken,theleftsideshouldsucceedingainingcontrol.

semaphorerequestlatch.Shouldtheotherside’ssemaphorerequestlatch

ThesemaphoreflagsareactiveLOW.Atokenisrequestedbywriting havebeenwrittentoazerointhemeantime,thesemaphoreflagwillflip

azerointoasemaphorelatchandisreleasedwhenthesamesidewrites overtotheothersideassoonasaoneiswrittenintothefirstside’srequest

aonetothatlatch.

latch.Thesecondside’sflagwillnowstayLOWuntilitssemaphorerequest

The eight semaphore flags reside within the IDT7025 in a separate latchiswrittentoaone.Fromthisitiseasytounderstandthat,ifasemaphore

memoryspacefromtheDual-PortRAM.Thisaddressspaceisaccessed is requested and the processor which requested it no longer needs the

by placing a LOW input on the SEM pin (which acts as a chip select for resource, the entire system can hang up until a one is written into that

thesemaphoreflags)andusingtheothercontrolpins(Address,OE,and semaphorerequestlatch.

R/W)astheywouldbeusedinaccessingastandardStaticRAM. Each

The critical case of semaphore timing is when both sides request a

oftheflagshasauniqueaddresswhichcanbeaccessedbyeitherside single token by attempting to write a zero into it at the same time. The

throughaddresspinsA0–A2.Whenaccessingthesemaphores,noneof semaphore logic is specially designed to resolve this problem. If

theotheraddresspinshasanyeffect.

simultaneousrequestsaremade,thelogicguaranteesthatonlyoneside

Whenwritingtoasemaphore,onlydatapinD0isused.IfaLOWlevel receives the token. If one side is earlier than the other in making the

iswrittenintoanunusedsemaphorelocation,thatflagwillbesettoazero request, the first side to make the request will receive the token. If both

on that side and a one on the other side (see Truth Table III). That requestsarriveatthesametime,theassignmentwillbearbitrarilymade

semaphorecannowonlybemodifiedbythesideshowingthezero.When to one port or the other.

aoneiswrittenintothesamelocationfromthesameside,theflagwillbe

One caution that should be noted when using semaphores is that

settoaoneforbothsides(unlessasemaphorerequestfromtheotherside semaphoresalonedonotguaranteethataccesstoaresourceissecure.

ispending)andthencanbewrittentobybothsides.Thefactthattheside Aswithanypowerfulprogrammingtechnique,ifsemaphoresaremisused

whichisabletowriteazerointoasemaphoresubsequentlylocksoutwrites or misinterpreted, a software error can easily happen.

fromtheothersideiswhatmakessemaphoreflagsusefulininterprocessor

Initializationofthesemaphoresisnotautomaticandmustbehandled

communications.(Athoroughdiscussionontheuseofthisfeaturefollows viatheinitializationprogramatpower-up.Sinceanysemaphorerequest

shortly.)Azerowrittenintothesamelocationfromtheothersidewillbe flagwhichcontainsazeromustberesettoaone,allsemaphoresonboth

storedinthesemaphorerequestlatchforthatsideuntilthesemaphoreis sidesshouldhaveaonewrittenintothematinitializationfrombothsides

freedbythefirstside.

to assure that they will be free when needed.

When a semaphore flag is read, its value is spread into all data bits

so that a flag that is a one reads as a one in all data bits and a flag con-

tainingazeroreadsasallzeros.Thereadvalueislatchedintooneside’s

output register when that side's semaphore select (SEM) and output

enable(OE)signalsgoactive.Thisservestodisallowthesemaphorefrom

changingstateinthemiddleofareadcycleduetoawritecyclefromthe

otherside.Becauseofthislatch,arepeatedreadofasemaphoreinatest

loopmustcauseeithersignal(SEMorOE)togoinactiveortheoutputwill

never change.

UsingSemaphores—SomeExamples

Perhapsthesimplestapplicationofsemaphoresistheirapplicationas

resourcemarkersfortheIDT7025’sDual-PortRAM.Saythe8Kx16RAM

wastobedividedintotwo4Kx16blockswhichweretobededicatedat

anyonetimetoservicingeithertheleftorrightport.Semaphore0could

be used to indicate the side which would control the lower section of

memory,andSemaphore1couldbedefinedastheindicatorfortheupper

sectionofmemory.

AsequenceWRITE/READmustbeusedbythesemaphoreinorder

to guarantee that no system level contention will occur. A processor

requestsaccesstosharedresourcesbyattemptingtowriteazerointoa

semaphorelocation.Ifthesemaphoreisalreadyinuse,thesemaphore

requestlatchwillcontainazero,yetthesemaphoreflagwillappearasone,

afactwhichtheprocessorwillverifybythesubsequentread(seeTruth

TableIII).Asanexample,assumeaprocessorwritesazerototheleftport

atafreesemaphorelocation.Onasubsequentread,theprocessorwill

verifythatithaswrittensuccessfullytothatlocationandwillassumecontrol

overtheresourceinquestion.Meanwhile,ifaprocessorontherightside

attemptstowriteazerotothesamesemaphoreflagitwillfail, aswillbe

verifiedbythefactthataonewillbereadfromthatsemaphoreontheright

side during subsequent read. Had a sequence of READ/WRITE been

usedinstead,systemcontentionproblemscouldhaveoccurredduringthe

gap between the read and write cycles.

Totakearesource, inthisexamplethelower4KofDual-PortRAM,

the processor on the left port could write and then read a zero in to

Semaphore0.Ifthistaskweresuccessfullycompleted(azerowasread

back rather than a one), the left processor would assume control

of the lower 4K. Meanwhile the right processor was attempting to gain

controlofthe resourceaftertheleftprocessor,itwouldreadbackaone

inresponsetothezeroithadattemptedtowriteintoSemaphore0.Atthis

point,thesoftwarecouldchoosetotryandgaincontrolofthesecond4K

sectionbywriting,thenreadingazerointoSemaphore1.Ifitsucceeded

ingainingcontrol,itwouldlockouttheleftside.

Once the left side was finished with its task, it would write a one to

Semaphore 0 and may then try to gain access to Semaphore 1. If

Semaphore1wasstilloccupiedbytherightside,theleftsidecouldundo

itssemaphorerequestandperformothertasksuntilitwasabletowrite,then

readazerointoSemaphore1.Iftherightprocessorperformsasimilartask

withSemaphore0,thisprotocolwouldallowthetwoprocessorstoswap

4K blocks of Dual-Port RAM with each other.

Itisimportanttonotethatafailedsemaphorerequestmustbefollowed

byeitherrepeatedreadsorbywritingaoneintothesamelocation. The

reasonforthisiseasilyunderstoodbylookingatthesimplelogicdiagram

ofthesemaphoreflaginFigure4.Twosemaphorerequestlatchesfeed

The blocks do not have to be any particular size and can even be

6.2402

IDT7025S/L

High-Speed 8K x 16 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

variable, depending upon the complexity of the software using the been performed, both processors can access their assigned RAM

semaphoreflags.AlleightsemaphorescouldbeusedtodividetheDual- segmentsatfullspeed.

Port RAM or other shared resources into eight parts. Semaphores can

evenbeassigneddifferentmeaningsondifferentsidesratherthanbeing case,blockarbitrationisveryimportant.Forthisapplicationoneprocessor

given a common meaning as was shown in the example above. mayberesponsibleforbuildingandupdatingadatastructure.Theother

Anotherapplicationisintheareaofcomplexdatastructures.Inthis

Semaphores are a useful form of arbitration in systems like disk processorthenreadsandinterpretsthatdatastructure.Iftheinterpreting

interfaceswheretheCPUmustbelockedoutofasectionofmemoryduring processorreadsanincompletedatastructure,amajorerrorconditionmay

atransferandtheI/Odevicecannottolerateanywaitstates.Withtheuse exist.Therefore,somesortofarbitrationmustbeusedbetweenthetwo

ofsemaphores,oncethetwodeviceshasdeterminedwhichmemoryarea differentprocessors.Thebuildingprocessorarbitratesfortheblock,locks

was“off-limits”totheCPU,boththeCPUandtheI/Odevicescouldaccess itandthenisabletogoinandupdatethedatastructure.Whentheupdate

theirassignedportionsofmemorycontinuouslywithoutanywaitstates. is completed, the data structure block is released. This allows the

Semaphoresarealsousefulinapplicationswherenomemory“WAIT” interpretingprocessortocomebackandreadthecompletedatastructure,

stateisavailableononeorbothsides.Onceasemaphorehandshakehas therebyguaranteeingaconsistentdatastructure.

L PORT

SEMAPHORE

R PORT

SEMAPHORE

REQUEST FLIP FLOP

0

D

0

D

Q

WRITE

SEMAPHORE

READ

SEMAPHORE

READ

.

2683 drw 20

Figure 4. IDT7025 Semaphore Logic

62.412

IDT7025S/L

High-Speed 8K x 16 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

OrderingInformation

A

XXXXX

A

999

A

Device

Type

Power

Speed

Package

Process/

Temperature

Range

Blank

8

Tube or Tray

Tape and Reel

Blank

I⁽¹⁾

B

Commercial (0°C to +70°C)

Industrial (-40°C to +85°C)

Military (-55°C to +125°C)

Compliant to MIL-PRF-38535 QML

Green

G

PF

G

J

100-pin TQFP (PN100-1)

84-pin PGA (G84-3)

84-pin PLCC (J84-1)

84-pin Flatpack (F84-2)

F

15

17

20

25

35

55

70

Commercial Only

Commercial, Industrial & Military

Commercial & Military

Commercial, Industrial & Military

Military Only

Speed in nanoseconds

S

L

Standard Power

Low Power

7025

128K (8K x 16) Dual-Port RAM

2683 drw 21

NOTES:

1. Industrial range is available on selected PLCC packages in standard power.

Forotherspeeds,packagesandpowerscontactyoursalesoffice.

LEADFINISH(SnPb)partsareinEOLprocess.ProductDiscontinuationNotice-PDN#SP-17-02

DatasheetDocumentHistory

01/13/99:

Initiateddatasheetdocument history

Convertedtonewformat

Cosmeticandtypographicalcorrections

Pages2and3Addedadditionalnotestopinconfigurations

Page 11 Fixedtypographicalerror

05/19/99:

06/03/99:

Changeddrawingformat

Page 1 Corrected DSC number

04/04/00:

05/22/00:

09/13/01:

ReplacedIDTlogo

Page 7 FixedtypoinDataRetentionchart

Changed ±500mV to 0mV in notes

Page 5 Increasedstoragetemperatureparameter

ClarifiedTA parameter

Page 6 DCElectricalparameters–changedwordingfrom"open"to"disabled"

Page 2 & 3 Added date revision for pin configurations

Page 6 AddedIndustrialtemptothecolumnheadingfor20nstoDCElectricalCharacteristics

Pages8,10,13&15 AddedIndustrialtemptothecolumnheadingsfor20nstoACElectricalCharacteristics

Pages5,6,8,10,13&15 RemovedIndustrialtempfootnotefromalltables

Page 21 AddedIndustrialtempto20nsinorderinginformation

Page 22 Removed "IDT" from orderable part number

10/21/08:

07/17/12:

03/07/18:

Page 22 AddedT&Randgreenindicatorstoorderinginformation

ProductDiscontinuationNotice-PDN#SP-17-02

Last time buy expires June 15, 2018

CORPORATE HEADQUARTERS

6024 Silver Creek Valley Road

San Jose, CA 95138

for SALES:

for Tech Support:

408-284-2794

DualPortHelp@idt.com

800-345-7015 or 408-284-8200

fax: 408-284-2775

www.idt.com

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

6.2422


型号：	7025S55FGI8
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	HIGH-SPEED 8K x 16 DUAL-PORT STATIC RAM
文件：	总22页 (文件大小：201K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

7025S55FGI8 [IDT]

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