709089S12PF9 [IDT]
Dual-Port SRAM, 64KX8, 25ns, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100;
| 型号： | 709089S12PF9 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Dual-Port SRAM, 64KX8, 25ns, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100 静态存储器 |
| 文件： | 总18页 (文件大小：306K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HIGH-SPEED 64/32K x 8
SYNCHRONOUS
IDT709089/79S/L
DUAL-PORT STATIC RAM
Features:
◆
◆
True Dual-Ported memory cells which allow simultaneous
Dual chip enables allow for depth expansion without
additional logic
Full synchronous operation on both ports
– 4ns setup to clock and 1ns hold on all control, data,
and address inputs
access of the same memory location
High-speed clock to data access
◆
◆
– Commercial:6/7/9/12/15ns(max.)
– Industrial: 12ns (max.)
Low-power operation
◆
– Data input, address, and control registers
– IDT709089/79S
Active: 950mW (typ.)
Standby: 5mW (typ.)
– IDT709089/79L
Active: 950mW (typ.)
Standby: 1mW (typ.)
Flow-Through or Pipelined output mode on either port via
the FT/PIPE pin
Counter enable and reset features
– Fast 6.5ns clock to data out in the Pipelined output mode
– Self-timed write allows fast cycle time
– 10ns cycle time, 100MHz operation in the Pipelined
output mode
TTL- compatible, single 5V (±10%) power supply
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
◆
◆
◆
◆
Available in 100-pin Thin Quad Flatpack (TQFP) package
◆
Functional Block Diagram
R/W
OE
R
R/W
L
OE
L
R
CE0R
CE1R
CE0L
CE1L
1
0
1
0
0/1
0/1
0
1
0
1
FT/PIPE
L
0/1
0/1
FT/PIPE
R
I/O0L - I/O7L
I/O0R - I/O7R
I/O
Control
I/O
Control
(1)
(1)
A
15L
A
A
15R
Counter/
Address
Reg.
Counter/
Address
Reg.
C0LRK
R
MEMORY
ARRAY
A
0L
CLK
L
ADS
R
ADS
L
CNTEN
R
CNTEN
L
CNTRST
R
CNTRST
L
.
3242 drw 01
NOTE:
1. A15X is a NC for IDT709079.
JUNE 2004
1
DSC-3242/12
©2004 IntegratedDeviceTechnology,Inc.
IDT709089/79S/L
High-Speed 64/32K x 8 Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Description:
Withaninputdataregister,theIDT709089/79hasbeenoptimizedfor
applications having unidirectional or bidirectional data flow in bursts.
An automatic power down feature, controlled by CE0and CE1, permits
the on-chip circuitry of each port to enter a very low standby power
mode. Fabricated using IDT’s CMOS high-performance technology,
these devices typically operate on only 950mW of power.
TheIDT709089/79isahigh-speed64/32Kx8bitsynchronous Dual-
Port RAM. The memory array utilizes Dual-Port memory cells to allow
simultaneousaccessofanyaddressfrombothports.Registersoncontrol,
data,andaddressinputsprovideminimalsetupandholdtimes.Thetiming
latitudeprovidedbythisapproachallowssystemstobedesignedwithvery
shortcycletimes.
Pin Configuration(1,2,3)
08/19/03
Index
10099 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1
NC
NC
NC
NC
75
74
73
2
A
A
A
A
A
A
A
A
A
7R
3
A
A
A
7L
8L
9L
8R
4
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
9R
5
10R
11R
12R
13R
14R
15R
6
A
A
A
A
A
A
10L
11L
12L
13L
14L
15L
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
IDT709089/79PF
(5)
PN100-1
NC
GND
NC
NC
NC
NC
CE0R
CE1R
NC
V
CC
100-PIN TQFP
(6)
NC
NC
NC
NC
CE0L
CE1L
TOP VIEW
CNTRST
R/W
R
CNTRST
R/W
OE
FT/PIPE
L
R
L
OER
L
FT/PIPE
GND
NC
R
L
NC
NC
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
3242 drw 02
NOTES:
1. A15X is a NC for IDT709079.
2. All VCC pins must be connected to power supply.
3. All GND pins must be connected to ground supply.
4. Package body is approximately 14mm x 14mm x 1.4mm.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
6.42
2
IDT709089/79S/L
High-Speed 64/32K x 8 Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
PinNames
Left Port
Right Port
CE0R, CE1R
R/W
OE
Names
Chip Enables
CE0L, CE1L
R/W
OE
L
R
Read/Write Enable
Output Enable
Address
L
R
(1)
(1)
A0L - A15L
A0R - A15R
I/O0L - I/O7L
CLK
I/O0R - I/O7R
CLK
Data Input/Output
Clock
L
R
Address Strobe
Counter Enable
Counter Reset
Flow-Through/Pipeline
Power
ADS
CNTEN
CNTRST
FT/PIPE
L
ADS
CNTEN
CNTRST
FT/PIPE
R
L
R
NOTE:
1. A15X is a NC for IDT709079.
L
R
L
R
V
CC
GND
Ground
3242 tbl 01
Truth Table I—
Read/Write and Enable Control(1,2,3)
CLK
CE
1
R/W
I/O0-7
Mode
OE
CE0
X
H
X
L
X
X
High-Z Deselected
High-Z Deselected
↑
X
L
X
↑
X
H
H
H
L
D
IN
Write
Read
↑
L
L
H
DOUT
↑
H
X
L
X
High-Z Outputs Disabled
3242 tbl 02
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. ADS, CNTEN, CNTRST = X.
3. OE is an asynchronous input signal.
Truth Table II—Address Counter Control(1,2)
Previous
Internal
Address
Internal
Address
Used
External
Address
MODE
CLK
↑
I/O(3)
DI/O (n) External Address Used
ADS CNTEN CNTRST
An
X
X
An
An
L(4)
X
H
H
An + 1
An + 1
H
L(5)
H
D
I/O(n+1) Counter Enabled—Internal Address generation
↑
↑
X
An + 1
X
H
H
D
I/O(n+1) External Address Blocked—Counter disabled (An + 1 reused)
X
A0
X
X
L(4)
DI/O(0)
Counter Reset to Address 0
↑
5640 tbl 03
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. CE0 and OE = VIL; CE1 and R/W = VIH.
3. Outputs configured in Flow-Through Output mode; if outputs are in Pipelined mode the data out will be delayed by one cycle.
4. ADS is independent of all other signals including CE0 and CE1.
5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other signals including CE0 and CE1.
6.342
IDT709089/79S/L
High-Speed 64/32K x 8 Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Recommended Operating
Recommended DC Operating
Temperature and Supply Voltage(1) Conditions
Symbol
Parameter
Min.
4.5
Typ.
Max. Unit
Grade
Ambient
Temperature
GND
VCC
V
CC
Supply Voltage
5.0
5.5
0
V
V
V
Commercial
0OC to +70OC
0V
0V
5.0V
5.0V
+
+
10%
GND
Ground
0
0
Industrial
-40OC to +85OC
10%
____
V
IH
IL
Input High Voltage
Input Low Voltage
2.2
6.0(1)
0.8
3242 tbl 04
____
NOTES:
V
-0.5(2)
V
1. This is the parameter TA. This is the "instant on" case temperature.
3242 tbl 05
NOTES:
1. VTERM must not exceed VCC + 10%.
2. VIL > -1.5V for pulse width less than 10ns.
Absolute Maximum Ratings(1)
Capacitance(1)
(TA = +25°C, f = 1.0MHz)
Symbol
Rating
Commercial
& Industrial
Unit
Symbol
Parameter
Input Capacitance
Output Capacitance
Conditions(2 )
IN = 3dV
OUT = 3dV
Max. Unit
(2)
V
TERM
Terminal Voltage
with Respect to GND
-0.5 to +7.0
V
CIN
V
9
pF
(3)
OUT
C
V
10
pF
T
BIAS
STG
JN
OUT
Temperature Under Bias
Storage Temperature
Junction Temperature
DC Output Current
-55 to +125
-65 to +150
+150
oC
oC
oC
3242 tbl 07
NOTES:
T
1. These parameters are determined by device characterization, but are not
production tested.
2. 3dV references the interpolated capacitance when the input and output
switch from 0V to 3V or from 3V to 0V.
T
I
50
mA
3. COUT also references CI/O.
3242 tbl 06
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VTERM must not exceed VCC+ 10% for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of VTERM > VCC + 10%.
3. Ambient Temperature Under DC Bias. No AC Conditions. Chip Deselected.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VCC = 5.0V ± 10%)
709089/79S/L
Min. Max.
Symbol
|ILI
|ILO
Parameter
Input Leakage Current(1)
Test Conditions
CC = 5.5V, VIN = 0V to VCC
CE
OL = +4mA
OH = -4mA
Unit
µA
µA
V
___
___
___
|
V
10
10
|
Output Leakage Current
Output Low Voltage
Output High Voltage
0
= VIH or CE1 = VIL, VOUT = 0V to VCC
V
OL
OH
I
0.4
___
V
I
2.4
V
3242 tbl 08
NOTE:
1. At VCC < 2.0V input leakages are undefined.
6.42
4
IDT709089/79S/L
High-Speed 64/32K x 8 Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(6) (VCC = 5V ± 10%)
709089/79X6
Com'l Only
709089/79X7
Com'l Only
709089/79X9
Com'l Only
Symbol
Parameter
Test Condition
Version
COM'L
Typ.(4)
Max.
Typ.(4)
Max.
Typ.(4)
Max.
Unit
ICC
Dynamic Operating
Current
(Both Ports Active)
S
L
270
270
585
525
250
250
490
440
210
210
390
350
mA
CEL and CER= VIL
Outputs Disabled
(1)
f = fMAX
____
____
____
____
____
____
____
____
____
____
____
____
IND
S
L
ISB1
ISB2
ISB3
ISB4
Standby Current
(Both Ports - TTL
Level Inputs)
COM'L
IND
S
L
80
80
205
175
65
65
170
145
50
50
135
115
mA
mA
CEL = CER = VIH
(1)
f = fMAX
____
____
____
____
____
____
____
____
____
____
____
____
S
L
Standby Current
(One Port - TTL
Level Inputs)
COM'L
IND
S
L
180
180
405
360
160
160
340
295
140
140
270
240
CE"A" = VIL and
(3)
CE"B" = VIH
Active Port Outputs
Disabled, f=fMAX
____
____
____
____
____
____
____
____
____
____
____
____
(1)
S
L
Full Standby Current
(Both Ports -
CMOS Level Inputs)
Both Ports CER and
CEL > VCC - 0.2V
VIN > VCC - 0.2V or
VIN < 0.2V, f = 0(2)
COM'L
IND
S
L
1.0
0.2
15
5
1.0
0.2
15
5
1.0
0.2
15
5
mA
____
____
____
____
____
____
____
____
____
____
____
____
S
L
Full Standby Current
(One Port -
CMOS Level Inputs)
mA
COM'L
IND
S
L
170
170
395
340
150
150
330
290
130
130
245
225
CE"A" < 0.2V and
CE"B" > VCC - 0.2V(5)
VIN > VCC - 0.2V or
____
____
____
____
____
____
____
____
____
____
____
____
S
L
VIN < 0.2V, Active Port Outputs
Disabled, f = fMAX
(1)
3242 tbl 09
NOTES:
1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS" at input levels of
GND to 3V.
2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. VCC = 5V, TA = 25°C for Typ, and are not production tested. ICC DC(f=0) = 150mA (Typ).
5. CEX = VIL means CE0X = VIL and CE1X = VIH
CEX = VIH means CE0X = VIH or CE1X = VIL
CEX < 0.2V means CE0X < 0.2V and CE1X > VCC - 0.2V
CEX > VCC - 0.2V means CE0X > VCC - 0.2V or CE1X < 0.2V
"X" represents "L" for left port or "R" for right port.
6. 'X' in part numbers indicate power (S or L).
6.542
IDT709089/79S/L
High-Speed 64/32K x 8 Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(6) (VCC = 5V ± 10%)(cont'd)
709089/79X12
Com'l
709089/79X15
Com'l Only
& Ind
Symbol
Parameter
Test Condition
and CE = VIL
Version
COM'L
Typ.(4)
Max.
Typ.(4)
Max.
Unit
ICC
Dynamic Operating
Current
(Both Ports Active)
S
L
200
200
345
305
190
190
325
285
mA
CE
L
R
(1)
Outputs Disabled f = fMAX
____
____
____
____
IND
S
L
200
200
380
340
I
SB1
Standby Current
(Both Ports - TTL
Level Inputs)
COM'L
IND
S
L
50
50
110
90
50
50
110
90
mA
mA
CE
L = CER = VIH
(1)
f = fMAX
____
____
____
____
S
L
50
50
125
105
ISB2
Standby Current
(One Port - TTL
Level Inputs)
COM'L
IND
S
L
130
130
230
200
120
120
220
190
CE"A" = VIL and
(3)
CE"B" = VIH
Active Port Outputs
____
____
____
____
(1)
S
L
130
130
245
215
Disabled, f=fMAX
ISB3
Full Standby Current
(Both Ports -
CMOS Level Inputs)
Both Ports CE
R
and
COM'L
IND
S
L
1.0
0.2
15
5
1.0
0.2
15
5
mA
CE
L
> VCC - 0.2V
V
IN > VCC - 0.2V or
____
____
____
____
IN < 0.2V, f = 0(2)
S
L
1.0
0.2
15
5
V
ISB4
Full Standby Current
(One Port -
CMOS Level Inputs)
mA
COM'L
IND
S
L
120
120
205
185
110
110
195
175
CE"A" < 0.2V and
CE"B" > VCC - 0.2V(5)
V
IN > VCC - 0.2V or
IN < 0.2V, Active Port Outputs
____
____
____
____
S
L
120
120
220
200
V
(1)
Disabled, f = fMAX
3242 tbl 09a
NOTES:
1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS" at input levels of
GND to 3V.
2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. VCC = 5V, TA = 25°C for Typ, and are not production tested. ICC DC(f=0) = 150mA (Typ).
5. CEX = VIL means CE0X = VIL and CE1X = VIH
CEX = VIH means CE0X = VIH or CE1X = VIL
CEX < 0.2V means CE0X < 0.2V and CE1X > VCC - 0.2V
CEX > VCC - 0.2V means CE0X > VCC - 0.2V or CE1X < 0.2V
"X" represents "L" for left port or "R" for right port.
6. 'X' in part numbers indicate power (S or L).
6.42
6
IDT709089/79S/L
High-Speed 64/32K x 8 Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Test Conditions
Input Pulse Levels
GND to 3.0V
3ns Max.
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
1.5V
1.5V
Figures 1,2 and 3
3242 tbl 10
5V
5V
893Ω
893Ω
DATAOUT
DATAOUT
30pF
347Ω
5pF*
347Ω
3242 drw 04
3242 drw 05
Figure 1. AC Output Test load.
Figure 2. Output Test Load
(For tCKLZ, tCKHZ, tOLZ, and tOHZ).
*Including scope and jig.
8
-10 pF is the I/O capacitance
of this device, and 30pF is the
AC Test Load Capacitance
7
6
5
4
tCD
tCD
(Typical, ns)
1
,
2
3
2
1
0
20 40 60 80 100 120 140 160 180 200
Capacitance (pF)
,
-1
3242 drw 06
Figure 3. Typical Output Derating (Lumped Capacitive Load).
6.742
IDT709089/79S/L
High-Speed 64/32K x 8 Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating Temperature Range
(Read and Write Cycle Timing)(3,4) (VCC = 5V ± 10%, TA = 0°C to +70°C)
709089/79X6
Com'l Only
709089/79X7
Com'l Only
709089/79X9
Com'l Only
709089/79X12
Com'l
709089/79X15
Com'l Only
& Ind
Symbol
Parameter
Clock Cycle Time (Flow-Through)(2)
Min.
Max.
Min.
22
Max.
Min.
Max.
Min.
30
20
12
12
8
Max.
Min.
35
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
____
____
____
____
____
t
CYC1
CYC2
CH1
CL1
CH2
CL2
19
10
6.5
6.5
4
25
15
12
12
6
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
Clock Cycle Time (Pipelined)(2)
Clock High Time (Flow-Through)(2)
Clock Low Time (Flow-Through)(2)
Clock High Time (Pipelined)(2)
Clock Low Time (Pipelined)(2)
Clock Rise Time
12
25
t
7.5
7.5
5
12
t
12
t
10
t
4
5
6
8
10
____
____
____
____
____
tR
3
3
3
3
3
____
____
____
____
____
tF
Clock Fall Time
3
3
3
3
3
____
____
____
____
____
t
SA
HA
SC
HC
SW
HW
SD
HD
SAD
HAD
SCN
HCN
SRST
HRST
OE
OLZ
OHZ
CD1
CD2
DC
CKHZ
CKLZ
Address Setup Time
Address Hold Time
3.5
0
4
0
4
0
4
0
4
0
4
0
4
0
4
4
1
4
1
4
1
4
1
4
1
4
1
4
4
1
4
1
4
1
4
1
4
1
4
1
4
4
1
4
1
4
1
4
1
4
1
4
1
4
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
t
Chip Enable Setup Time
Chip Enable Hold Time
R/W Setup Time
3.5
0
t
t
3.5
0
t
R/W Hold Time
t
Input Data Setup Time
Input Data Hold Time
ADS Setup Time
3.5
0
t
t
3.5
0
t
ADS Hold Time
t
3.5
0
CNTEN Setup Time
t
CNTEN Hold Time
t
3.5
CNTRST Setup Time
CNTRST Hold Time
t
0
0
1
1
1
____
____
____
____
____
t
Output Enable to Data Valid
6.5
7.5
9
12
15
(1)
____
____
____
____
____
t
Output Enable to Output Low-Z
2
2
2
2
2
t
Output Enable to Output High-Z(1)
Clock to Data Valid (Flow-Through)(2)
Clock to Data Valid (Pipelined)(2)
Data Output Hold After Clock High
Clock High to Output High-Z(1)
Clock High to Output Low-Z(1)
1
7
1
7
1
7
1
7
1
7
____
____
____
____
____
t
15
18
20
25
30
____
____
____
____
____
t
6.5
7.5
9
12
15
____
____
____
____
____
t
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
t
9
9
9
9
9
____
____
____
____
____
t
Port-to-Port Delay
____
____
____
____
____
____
____
____
____
____
t
CWDD
Write Port Clock High to Read Data Delay
Clock-to-Clock Setup Time
24
9
28
10
35
15
40
15
50
20
ns
tCCS
ns
3242 tbl 11
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). This parameter is guaranteed by device
characterization, but is not production tested.
2. The Pipelined output parameters (tCYC2, tCD2) apply to either or both left and right ports when FT/PIPE = VIH. Flow-through parameters (tCYC1, tCD1) apply when
FT/PIPE = VIL for that port.
3. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE) and FT/PIPE. FT/PIPE should be treated as a DC
signal, i.e. steady state during operation.
4. 'X' in part number indicates power rating (S or L).
6.42
8
IDT709089/79S/L
High-Speed 64/32K x 8 Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Read Cycle for
Flow-Through Output (FT/PIPE"X" = VIL)(3,6)
tCYC1
t
CH1
t
CL1
CLK
CE0
t
SC
tHC
tSC
tHC
CE1
R/W
t
HW
t
SW
SA
t
HA
t
ADDRESS(5)
An
An + 1
An + 2
An + 3
(1)
t
DC
t
CD1
tCKHZ
Qn
Qn + 1
Qn + 2
DATAOUT
(1)
(1)
t
CKLZ
tDC
(1)
tOHZ
tOLZ
,
OE(2)
tOE
3242 drw 07
Timing Waveform of Read Cycle for Pipelined Output
(FT/PIPE"X" = VIH)(3,6)
tCYC2
t
CH2
t
CL2
CLK
CE
0
t
SC
(4)
t
HC
tSC
tHC
CE1
R/W
tHW
tSW
t
SA
tHA
ADDRESS(5)
DATAOUT
An
An + 1
An + 2
Qn
An + 3
(1 Latency)
t
DC
tCD2
Qn + 1
Qn + 2
(1)
t
CKLZ
(1)
(1)
t
OHZ
tOLZ
(2)
OE
tOE
NOTES:
3242 drw 08
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.
3. ADS = VIL, CNTEN and CNTRST = VIH.
4. The output is disabled (High-Impedance state) by CE0 = VIH or CE1 = VIL following the next rising edge of clock. Refer to Truth Table 1.
5. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use
only.
6. "X" denotes Left or Right port. The diagram is with respect to that port.
6.942
IDT709089/79S/L
High-Speed 64/32K x 8 Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of a Bank Select Pipelined Read(1,2)
t
CYC2
tCH2
tCL2
CLK
ADDRESS(B1)
CE0(B1)
t
SA
tHA
A6
A5
A4
A3
A
2
A
0
A1
tSC
tHC
t
SC
tHC
(3)
tCD2
tCD2
tCKHZ
tCD2
Q
0
Q3
Q
1
DATAOUT(B1)
ADDRESS(B2)
(3)
(3)
tDC
tCKLZ
t
DC
tCKHZ
t
SA
tHA
A6
A5
A4
A3
A2
A
0
A1
tSC
tHC
CE0(B2)
tSC
tHC
(3)
tCD2
tCKHZ
tCD2
DATAOUT(B2)
Q4
Q2
(3)
(3)
tCKLZ
tCKLZ
3242 drw 09
Timing Waveform of a Bank Select Flow-Through Read(6,7)
t
CYC1
tCH1
tCL1
CLK
tSA
tHA
A6
A5
A4
A3
A2
A0
A1
ADDRESS(B1)
tSC
tHC
CE0(B1)
tSC
tHC
(1)
tCD1
tCD1
t
CKHZ
t
CD1
(1)
tCD1
D0
D3
D
5
6
D1
DATAOUT(B1)
ADDRESS(B2)
(1)
(1)
tDC
t
CKLZ
tCKLZ
tDC
tCKHZ
tSA
tHA
A
A5
A4
A3
A2
A
0
A1
tSC
tHC
CE0(B2)
tSC
tHC
(1)
(1)
t
CD1
t
CKHZ
t
CD1
(1)
tCKHZ
D4
DATAOUT(B2)
D2
(1)
t
CKLZ
tCKLZ
3242 drw 09a
NOTES:
1. B1 Represents Bank #1; B2 Represents Bank #2. Each Bank consists of one IDT709089/79 for this waveform, and are setup for depth expansion in this
example. ADDRESS(B1) = ADDRESS(B2) in this situation.
2. OE and ADS = VIL; CE1(B1), CE1(B2), R/W, CNTEN, and CNTRST = VIH.
3. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
4. CE0 and ADS = VIL; CE1, CNTEN, and CNTRST = VIH.
5. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to.
6. If tCCS < maximum specified, then data from right port READ is not valid until the maximum specified for tCWDD.
If tCCS > maximum specified, then data from right port READ is not valid until tCCS + tCD1. tCWDD does not apply in this case.
7. All timing is the same for both Left and Right ports. Port "A" may be either Left or Right port. Port "B" is the opposite of Port "A".
6.42
10
IDT709089/79S/L
High-Speed 64/32K x 8 Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform with Port-to-Port Flow-Through Read(1,2,3,5)
CLK "A"
tSW
tHW
R/W"A"
ADDRESS"A"
DATAIN"A"
CLK"B"
t
SA
MATCH
SD HD
VALID
tHA
NO
MATCH
t
t
(4)
tCCS
tCD1
R/W"B"
t
HW
HA
t
SW
t
tSA
NO
MATCH
ADDRESS"B"
DATAOUT"B"
MATCH
(4)
tCD1
tCWDD
VALID
VALID
t
DC
tDC
3242 drw 10
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. CE0 and ADS = VIL; CE1, CNTEN, and CNTRST = VIH.
3. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to.
4. If tCCS < maximum specified, then data from right port READ is not valid until the maximum specified for tCWDD.
If tCCS > maximum specified, then data from right port READ is not valid until tCCS + tCD1. tCWDD does not apply in this case.
5. All timing is the same for both Left and Right ports. Port "A" may be either Left or Right port. Port "B" is the opposite of Port "A".
61.412
IDT709089/79S/L
High-Speed 64/32K x 8 Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Pipelined Read-to-Write-to-Read (OE = VIL)(3)
tCYC2
tCH2
tCL2
CLK
CE0
t
SC
tHC
CE1
tSW tHW
R/W
tSW tHW
(4)
An + 3
An + 4
An
An +1
An + 2
An + 2
ADDRESS
t
SA
tHA
t
SD
t
HD
DATAIN
Dn + 2
(1)
tCD2
(1)
tCD2
(2)
tCKHZ
tCKLZ
Qn + 3
Qn
DATAOUT
READ
NOP(5)
WRITE
READ
3242 drw 11
Timing Waveform of Pipelined Read-to-Write-to-Read (OE Controlled)(3)
t
CYC2
tCH2
tCL2
CLK
CE0
tSC
tHC
CE1
tSW tHW
R/W
tSW tHW
(4)
An + 4
An
An +1
An + 2
An + 3
Dn + 3
An + 5
ADDRESS
t
SA
tHA
t
SD
t
HD
DATAIN
Dn + 2
(1)
tCKLZ
tCD2
tCD2
(2)
Qn
Qn + 4
DATAOUT
(1)
OHZ
t
OE
READ
WRITE
READ
3242 drw 12
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
3. CE0 and ADS = VIL; CE1, CNTEN, and CNTRST = VIH.
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only.
5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
6.42
12
IDT709089/79S/L
High-Speed 64/32K x 8 Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform Flow-Through Read-to-Write-to-Read (OE = VIL)(3)
t
CYC1
tCH1
tCL1
CLK
CE0
tSC
tHC
CE1
tSW tHW
R/W
tSW tHW
(4)
An + 4
An
An + 3
An +1
An + 2
An + 2
ADDRESS
tSA
tHA
t
SD tHD
DATAIN
Dn + 2
tCD1
tCD1
tCD1
tCD1
(2)
Qn + 3
Qn
READ
Qn + 1
DATAOUT
(1)
(1)
tDC
tDC
tCKLZ
t
CKHZ
NOP(5)
WRITE
READ
3242 drw 13
TimingWaveformofFlow-ThroughRead-to-Write-to-Read(OEControlled)(3)
tCYC1
tCH1
tCL1
CLK
CE0
tSC tHC
CE1
tSW tHW
R/W
tSW tHW
(4)
An + 5
An
tSA tHA
An +1
An + 2
An + 3
Dn + 3
An + 4
ADDRESS
tSD tHD
DATAIN
Dn + 2
tOE
tCD1
tDC
tCD1
tCD1
(2)
Qn + 4
tDC
Qn
DATAOUT
OE
(1)
tCKLZ
(1)
tOHZ
READ
WRITE
READ
3242 drw 14
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. Output state (High, Low, or High-impedance is determined by the previous cycle control signals.
3. CE0 and ADS = VIL; CE1, CNTEN, and CNTRST = VIH.
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only.
5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
61.432
IDT709089/79S/L
High-Speed 64/32K x 8 Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Pipelined Read with Address Counter Advance(1)
t
CYC2
tCH2
tCL2
CLK
tSA
tHA
An
ADDRESS
tSAD
tHAD
ADS
t
SAD tHAD
CNTEN
t
SCN tHCN
tCD2
Qn + 2(2)
Qx - 1(2)
Qn + 3
Qn + 1
Qn
Qx
DATAOUT
tDC
READ
EXTERNAL
ADDRESS
READ
WITH
COUNTER
COUNTER
HOLD
READ WITH COUNTER
3242 drw 15
TimingWaveformof Flow-ThroughReadwithAddressCounterAdvance(1)
tCYC1
t
CH1
tCL1
CLK
tSA
tHA
An
ADDRESS
tSAD tHAD
tSAD
tHAD
ADS
tSCN
tHCN
CNTEN
tCD1
Qn + 3(2)
Qx(2)
Qn + 4
Qn + 1
Qn + 2
Qn
DATAOUT
tDC
READ
WITH
READ
EXTERNAL
ADDRESS
READ WITH COUNTER
COUNTER
HOLD
COUNTER
3242 drw 16
NOTES:
1. CE0 and OE = VIL; CE1, R/W, and CNTRST = VIH.
2. If there is no address change via ADS = VIL (loading a new address) or CNTEN = VIL (advancing the address), i.e. ADS = VIH and CNTEN = VIH, then the data output
remains constant for subsequent clocks.
6.42
14
IDT709089/79S/L
High-Speed 64/32K x 8 Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Address Counter Advance
(Flow-Through or Pipelined Outputs)(1)
t
CYC2
tCH2
tCL2
CLK
tSA
tHA
An
ADDRESS
INTERNAL(3)
ADDRESS
An(7)
An + 2
An + 4
An + 1
An + 3
t
SAD tHAD
ADS
CNTEN
tSD tHD
Dn + 4
Dn + 1
Dn + 3
Dn
Dn + 1
Dn + 2
DATAIN
WRITE
EXTERNAL
ADDRESS
WRITE
WITH COUNTER
WRITE
COUNTER HOLD
WRITE WITH COUNTER
3242 drw 17
Timing Waveform of Counter Reset (Pipelined Outputs)(2)
t
CYC2
tCH2
tCL2
CLK
tSA tHA
(4)
An + 2
An
An + 1
ADDRESS
INTERNAL(3)
ADDRESS
Ax(6)
0
An + 1
1
An
tSW tHW
R/W
ADS
t
SAD
SCN
tHAD
CNTEN
t
tHCN
tSRST
tHRST
CNTRST
tSD
tHD
D0
DATAIN
(5)
Qn
Q1
Q0
DATAOUT
COUNTER (6)
RESET
WRITE
ADDRESS 0
READ
ADDRESS 0
READ
READ
READ
ADDRESS 1
ADDRESS n ADDRESS n+1
3242 drw 18
NOTES:
1. CE0 and R/W = VIL; CE1 and CNTRST = VIH.
CE0 = VIL; CE1 = VIH.
2.
3. The "Internal Address" is equal to the "External Address" when ADS = VIL and equals the counter output when ADS = VIH.
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only.
5. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
6. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset. ADDR0 will be accessed. Extra cycles are shown here
simply for clarification.
7. CNTEN = VIL advances Internal Address from ‘An’ to ‘An +1’. The transition shown indicates the time required for the counter to advance. The ‘An +1’Address is written
to during this cycle.
61.452
IDT709089/79S/L
High-Speed 64/32K x 8 Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Depth and Width Expansion
FunctionalDescription
The IDT709089/79 features dual chip enables (refer to Truth Table
I)inordertofacilitaterapidandsimpledepthexpansionwithnorequire-
mentsforexternallogic.Figure4illustrateshowtocontrolthevariouschip
enables in order to expand two devices in depth.
The IDT709089/79 provides a true synchronous Dual-Port Static
RAM interface. Registered inputs provide minimal set-up and hold
times on address, data, and all critical control inputs. All internal
registers are clocked on the rising edge of the clock signal, however,
the self-timed internal write pulse is independent of the LOW to HIGH
transition of the clock signal.
The IDT709089/79 can also be used in applications requiring ex-
pandedwidth,asindicatedinFigure4.Sincethebanksareallocatedat
thediscretionoftheuser,theexternalcontrollercanbesetuptodrivethe
input signals for the various devices as required to allow for 16-bit or
wider applications.
An asynchronous output enable is provided to ease asynchronous
bus interfacing. Counter enable inputs are also provided to stall the
operation of the address counters for fast interleaved memory appli-
cations.
A HIGH on CE0 or a LOW on CE1 for one clock cycle will power
down the internal circuitry to reduce static power consumption.
MultiplechipenablesalloweasierbankingofmultipleIDT709089/79'sfor
depth expansion configurations. When the Pipelined output mode is
enabled, two cycles are required with CE0 LOW and CE1 HIGH to re-
activate the outputs.
(1)
A15/A14
IDT709089/79
IDT709089/79
CE0
CE0
VCC
VCC
CE1
CE1
Control Inputs
Control Inputs
IDT709089/79
IDT709089/79
CE1
CE1
CE0
CE0
CNTRST
CLK
Control Inputs
Control Inputs
,
ADS
CNTEN
R/W
3242 drw 19
OE
Figure 4. Depth and Width Expansion with IDT709089/79
NOTE:
1. A15 is for IDT709089, A14 is for IDT709079.
6.42
16
IDT709089/79S/L
High-Speed 64/32K x 8 Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Ordering Information
IDT XXXXX
A
99
A
A
Device
Type
Power Speed
Package
Process/
Temperature
Range
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
Blank
I(1)
PF
100-pin TQFP (PN100-1)
6
Commercial Only
Commercial Only
7
Speed in nanoseconds
Commercial Only
9
12
15
Commercial & Industrial
Commercial Only
S
L
Standard Power
Low Power
709089 512K (64K x 8-Bit) Synchronous Dual-Port RAM
709079 256K (32K x 8-Bit) Synchronous Dual-Port RAM
3242 drw 20
NOTE:
1. Contact your local sales office for industrial temp range for other speeds, packages and powers.
Ordering Information for Flow-through Devices
Old Flow-through Part
New Combined Part
70908S/L20
709089S/L9
70908S/L25
709089S/L12
70908S/L30
709089S/L15
3242 tbl 12
IDT Clock Solution for IDT709089/79 Dual-Port
Dual-Port I/O Specitications
Clock Specifications
Input Duty
Cycle
IDT
PLL
IDT
Non-PLL
IDT Dual-Port
Part Number
Input
Capacitance
Maximum
Frequency Tolerance
Jitter
Voltage
5
I/O
Clock Device Clock Device
Requirement
49FCT805T
FCT88915TT 49FCT806T
74FCT807T
709089/79
TTL
9pF
40%
100
150ps
3242 tbl 13
61.472
IDT709089/79S/L
High-Speed 64/32K x 8 Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
DatasheetDocumentHistory
1/12/99:
Initiated datasheet document history
Converted to new format
Cosmetic and typographical corrections
Added additional notes to pin configurations
Page 15 AddedDepthandWidthExpansionnote
Changeddrawingformat
6/7/99:
Page 4 Deleted note 6 for Table II
Replaced IDT logo
Page 1 Removed "Separate upper-byte..." line
CombinedPipelined709089familyandFlow-through70908familyofferingsintoonedatasheet
Changed±200mVinwaveformnotesto0mV
11/10/99:
12/22/99:
1/12/00:
Addedcorrespondingpartchartwithorderinginformation
Pages 8 and 9 Changed ±220mV waveform notes to 0mV
Page 9 Changed "Operation" in heading to "Pipelined Output", fixed drawing 08
RemovedPGApackage
2/18/00:
5/24/00:
Page 3 Changed information in Truth Table II
Page 4 Increasedstoragetemperatureparameters
ClarifiedTAparameter
Page 5 DCElectricalparameters–changedwordingfrom"open"to"disabled"
AddedIndustrialTemperatureRangesandremovedrelatednotes
Page 2 Addeddaterevisionforpinconfiguration
Page5&7 Removedindustrialtempfromcolumnheadingsandvaluesfor15nsfromAC&DCElectricalCharacteristics
Page 16 Removedindustrialofferingfrom15nsorderinginfoandaddedindustrialtempfootnote
Page 1 & 17 Replaced IDT TM logo with ® logo
01/10/02:
06/21/04:
Consolidatedmultipledevicesintoonedatasheet
RemovedPreliminarystatusfromdatasheet
Page 4 AddedJunctionTemperaturetoAbsoluteMaximumRatingsTable
AddedAmbientTemperaturefootnote
Page 5 Added6ns&7nsspeedDCtimingnumberstotheDCElectricalCharacteristicsTable
Page 8 Added6ns&7nsspeedACtimingnumberstotheACElectricalCharacteristicsTable
Page 17 Added 6ns & 7ns speed grades to ordering information
Added IDT Clock Solution Table
Page 1 & 18 Replaced old logo with new TM logo
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6.42
18
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