709089S15PFGI [IDT]
HIGH-SPEED 64/32K x 8 SYNCHRONOUS DUAL-PORT STATIC RAM;
| 型号： | 709089S15PFGI |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | HIGH-SPEED 64/32K x 8 SYNCHRONOUS DUAL-PORT STATIC RAM |
| 文件： | 总17页 (文件大小：192K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HIGH-SPEED 64/32K x 8
SYNCHRONOUS
IDT709089/79S/L
DUAL-PORT STATIC RAM
Features:
◆
◆
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed clock to data access
– Commercial:9/12/15ns(max.)
– Industrial: 12ns (max.)
Dual chip enables allow for depth expansion without
additional logic
Full synchronous operation on both ports
– 4ns setup to clock and 1ns hold on all control, data,
and address inputs
◆
◆
◆
Low-power operation
– Data input, address, and control registers
– IDT709089/79S
– Fast 9ns clock to data out in the Pipelined output mode
– Self-timed write allows fast cycle time
Active: 950mW (typ.)
Standby: 5mW (typ.)
– IDT709089/79L
– 15ns cycle time, 66.7MHz operation in the Pipelined
output mode
TTL- compatible, single 5V (±10%) power supply
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
◆
◆
Active: 950mW (typ.)
Standby: 1mW (typ.)
Flow-Through or Pipelined output mode on either port via
the FT/PIPE pin
Counter enable and reset features
◆
◆
◆
◆
Available in 100-pin Thin Quad Flatpack (TQFP) package
Green parts available, see ordering information
Functional Block Diagram
R/W
OE
R
R/W
L
OE
L
R
CE0R
CE1R
CE0L
CE1L
1
0
1
0
0/1
0/1
1
0
0
1
FT/PIPE
L
0/1
0/1
FT/PIPE
R
I/O0L - I/O7L
I/O0R - I/O7R
I/O
Control
I/O
Control
(1)
(1)
A
15L
A
A
15R
Counter/
Address
Reg.
Counter/
Address
Reg.
C0LRK
R
MEMORY
ARRAY
A
0L
CLK
L
ADS
R
ADS
L
CNTEN
R
CNTEN
L
CNTRST
R
CNTRST
L
.
3242 drw 01
NOTE:
1. A15X is a NC for IDT709079.
FEBRUARY 2016
1
DSC-3242/16
©2016 Integrated Device Technology, Inc.
IDT709089/79S/L
High-Speed 64/32K x 8 Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Description:
Withaninputdataregister,theIDT709089/79hasbeenoptimizedfor
applications having unidirectional or bidirectional data flow in bursts.
An automatic power down feature, controlled by CE0 and CE1, permits
the on-chip circuitry of each port to enter a very low standby power
mode. Fabricated using CMOS high-performance technology, these
devicestypicallyoperateononly950mWofpower.
TheIDT709089/79isahigh-speed64/32Kx8bitsynchronous Dual-
Port RAM. The memory array utilizes Dual-Port memory cells to allow
simultaneousaccessofanyaddressfrombothports.Registersoncontrol,
data,andaddressinputsprovideminimalsetupandholdtimes.Thetiming
latitudeprovidedbythisapproachallowssystemstobedesignedwithvery
shortcycletimes.
Pin Configuration(1,2,3)
NC
NC
76
77
50
49
NC
NC
NC
I/O7R
I/O6R
I/O5R
I/O4R
I/O3R
A6R
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
48
47
46
45
44
43
42
41
40
39
38
37
36
A5R
A4R
A3R
A2R
A1R
A0R
VCC
CNTEN
R
I/O2R
I/O1R
I/O0R
GND
CLKR
ADSR
(5)
709089/79
PN100
GND
ADS
L
VCC
CLK
L
I/O0L
I/O1L
GND
I/O2L
I/O3L
I/O4L
I/O5L
I/O6L
I/O7L
NC
CNTEN
L
35
34
A0L
A1L
33
32
31
30
29
28
27
26
A
A
2L
3L
A
4L
5L
6L
A
A
NC
NC
GND
3242 drw 02
Index
NOTES:
1. A15X is a NC for IDT709079.
2. All VCC pins must be connected to power supply.
3. All GND pins must be connected to ground supply.
4. Package body is approximately 14mm x 14mm x 1.4mm.
5. This package code is used to reference the package diagram.
6.42
2
IDT709089/79S/L
High-Speed 64/32K x 8 Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
PinNames
Left Port
Right Port
CE0R, CE1R
R/W
OE
Names
Chip Enables
CE0L, CE1L
R/W
OE
L
R
Read/Write Enable
Output Enable
Address
L
R
(1)
(1)
A
0L - A15L
A0R - A15R
I/O0L - I/O7L
CLK
I/O0R - I/O7R
CLK
Data Input/Output
Clock
L
R
Address Strobe
Counter Enable
Counter Reset
Flow-Through/Pipeline
Power
ADS
CNTEN
CNTRST
FT/PIPE
L
ADS
CNTEN
CNTRST
FT/PIPE
R
L
R
NOTE:
1. A15X is a NC for IDT709079.
L
R
L
R
V
CC
GND
Ground
3242 tbl 01
Truth Table I—
Read/Write and Enable Control(1,2,3)
CLK
CE
1
R/W
I/O0-7
Mode
OE
CE0
X
H
X
L
X
X
High-Z Deselected
High-Z Deselected
↑
X
L
X
↑
X
H
H
H
L
D
IN
Write
Read
↑
L
L
H
DOUT
↑
H
X
L
X
High-Z Outputs Disabled
3242 tbl 02
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. ADS, CNTEN, CNTRST = X.
3. OE is an asynchronous input signal.
Truth Table II—Address Counter Control(1,2)
Previous Internal
External
Address
Internal
Address
Address
Used
MODE
CLK
↑
I/O(3)
ADS CNTEN CNTRST
An
X
X
An
An
L(4)
H
X
H
H
DI/O (n)
External Address Used
An + 1
An + 1
L(5)
H
D
I/O(n+1) Counter Enabled—Internal Address generation
↑
↑
X
An + 1
X
H
H
D
I/O(n+1) External Address Blocked—Counter disabled (An + 1 reused)
X
A
0
X
X
L(4)
DI/O(0)
Counter Reset to Address 0
↑
5640 tbl 03
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. CE0 and OE = VIL; CE1 and R/W = VIH.
3. Outputs configured in Flow-Through Output mode; if outputs are in Pipelined mode the data out will be delayed by one cycle.
4. ADS is independent of all other signals including CE0 and CE1.
5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other signals including CE0 and CE1.
6.342
IDT709089/79S/L
High-Speed 64/32K x 8 Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Recommended Operating
Recommended DC Operating
Temperature and Supply Voltage(1) Conditions
Symbol
Parameter
Min.
4.5
Typ.
Max. Unit
Grade
Ambient
Temperature
GND
VCC
V
CC
Supply Voltage
5.0
5.5
0
V
V
V
Commercial
0OC to +70OC
0V
0V
5.0V
5.0V
+
+
10%
GND
Ground
0
0
Industrial
-40OC to +85OC
10%
____
V
IH
IL
Input High Voltage
Input Low Voltage
2.2
6.0(1)
0.8
3242 tbl 04
____
NOTES:
V
-0.5(2)
V
1. This is the parameter TA. This is the "instant on" case temperature.
3242 tbl 05
NOTES:
1. VTERM must not exceed VCC + 10%.
2. VIL > -1.5V for pulse width less than 10ns.
Absolute Maximum Ratings(1)
Capacitance(1)
(TA = +25°C, f = 1.0MHz)
Symbol
Rating
Commercial
& Industrial
Unit
Symbol
Parameter
Input Capacitance
Output Capacitance
Conditions(2)
IN = 3dV
OUT = 3dV
Max. Unit
(2)
V
TERM
Terminal Voltage
with Respect to GND
-0.5 to +7.0
V
CIN
V
9
pF
(3)
OUT
C
V
10
pF
T
BIAS
STG
JN
OUT
Temperature Under Bias
Storage Temperature
Junction Temperature
DC Output Current
-55 to +125
-65 to +150
+150
oC
oC
oC
3242 tbl 07
NOTES:
T
1. These parameters are determined by device characterization, but are not
production tested.
2. 3dV references the interpolated capacitance when the input and output
switch from 0V to 3V or from 3V to 0V.
T
I
50
mA
3. COUT also references CI/O.
3242 tbl 06
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VTERM must not exceed VCC+ 10% for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of VTERM > VCC + 10%.
3. Ambient Temperature Under DC Bias. No AC Conditions. Chip Deselected.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VCC = 5.0V ± 10%)
709089/79S/L
Min. Max.
Symbol
|ILI
Parameter
Input Leakage Current(1)
Test Conditions
CC = 5.5V, VIN = 0V to VCC
CE
OL = +4mA
OH = -4mA
Unit
µA
µA
V
___
___
___
|
V
10
10
|ILO
|
Output Leakage Current
Output Low Voltage
Output High Voltage
0
= VIH or CE1 = VIL, VOUT = 0V to VCC
V
OL
OH
I
0.4
___
V
I
2.4
V
3242 tbl 08
NOTE:
1. At VCC < 2.0V input leakages are undefined.
6.42
4
IDT709089/79S/L
High-Speed 64/32K x 8 Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(6) (VCC = 5V ± 10%)
709089/79X9
Com'l Only
709089/79X12
709089/79X15
Com'l Only
Com'l
& Ind
Typ.(4)
Typ.(4)
Symbol
Parameter
Test Condition
= VIL
Version
COM'L
Max.
Max.
Typ.(4)
Max.
Unit
ICC
Dynamic Operating
Current
(Both Ports Active)
S
L
210
210
390
350
200
200
345
305
190
190
325
285
mA
CE
L
and CE
R
Outputs Disabled
(1)
f = fMAX
____
____
____
____
____
____
____
____
IND
S
L
200
200
380
340
I
SB1
Standby Current
(Both Ports - TTL
Level Inputs)
COM'L
IND
S
L
50
50
135
115
50
50
110
90
50
50
110
90
mA
mA
CE
L
= CER = VIH
(1)
f = fMAX
____
____
____
____
____
____
____
____
S
L
50
50
125
105
ISB2
Standby Current
(One Port - TTL
Level Inputs)
COM'L
IND
S
L
140
140
270
240
130
130
230
200
120
120
220
190
CE"A" = VIL and
(3)
CE"B" = VIH
Active Port Outputs
____
____
____
____
____
____
____
____
(1)
S
L
130
130
245
215
Disabled, f=fMAX
ISB3
Full Standby Current
(Both Ports -
CMOS Level Inputs)
Both Ports CE
R
and
COM'L
IND
S
L
1.0
0.2
15
5
1.0
0.2
15
5
1.0
0.2
15
5
mA
CE
L
> VCC - 0.2V
V
V
IN > VCC - 0.2V or
____
____
____
____
____
____
____
____
IN < 0.2V, f = 0(2)
S
L
1.0
0.2
15
5
ISB4
Full Standby Current
(One Port -
CMOS Level Inputs)
mA
COM'L
S
L
130
130
245
225
120
120
205
185
110
110
195
175
CE"A" < 0.2V and
CE"B" > VCC - 0.2V(5)
V
V
IN > VCC - 0.2V or
IN < 0.2V, Active Port Outputs
____
____
____
____
____
____
____
____
IND
S
L
120
120
220
200
(1)
Disabled, f = fMAX
3242 tbl 09
NOTES:
1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS" at input levels of
GND to 3V.
2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. VCC = 5V, TA = 25°C for Typ, and are not production tested. ICC DC(f=0) = 150mA (Typ).
5. CEX = VIL means CE0X = VIL and CE1X = VIH
CEX = VIH means CE0X = VIH or CE1X = VIL
CEX < 0.2V means CE0X < 0.2V and CE1X > VCC - 0.2V
CEX > VCC - 0.2V means CE0X > VCC - 0.2V or CE1X < 0.2V
"X" represents "L" for left port or "R" for right port.
6. 'X' in part numbers indicate power (S or L).
6.542
IDT709089/79S/L
High-Speed 64/32K x 8 Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Test Conditions
Input Pulse Levels
GND to 3.0V
3ns Max.
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
1.5V
1.5V
Figures 1,2 and 3
3242 tbl 10
5V
5V
893Ω
893Ω
DATAOUT
DATAOUT
30pF
347Ω
5pF*
347Ω
3242 drw 04
3242 drw 05
Figure 1. AC Output Test load.
Figure 2. Output Test Load
(For tCKLZ, tCKHZ, tOLZ, and tOHZ).
*Including scope and jig.
8
10 pF is the I/O capacitance
of this device, and 30pF is the
AC Test Load Capacitance
7
6
5
4
3
tCD
tCD
(Typical, ns)
1
,
2
2
1
0
20 40 60 80 100 120 140 160 180 200
Capacitance (pF)
,
-1
3242 drw
06
Figure 3. Typical Output Derating (Lumped Capacitive Load).
6.42
6
IDT709089/79S/L
High-Speed 64/32K x 8 Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating Temperature Range
(Read and Write Cycle Timing)(3,4) (VCC = 5V ± 10%)
709089/79X9
Com'l Only
709089/79X12
Com'l
709089/79X15
Com'l Only
& Ind
Symbol
Parameter
Clock Cycle Time (Flow-Through)(2)
Min.
25
15
12
12
6
Max.
Min.
30
20
12
12
8
Max.
Min.
35
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
____
____
____
____
____
____
____
____
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
CYC1
Clock Cycle Time (Pipelined)(2)
Clock High Time (Flow-Through)(2)
Clock Low Time (Flow-Through)(2)
Clock High Time (Pipelined)(2)
Clock Low Time (Pipelined)(2)
Clock Rise Time
25
____
____
____
____
____
____
____
____
____
____
CYC2
CH1
CL1
CH2
CL2
R
12
12
10
6
8
10
____
____
____
3
3
3
____
____
____
F
Clock Fall Time
3
3
3
____
____
____
SA
Address Setup Time
4
1
4
1
4
1
4
1
4
1
4
1
4
4
1
4
1
4
1
4
1
4
1
4
1
4
4
1
4
1
4
1
4
1
4
1
4
1
4
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
HA
Address Hold Time
SC
Chip Enable Setup Time
Chip Enable Hold Time
R/W Setup Time
HC
SW
HW
SD
R/W Hold Time
Input Data Setup Time
Input Data Hold Time
HD
SAD
HAD
ADS Setup Time
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
ADS Hold Time
SCN
HCN
SRST
CNTEN Setup Time
CNTEN Hold Time
CNTRST Setup Time
HRST
OE
1
1
1
CNTRST Hold Time
____
____
____
Output Enable to Data Valid
Output Enable to Output Low-Z(1)
Output Enable to Output High-Z(1)
Clock to Data Valid (Flow-Through)(2)
Clock to Data Valid (Pipelined)(2)
Data Output Hold After Clock High
Clock High to Output High-Z(1)
Clock High to Output Low-Z(1)
9
12
15
____
____
____
OLZ
OHZ
CD1
CD2
DC
2
2
2
1
7
1
7
1
7
____
____
____
20
25
30
____
____
____
9
12
15
____
____
____
2
2
2
2
2
2
2
2
2
CKHZ
CKLZ
9
9
9
____
____
____
Port-to-Port Delay
____
____
____
____
____
____
t
t
CWDD
CCS
Write Port Clock High to Read Data Delay
Clock-to-Clock Setup Time
35
15
40
15
50
20
ns
ns
3242 tbl 11
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). This parameter is guaranteed by device
characterization, but is not production tested.
2. The Pipelined output parameters (tCYC2, tCD2) apply to either or both left and right ports when FT/PIPE = VIH. Flow-through parameters (tCYC1, tCD1) apply when
FT/PIPE = VIL for that port.
3. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE) and FT/PIPE. FT/PIPE should be treated as a DC
signal, i.e. steady state during operation.
4. 'X' in part number indicates power rating (S or L).
6.742
IDT709089/79S/L
High-Speed 64/32K x 8 Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Read Cycle for
Flow-Through Output (FT/PIPE"X" = VIL)(3,6)
tCYC1
tCH1
t
CL1
CLK
CE
0
tSC
tHC
tSC
tHC
CE
1
R/W
tHW
tSW
tSA
tHA
ADDRESS(5)
An
An + 1
An + 2
An + 3
(1)
t
DC
tCD1
tCKHZ
Qn
Qn + 1
Qn + 2
DATAOUT
(1)
(1)
tCKLZ
tDC
(1)
tOHZ
tOLZ
,
OE(2)
tOE
3242 drw 07
Timing Waveform of Read Cycle for Pipelined Output
(FT/PIPE"X" = VIH)(3,6)
tCYC2
t
CH2
t
CL2
CLK
CE
0
t
SC
(4)
tHC
tSC
tHC
CE1
R/W
t
HW
tSW
t
SA
tHA
ADDRESS(5)
DATAOUT
An
An + 1
An + 2
Qn
An + 3
(1 Latency)
t
DC
t
CD2
Qn + 1
Qn + 2
(1)
tCKLZ
(1)
(1)
t
OHZ
t
OLZ
(2)
OE
tOE
NOTES:
3242 drw 08
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.
3. ADS = VIL and CNTRST = VIH.
4. The output is disabled (High-Impedance state) by CE0 = VIH or CE1 = VIL following the next rising edge of clock. Refer to Truth Table 1.
5. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use
only.
6. "X" denotes Left or Right port. The diagram is with respect to that port.
6.42
8
IDT709089/79S/L
High-Speed 64/32K x 8 Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of a Bank Select Pipelined Read(1,2)
t
CYC2
tCH2
tCL2
CLK
ADDRESS(B1)
CE0(B1)
t
SA
tHA
A6
A5
A4
A3
A
2
A
0
A1
tSC
tHC
t
SC
tHC
(3)
tCD2
tCD2
tCKHZ
tCD2
Q
0
Q3
Q
1
DATAOUT(B1)
ADDRESS(B2)
(3)
(3)
tDC
tCKLZ
t
DC
tCKHZ
tSA
tHA
A6
A5
A4
A3
A2
A
0
A1
tSC
tHC
CE0(B2)
tSC
tHC
(3)
tCD2
tCKHZ
tCD2
DATAOUT(B2)
Q4
Q2
(3)
(3)
tCKLZ
tCKLZ
3242 drw 09
Timing Waveform of a Bank Select Flow-Through Read(6,7)
t
CYC1
tCH1
tCL1
CLK
tSA
tHA
A6
A5
A4
A3
A2
A0
A1
ADDRESS(B1)
tSC
tHC
CE0(B1)
t
SC
tHC
(1)
tCD1
tCD1
tCKHZ
tCD1
tCD1
D
0
D
3
D5
D
1
DATAOUT(B1)
ADDRESS(B2)
(1)
(1)
(1)
tDC
tCKLZ
tCKLZ
tDC
tCKHZ
tSA
tHA
A6
A
5
A4
A3
A2
A
0
A1
t
SC
tHC
CE0(B2)
tSC
tHC
(1)
(1)
tCD1
tCKHZ
tCD1
tCKHZ
D4
DATAOUT(B2)
D2
(1)
(1)
tCKLZ
tCKLZ
3242 drw 09a
NOTES:
1. B1 Represents Bank #1; B2 Represents Bank #2. Each Bank consists of one IDT709089/79 for this waveform, and are setup for depth expansion in this
example. ADDRESS(B1) = ADDRESS(B2) in this situation.
2. OE and ADS = VIL; CE1(B1), CE1(B2), R/W and CNTRST = VIH.
3. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
4. CE0 and ADS = VIL; CE1 and CNTRST = VIH.
5. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to.
6. If tCCS < maximum specified, then data from right port READ is not valid until the maximum specified for tCWDD.
If tCCS > maximum specified, then data from right port READ is not valid until tCCS + tCD1. tCWDD does not apply in this case.
7. All timing is the same for both Left and Right ports. Port "A" may be either Left or Right port. Port "B" is the opposite of Port "A".
6.942
IDT709089/79S/L
High-Speed 64/32K x 8 Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform with Port-to-Port Flow-Through Read(1,2,3,5)
CLK "A"
tSW
tHW
R/W"A"
ADDRESS"A"
DATAIN"A"
CLK"B"
t
SA
MATCH
SD HD
VALID
tHA
NO
MATCH
t
t
(4)
tCCS
tCD1
R/W"B"
tHW
tSW
tHA
tSA
NO
MATCH
ADDRESS"B"
DATAOUT"B"
MATCH
(4)
tCD1
tCWDD
VALID
VALID
tDC
tDC
3242 drw 10
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. CE0 and ADS = VIL; CE1 and CNTRST = VIH.
3. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to.
4. If tCCS < maximum specified, then data from right port READ is not valid until the maximum specified for tCWDD.
If tCCS > maximum specified, then data from right port READ is not valid until tCCS + tCD1. tCWDD does not apply in this case.
5. All timing is the same for both Left and Right ports. Port "A" may be either Left or Right port. Port "B" is the opposite of Port "A".
6.42
10
IDT709089/79S/L
High-Speed 64/32K x 8 Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Pipelined Read-to-Write-to-Read (OE = VIL)(3)
tCYC2
tCH2
tCL2
CLK
CE0
tSC
tHC
CE1
tSW tHW
R/W
tSW tHW
(4)
An + 3
An + 4
An
An +1
An + 2
An + 2
ADDRESS
t
SA
tHA
t
SD
tHD
DATAIN
Dn + 2
(1)
tCD2
(1)
tCD2
(2)
tCKHZ
tCKLZ
Qn + 3
Qn
DATAOUT
READ
NOP(5)
WRITE
READ
3242 drw 11
Timing Waveform of Pipelined Read-to-Write-to-Read (OE Controlled)(3)
tCYC2
tCH2
tCL2
CLK
CE0
tSC
tHC
CE1
tSW tHW
R/W
tSW tHW
(4)
An + 4
An
An +1
An + 2
An + 3
Dn + 3
An + 5
ADDRESS
t
SA
tHA
t
SD
tHD
DATAIN
Dn + 2
(1)
tCKLZ
tCD2
tCD2
(2)
Qn
Qn + 4
DATAOUT
(1)
tOHZ
OE
READ
WRITE
READ
3242 drw 12
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
3. CE0 and ADS = VIL; CE1 and CNTRST = VIH.
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only.
5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
61.412
IDT709089/79S/L
High-Speed 64/32K x 8 Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform Flow-Through Read-to-Write-to-Read (OE = VIL)(3)
t
CYC1
tCH1
tCL1
CLK
CE0
tSC
tHC
CE1
tSW tHW
R/W
t
SW tHW
(4)
An + 4
An
An + 3
An +1
An + 2
An + 2
ADDRESS
tSA
tHA
tSD tHD
DATAIN
Dn + 2
tCD1
tCD1
tCD1
tCD1
(2)
Qn + 3
Qn
READ
Qn + 1
DATAOUT
(1)
CKLZ
(1)
tDC
tDC
t
t
CKHZ
NOP(5)
WRITE
READ
3242 drw 13
TimingWaveformof Flow-ThroughRead-to-Write-to-Read(OEControlled)(3)
tCYC1
tCH1
tCL1
CLK
CE0
tSC
tHC
CE1
tSW tHW
R/W
tSW tHW
(4)
An + 5
An
An +1
An + 2
An + 3
Dn + 3
An + 4
ADDRESS
tSA
tHA
t
SD tHD
DATAIN
Dn + 2
tOE
tDC
tCD1
tCD1
tCD1
(2)
Qn + 4
Qn
DATAOUT
OE
(1)
CKLZ
(1)
t
tOHZ
tDC
READ
WRITE
READ
3242 drw 14
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. Output state (High, Low, or High-impedance is determined by the previous cycle control signals.
3. CE0 and ADS = VIL; CE1 and CNTRST = VIH.
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only.
5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
6.42
12
IDT709089/79S/L
High-Speed 64/32K x 8 Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Pipelined Read with Address Counter Advance(1)
t
CYC2
tCH2
tCL2
CLK
t
SA
tHA
An
ADDRESS
tSAD tHAD
ADS
t
SAD tHAD
CNTEN
tSCN tHCN
tCD2
Qx - 1(2)
Qn + 3
Qn + 1
Qn + 2(2)
Qn
Qx
DATAOUT
tDC
READ
EXTERNAL
ADDRESS
READ
WITH
COUNTER
COUNTER
HOLD
READ WITH COUNTER
3242 drw 15
TimingWaveformof Flow-ThroughReadwithAddressCounterAdvance(1)
tCYC1
tCH1
tCL1
CLK
tSA
tHA
An
ADDRESS
tSAD tHAD
ADS
tSAD
tHAD
tSCN
tHCN
CNTEN
tCD1
Qn + 3(2)
Qx(2)
Qn + 4
Qn + 1
Qn + 2
Qn
DATAOUT
tDC
READ
WITH
READ
EXTERNAL
ADDRESS
READ WITH COUNTER
COUNTER
HOLD
COUNTER
3242 drw 16
NOTES:
1. CE0 and OE = VIL; CE1, R/W, and CNTRST = VIH.
2. If there is no address change via ADS = VIL (loading a new address) or CNTEN = VIL (advancing the address), i.e. ADS = VIH and CNTEN = VIH, then the data output
remains constant for subsequent clocks.
61.432
IDT709089/79S/L
High-Speed 64/32K x 8 Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Address Counter Advance
(Flow-Through or Pipelined Outputs)(1)
t
CYC2
tCH2
tCL2
CLK
tSA
tHA
An
ADDRESS
INTERNAL(3)
ADDRESS
An(7)
An + 1
An + 3
An + 4
An + 2
t
SAD tHAD
ADS
CNTEN
t
SD tHD
Dn + 4
Dn + 1
Dn + 3
Dn
Dn + 1
Dn + 2
DATAIN
WRITE
EXTERNAL
ADDRESS
WRITE
WITH COUNTER
WRITE
COUNTER HOLD
WRITE WITH COUNTER
3242 drw 17
Timing Waveform of Counter Reset (Pipelined Outputs)(2)
t
CYC2
tCH2
tCL2
CLK
t
SA tHA
(4)
An + 2
An
An + 1
ADDRESS
INTERNAL(3)
ADDRESS
Ax(6)
0
An + 1
1
An
t
SW tHW
R/W
ADS
t
t
SAD
SCN
tHAD
CNTEN
tHCN
tSRST
tHRST
CNTRST
t
SD
tHD
D0
DATAIN
(5)
Qn
Q1
Q0
DATAOUT
COUNTER(6)
RESET
WRITE
ADDRESS 0
READ
ADDRESS 0
READ
READ
READ
ADDRESS 1
ADDRESS n ADDRESS n+1
3242 drw 18
NOTES:
1. CE0 and R/W = VIL; CE1 and CNTRST = VIH.
CE0 = VIL; CE1 = VIH.
2.
3. The "Internal Address" is equal to the "External Address" when ADS = VIL and equals the counter output when ADS = VIH.
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only.
5. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
6. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset. ADDR0 will be accessed. Extra cycles are shown here
simply for clarification.
7. CNTEN = VIL advances Internal Address from ‘An’ to ‘An +1’. The transition shown indicates the time required for the counter to advance. The ‘An +1’Address is written
to during this cycle.
6.42
14
IDT709089/79S/L
High-Speed 64/32K x 8 Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Depth and Width Expansion
FunctionalDescription
The IDT709089/79 features dual chip enables (refer to Truth Table
I)inordertofacilitaterapidandsimpledepthexpansionwithnorequire-
mentsforexternallogic.Figure4illustrateshowtocontrolthevariouschip
enables in order to expand two devices in depth.
The IDT709089/79 provides a true synchronous Dual-Port Static
RAM interface. Registered inputs provide minimal set-up and hold
times on address, data, and all critical control inputs. All internal
registers are clocked on the rising edge of the clock signal, however,
the self-timed internal write pulse is independent of the LOW to HIGH
transition of the clock signal.
The IDT709089/79 can also be used in applications requiring ex-
pandedwidth,asindicatedinFigure4.Sincethebanksareallocatedat
thediscretionoftheuser,theexternalcontrollercanbesetuptodrivethe
input signals for the various devices as required to allow for 16-bit or
wider applications.
An asynchronous output enable is provided to ease asynchronous
bus interfacing. Counter enable inputs are also provided to stall the
operation of the address counters for fast interleaved memory appli-
cations.
A HIGH on CE0 or a LOW on CE1 for one clock cycle will power
down the internal circuitry to reduce static power consumption.
MultiplechipenablesalloweasierbankingofmultipleIDT709089/79'sfor
depth expansion configurations. When the Pipelined output mode is
enabled, two cycles are required with CE0 LOW and CE1 HIGH to re-
activate the outputs.
(1)
A
15/A14
IDT709089/79
IDT709089/79
CE0
CE0
VCC
V
CC
CE1
CE1
Control Inputs
Control Inputs
IDT709089/79
IDT709089/79
CE1
CE1
CE0
CE0
CNTRST
CLK
Control Inputs
Control Inputs
,
ADS
CNTEN
R/W
3242 drw 19
OE
Figure 4. Depth and Width Expansion with IDT709089/79
NOTE:
1. A15 is for IDT709089, A14 is for IDT709079.
61.452
IDT709089/79S/L
High-Speed 64/32K x 8 Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Ordering Information
A
A
XXXXX
99
A
A
A
Device
Type
Power Speed Package
Process/
Temperature
Range
Tube or Tray
Tape and Reel
Blank
8
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
Blank
)
I(1
)
G(2
Green
PF
100-pin TQFP (PN100)
9
12
15
Commercial Only
Commercial & Industrial
Commercial Only
Speed in nanoseconds
S
L
Standard Power
Low Power
709089
709079
512K (64K x 8-Bit) Synchronous Dual-Port RAM
256K (32K x 8-Bit) Synchronous Dual-Port RAM
3242 drw 20
NOTE:
1. Contact your local sales office for industrial temp range for other speeds, packages and powers.
2. Green parts available. For specific speeds, packages and powers contact your sales office.
Ordering Information for Flow-through Devices
Old Flow-through Part
New Combined Part
70908S/L20
709089S/L9
709089S/L12
709089S/L15
70908S/L25
70908S/L30
3242 tbl 12
DatasheetDocumentHistory
1/12/99:
Initiateddatasheetdocumenthistory
Convertedtonewformat
Cosmeticandtypographicalcorrections
Addedadditionalnotestopinconfigurations
AddedDepthandWidthExpansionnote
Changeddrawingformat
Page 15
Page 4
6/7/99:
Deletednote6forTableII
11/10/99:
ReplacedIDTlogo
6.42
16
IDT709089/79S/L
High-Speed 64/32K x 8 Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
DatasheetDocumentHistory(con't)
12/22/99:
1/12/00:
Page 1
Removed"Separateupper-byte..."line
CombinedPipelined709089familyandFlow-through70908familyofferingsintoonedatasheet
Changed±200mVinwaveformnotesto0mV
Addedcorrespondingpartchartwithorderinginformation
Changed±220mVwaveformnotesto0mV
Changed "Operation" in heading to "Pipelined Output", fixed drawing 08
RemovedPGApackage
Changed information in Truth Table II
Increasedstoragetemperatureparameters
2/18/00:
5/24/00:
Pages 8 & 9
Page 9
Page 3
Page 4
ClarifiedTA parameter
Page 5
DCElectricalparameters–changedwordingfrom"open"to"disabled"
AddedIndustrialTemperatureRangesandremovedrelatednotes
Addeddaterevisionforpinconfiguration
01/10/02:
06/21/04:
Page 2
Page 5 & 7
Page 16
Page 1 & 17
Removedindustrialtempfromcolumnheadingsandvaluesfor15nsfromAC&DCElectricalCharacteristics
Removedindustrialofferingfrom15nsorderinginfoandaddedindustrialtempfootnote
Replaced IDT TM logo with ® logo
Consolidatedmultipledevicesintoonedatasheet
RemovedPreliminarystatusfromdatasheet
Page 4
AddedJunctionTemperaturetoAbsoluteMaximumRatingsTable
AddedAmbientTemperaturefootnote
Page 5
Page 8
Page 17
Added6ns&7nsspeedDCtimingnumberstotheDCElectricalCharacteristicsTable
Added6ns&7nsspeedACtimingnumberstotheACElectricalCharacteristicsTable
Added 6ns & 7ns speed grades to ordering information
Added IDT Clock Solution Table
Page 1 & 18
Page 17
Page 1
Replaced old logo with new TM logo
Removed "IDT" from orderable part number
Addedgreenpartsavailabilitytofeatures
01/29/09:
07/26/10:
Page 17
Page 8
Addedgreenindicatortoorderinginformation
InordertocorrecttheheadernotesoftheACElectCharsTableandalignthemwiththeIndustrialtemprange
values located in the table, the commercial TA header note has been removed
Inordertocorrectthefootnotesoftimingdiagrams,CNTEN hasbeenremovedtoreconcilethefootnoteswith
the CNTEN logicdefinitionfoundinTruthTableII-AddressCounterControl
UpdatedspeedofferingsandcycletimeinFeatures
Pages 9-13
05/28/15:
Page 1
Page 2
RemovedIDTinreferencetofabrication
Page 2
Removeddateforthe100-PINTQFPconfiguration
Page 2 & 16
Page 5
The package code PN100-1 changed to PN100 to match standard package codes
Removed X6 and X7 speed grades from the DC Elec Chars table and combined X9, X12 & X15 speed
grades into one DC Elec Chars table
Page 6
Page 7
Page 16
CorrectedtypointheTypicalOutputDeratingdrawing
Removed X6 and X7 speed grades from the AC Elec Chars table
Added Tape and Reel indicator to, removed X6 & X7 speed grades and updated the commercial and
industrialofferingsinOrderingInformation
Page 16
Page 2
RemovedtheIDTClockSolutiontable
02/22/16:
ChangeddiagramforthePN100pinconfigurationbyrotatingthepin1orientationcounterclockwiseby
90degreesforaccuraterepresentationofthepartandaddedtheblackdotasthepin1indicator
Added the IDT logo to the pin configuration and changed the text to be in alignment with new diagram
markingspecsandrotatedthepinnamesontheverticalsidestoanuprightposition
UpdatedfootnotereferencesforthePN100pinconfiguration
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
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for SALES:
for Tech Support:
408-284-2794
DualPortHelp@idt.com
800-345-7015 or 408-284-8200
fax: 408-284-2775
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
61.472
相关型号：
709099L12PFG8
Dual-Port SRAM, 128KX8, 25ns, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, GREEN, TQFP-100
IDT
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