709099L12PFGI8 [IDT]
Dual-Port SRAM;
| 型号： | 709099L12PFGI8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Dual-Port SRAM 静态存储器 内存集成电路 |
| 文件： | 总16页 (文件大小：679K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HIGH-SPEED 128K x 8
IDT709099L
SYNCHRONOUS PIPELINED
DUAL-PORT STATIC RAM
Features
◆
◆
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed clock to data access
– Commercial: 9/12ns (max.)
Full synchronous operation on both ports
– 4ns setup to clock and 0ns hold on all control, data, and
address inputs
◆
– Data input, address, and control registers
– Fast 9ns clock to data out in the Pipelined output mode
– Self-timed write allows fast cycle time
– Industrial: 9ns (max.)
◆
Low-power operation
– IDT709099L
– 15ns cycle time, 66.7MHz operation in Pipelined output mode
TTL- compatible, single 5V (±10%) power supply
Industrial temperature range (–40°C to +85°C) is
available for selected speeds
◆
◆
Active: 1.2W (typ.)
Standby: 2.5mW (typ.)
◆
Flow-Through or Pipelined output mode on either Port via
the FT/PIPE pins
◆
◆
Available in a 100-pin Thin Quad Flatpack (TQFP) package
Green parts available, see ordering information
◆
◆
Counter enable and reset features
Dual chip enables allow for depth expansion without
additional logic
Functional Block Diagram
R/WR
R/W
L
OEL
OER
CE
CE10LL
CE0R
CE1R
1
0
1
0
0/1
0/1
1
0
1
0
0/1
0/1
FT/PIPE
L
FT/PIPE
R
I/O0L - I/O7L
I/O0R - I/O7R
I/O
Control
I/O
Control
A
16L
A
16R
Counter/
Address
Reg.
Counter/
Address
Reg.
MEMORY
ARRAY
A
C0LRK
R
R
A
0L
L
L
CLK
ADS
ADS
CNTEN
R
CNTEN
L
CNTRST
R
CNTRST
L
4846 drw 01
APRIL 2015
1
DSC-4846/8
©2015 Integrated Device Technology, Inc.
IDT709099L
High-Speed 128K x 8 Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Description
With an input data register, the IDT709099 has been optimized for
applications having unidirectional or bidirectional data flow in bursts.
An automatic power down feature, controlled by CE0 and CE1, permits
the on-chip circuitry of each port to enter a very low standby power
mode. Fabricated using CMOS high-performance technology, these
devicestypicallyoperateononly1.2Wofpower.
The IDT709099 is a high-speed 128K x 8 bit synchronous Dual-
Port RAM. The memory array utilizes Dual-Port memory cells to allow
simultaneous access of any address from both ports. Registers on
control, data, and address inputs provide minimal setup and hold
times. The timing latitude provided by this approach allows systems
to be designed with very short cycle times.
Pin Configurations(1,2,3)
Index
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1
NC
NC
NC
NC
75
2
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
3
A
A
A
A
A
A
A
A
A
A
GND
NC
NC
NC
NC
CE0R
CE1R
CNTRST
R/W
OE
FT/PIPE
GND
NC
7R
A
A
A
7L
8L
9L
4
8R
5
9R
6
10R
11R
12R
13R
14R
15R
16R
A
A
A
A
A
A
A
10L
11L
12L
13L
14L
15L
16L
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
IDT709099PF
(4)
PN100
VCC
100-PIN TQFP
(5)
TOP VIEW
NC
NC
NC
NC
CE0L
CE1L
.
R
CNTRST
L
L
L
L
R
R/W
OE
FT/PIPE
R
R
NC
NC
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
4846 drw 02
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground.
3. Package body is approximately 14mm x 14mm x 1.4mm
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
2
6.42
IDT709099L
High-Speed 128K x 8 Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Pin Names
Left Port
Right Port
CE0R, CE1R
R/W
OE
Names
Chip Enables
CE0L, CE1L
R/W
OE
L
R
Read/Write Enable
Output Enable
Address
L
R
A
0L - A16L
I/O0L - I/O7L
CLK
ADS
CNTEN
CNTRST
FT/PIPE
A
0R - A16R
I/O0R - I/O7R
CLK
ADS
CNTEN
CNTRST
FT/PIPE
Data Input/Output
Clock
L
R
Address Strobe
Counter Enable
Counter Reset
Flow-Through/Pipeline
Power
L
R
L
R
L
R
L
R
V
CC
GND
Ground
4846 tbl 01
Truth Table I—Read/Write and Enable Control(1,2,3)
CLK
↑
CE
X
1
R/W
X
I/O0-7
High-Z
High-Z
DATAIN
DATAOUT
High-Z
Mode
OE
CE0
X
H
X
L
Deselected—Power Down
Deselected—Power Down
Write
X
L
X
↑
X
H
H
H
L
↑
L
L
H
Read
↑
H
X
L
X
Outputs Disabled
4846 tbl 02
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. ADS, CNTEN, CNTRST = X.
3. OE is an asynchronous input signal.
Truth Table II—Address Counter Control(1,2,6)
Previous
Addr
Used
Mode
Address Address
CLK
↑
I/O(3)
ADS
CNTEN CNTRST
X
An
An
X
X
X
0
An
X
X
X
H
L
D
I/O(0)
I/O(n)
I/O(n)
Counter Reset to Address 0
External Address Utilized
L(4)
H
H
H
H
D
D
↑
Ap
Ap
Ap
External Address Blocked—Counter Disabled (Ap reused)
↑
Ap + 1
H
L(5)
DI/O(n+1)
Counter Enable—Internal Address Generation
↑
4846 tbl 03
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. CE0 and OE = VIL; CE1 and R/W = VIH.
3. Outputs configured in Flow-Through Output mode: if outputs are in Pipelined mode the data out will be delayed by one cycle.
4. ADS is independent of all other signals including CE0 and CE1.
5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other signals including CE0 and CE1.
6. While an external address is being loaded (ADS = VIL), R/W = VIH is recommended to ensure data is not written arbitrarily.
6.342
IDT709099L
High-Speed 128K x 8 Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Recommended Operating
Recommended DC Operating
Conditions
TemperatureandSupplyVoltage
Symbol
Parameter
Supply Voltage
Min.
4.5
Typ.
Max. Unit
Grade
Ambient
GND
Vcc
Temperature(2)
V
CC
5.0
5.5
V
V
V
Commercial
0OC to +70OC
-40OC to +85OC
0V
0V
5.0V
5.0V
+
+
10%
GND
Ground
0
0
0
Industrial
10%
____
V
IH
Input High Voltage
Input Low Voltage
2.2
-0.5(2)
6.0(1)
0.8
4846 tbl 04
____
NOTES:
V
IL
V
1. This is the parameter TA. This is the "instant on" case temperature.
4846 tbl 05
NOTES:
1. VTERM must not exceed Vcc + 10%.
2. VIL > -1.5V for pulse width less than 10ns.
Absolute Maximum Ratings(1)
Capacitance(1)
(TA = +25°C, f = 1.0MHz)
Symbol
Rating
Commercial
& Industrial
Unit
Symbol
Parameter
Input Capacitance
Output Capacitance
Conditions(2)
IN = 3dV
OUT = 3dV
Max. Unit
(2)
V
TERM
Terminal Voltage
with Respect
to GND
-0.5 to +7.0
V
CIN
V
9
pF
(3)
C
OUT
V
10
pF
Te m p e rature
Under Bias
-55 to +125
-65 to +150
50
oC
oC
4846 tbl 07
T
BIAS
NOTES:
1. These parameters are determined by device characterization, but are not
production tested.
TSTG
Storage
2. 3dV references the interpolated capacitance when the input and output switch from
0V to 3V or from 3V to 0V.
Te m p e rature
3. COUT also references CI/O.
IOUT
DC Output
Current
mA
4846 tbl 06
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VTERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of VTERM > Vcc + 10%.
DC Electrical Characteristics Over the Operating
Temperature Supply Voltage Range (VCC = 5.0V ± 10%)
709099L
Symbol
|ILI
|ILO
Parameter
Input Leakage Current(1)
Test Conditions
CC = 5.5V, VIN = 0V to VCC
CE = VIH or CE = VIL, VOUT = 0V to VCC
OL = +4mA
OH = -4mA
Min.
Max.
Unit
µA
µA
V
___
___
___
|
V
5
5
|
Output Leakage Current
Output Low Voltage
Output High Voltage
0
1
V
OL
I
0.4
___
V
OH
I
2.4
V
4846 tbl 08
NOTE:
1. At Vcc < 2.0V input leakages are undefined.
4
6.42
IDT709099L
High-Speed 128K x 8 Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(3) (VCC = 5V ± 10%)
709099L9
Com'l
709099L12
Com'l Only
& Ind
Symbol
Parameter
Test Condition
Version
COM'L
Typ.(4)
250
300
80
Max.
400
430
135
160
275
Typ.(4)
Max.
Unit
mA
ICC
Dynamic Operating
Current
L
L
L
L
L
L
230
355
CEL and CER= VIL
Outputs (D1)isabled
f = fMAX
____
____
(Both Ports Active)
IND
mA
mA
ISB1
Standby Current
(Both Ports - TTL
Level Inputs)
COM'L
IND
70
____
110
____
CE
L = CER = VIH
(1)
f = fMAX
95
ISB2
Standby Current
(One Port - TTL
Level Inputs)
COM'L
IND
175
150
240
CE"A" = VIL and
(3)
CE"B" = VIH
____
____
Active Port Outp(u1t)s
Disabled, f=fMAX
195
0.5
0.5
170
295
3.0
6.0
270
mA
mA
ISB3
Full Standby Current
(Both Ports -
Both Ports CE
R
and
COM'L
IND
L
L
0.5
____
3.0
____
CE
V
V
L
> VCC - 0.2V
CMOS Level Inputs)
IN > VCC - 0.2V or
IN < 0.2V, f = 0(2)
ISB4
Full Standby Current
(One Port -
COM'L
IND
L
L
140
225
CE"A" < 0.2V and
CE"B" > VCC - 0.2V(5)
____
____
CMOS Level Inputs)
V
V
IN > VCC - 0.2V or
190
290
IN < 0.2V, Active Port
(1)
Outputs Disabled, f = fMAX
4846 tbl 09
NOTES:
1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS" at input levels of
GND to 3V.
2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. Vcc = 5V, TA = 25°C for Typ, and are not production tested. ICC DC(f=0) = 150mA (Typ).
5. CEX = VIL means CE0X = VIL and CE1X = VIH
CEX = VIH means CE0X = VIH or CE1X = VIL
CEX < 0.2V means CE0X < 0.2V and CE1X > VCC - 0.2V
CEX > VCC - 0.2V means CE0X > VCC - 0.2V or CE1X < 0.2V
"X" represents "L" for left port or "R" for right port.
6.542
IDT709099L
High-Speed 128K x 8 Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Test Conditions
Input Pulse Levels
GND to 3.0V
3ns Max.
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
1.5V
1.5V
Figures 1,2 and 3
4846 tbl 10
5V
5V
893Ω
893Ω
DATAOUT
DATAOUT
30pF
347Ω
5pF*
347Ω
4846 drw 04
4846 drw 05
Figure 1. AC Output Test load.
Figure 2. Output Test Load
(For tCKLZ, tCKHZ, tOLZ, and tOHZ).
*Including scope and jig.
8
7
6
5
10pF is the I/O capacitance
of this device, and 30pF is the
AC Test Load Capacitance
tCD
tCD
(Typical, ns)
1
2
,
4
3
2
1
0
20 40 60 80 100 120 140 160 180 200
Capacitance (pF)
-1
4846 drw 06
Figure 3. Typical Output Derating (Lumped Capacitive Load).
6
6.42
IDT709099L
High-Speed 128K x 8 Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating Temperature Range
(Read and Write Cycle Timing)(3) (VCC = 5V ± 10%=)
709099L9
Com'l
709099L12
Com'l Only
& Ind
Symbol
Parameter
Min.
25
15
12
12
6
Max.
Min.
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
CYC1
Clock Cycle Time (Flow-Through)(2)
Clock Cycle Time (Pipelined)(2)
Clock High Time (Flow-Through)(2)
Clock Low Time (Flow-Through)(2)
Clock High Time (Pipelined)(2)
Clock Low Time (Pipelined)(2)
Clock Rise Time
30
20
12
12
8
____
____
____
____
____
____
____
____
____
____
____
____
t
CYC2
CH1
CL1
t
t
t
CH2
t
CL2
6
____
8
____
tR
3
3
____
____
tF
Clock Fall Time
3
____
3
____
t
SA
HA
SC
Address Setup Time
4
1
4
1
4
1
4
1
4
1
4
1
4
4
1
4
1
4
1
4
1
4
1
4
1
4
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
Address Hold Time
t
Chip Enable Setup Time
Chip Enable Hold Time
R/W Setup Time
t
HC
SW
HW
t
t
R/W Hold Time
tSD
Input Data Setup Time
tHD
Input Data Hold Time
t
SAD
HAD
SCN
HCN
SRST
HRST
ADS Setup Time
t
ADS Hold Time
t
CNTEN Setup Time
t
CNTEN Hold Time
t
CNTRST Setup Time
t
1
____
1
____
CNTRST Hold Time
t
OE
OLZ
OHZ
Output Enable to Data Valid
Output Enable to Output Low-Z(1)
Output Enable to Output High-Z(1)
Clock to Data Valid (Flow-Through)(2)
Clock to Data Valid (Pipelined)(2)
Data Output Hold After Clock High
Clock High to Output High-Z(1)
Clock High to Output Low-Z(1)
12
____
12
____
t
2
2
t
1
____
7
1
____
7
t
CD1
20
25
____
____
t
CD2
9
____
12
____
t
DC
CKHZ
CKLZ
2
2
2
2
2
2
t
9
____
9
____
t
Port-to-Port Delay
Write Port Clock High to Read Data Delay
Clock-to-Clock Setup Time
____
____
____
____
t
CWDD
35
15
40
15
ns
tCCS
ns
4846 tbl 11
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). This parameter is guaranteed by device
characterization, but is not production tested.
2. The Pipelined output parameters (tCYC2, tCD2) to either the Left or Right ports when FT/PIPE = VIH. Flow-Through parameters (tCYC1, tCD1) apply when FT/PIPE
= VIL for that port.
3. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE), FT/PIPER and FT/PIPEL.
6.742
IDT709099L
High-Speed 128K x 8 Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Read Cycle for
Flow-Through Output (FT/PIPE"X" = VIL)(3,6)
tCYC1
tCH1
tCL1
CLK
CE0
tSC
tHC
tSC
tHC
(4)
CE1
R/W
tHW
tSW
tSA
t
HA
ADDRESS(5)
DATAOUT
An
An + 1
An + 2
An + 3
(1)
tDC
tCD1
tCKHZ
Qn
Qn + 1
Qn + 2
(1)
(1)
tCKLZ
tDC
(1)
tOHZ
t
OLZ
OE(2)
tOE
4846 drw 07
Timing Waveform of Read Cycle for Pipelined Operation
(FT/PIPE"X" = VIH)(3,6)
tCYC2
tCH2
tCL2
CLK
CE
0
tSC
tHC
tSC
tHC
(4)
CE1
tSB
tHB
R/W
tHW
tSW
tSA
tHA
ADDRESS(5)
An
An + 1
An + 2
Qn
An + 3
(1 Latency)
tDC
tCD2
Qn + 2 (6)
DATAOUT
Qn + 1
(1)
tCKLZ
(1)
(1)
t
OHZ
tOLZ
OE(2)
tOE
4846 drw 08
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.
3. ADS = VIL and CNTRST = VIH.
4. The output is disabled (High-Impedance state) by CE0 = VIH or CE1 = VIL following the next rising edge of the clock. Refer to Truth Table 1.
5. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers
are for reference use only.
6. 'X' here denotes Left or Right port. The diagram is with respect to that port.
8
6.42
IDT709099L
High-Speed 128K x 8 Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of a Bank Select Pipelined Read(1,2)
t
CYC2
tCH2
tCL2
CLK
ADDRESS(B1)
CE0(B1)
t
SA
tHA
A6
A5
A4
A3
A
2
A
0
A1
tSC
tHC
t
SC
tHC
(3)
CKHZ
tCD2
tCD2
t
tCD2
Q
0
Q3
Q
1
DATAOUT(B1)
ADDRESS(B2)
(3)
(3)
tDC
tCKLZ
t
DC
tCKHZ
tSA
tHA
A6
A5
A4
A3
A2
A
0
A1
t
SC
tHC
CE0(B2)
tSC
tHC
(3)
tCD2
tCKHZ
tCD2
DATAOUT(B2)
Q4
Q2
(3)
(3)
tCKLZ
tCKLZ
4846 drw 09
Timing Waveform of Write with Port-to-Port Flow-Through Read(4,5,7)
CLK "A"
tSW
tHW
R/W "A"
ADDRESS "A"
DATAIN "A"
CLK "B"
t
SA
MATCH
SD HD
VALID
tHA
NO
MATCH
t
t
(6)
tCCS
tCD1
R/W "B"
tHW
t
SW
tHA
tSA
NO
MATCH
ADDRESS "B"
DATAOUT "B"
MATCH
(6)
t
CD1
tCWDD
VALID
VALID
tDC
tDC
4846 drw 10
NOTES:
1. B1 Represents Bank #1; B2 Represents Bank #2. Each Bank consists of one IDT709099 for this waveform, and are setup for depth expansion in this example.
ADDRESS(B1) = ADDRESS(B2) in this situation.
2. OE, and ADS = VIL; CE1(B1), CE1(B2), R/W and CNTRST = VIH.
3. Transition is measured ±200mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
4. CE0 and ADS = VIL; CE1 and CNTRST = VIH.
5. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to.
6. If tCCS < maximum specified, then data from right port READ is not valid until the maximum specified for tCWDD.
If tCCS > maximum specified, then data from right port READ is not valid until tCCS + tCD1. tCWDD does not apply in this case.
7. All timing is the same for both Left and Right ports. Port "A" may be either Left or Right port. Port "B" is the opposite from Port "A".
6.942
IDT709099L
High-Speed 128K x 8 Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Pipelined Read-to-Write-to-Read (OE = VIL)(3)
tCYC2
tCH2
tCL2
CLK
CE0
tSC
tHC
CE1
tSW tHW
R/W
tSW tHW
(4)
An + 3
An + 4
An
An +1
An + 2
An + 2
ADDRESS
tSA
tHA
tSD
tHD
DATAIN
Dn + 2
(1)
(1)
tCKLZ
tCD2
tCD2
(2)
tCKHZ
Qn + 3
Qn
DATAOUT
READ
NOP(5)
WRITE
READ
4846 drw 11
Timing Waveforn of Pipelined Read-to-Write-to-Read (OE Controlled)(3)
t
CYC2
tCH2
tCL2
CLK
CE0
tSC
tHC
CE1
t
SW tHW
R/W
tSW tHW
(4)
An + 4
An
An +1
An + 2
An + 3
Dn + 3
An + 5
ADDRESS
t
SA
tHA
t
SD
t
HD
DATAIN
Dn + 2
(1)
CKLZ
tCD2
tCD2
t
(2)
Qn
Qn + 4
DATAOUT
(1)
t
OHZ
OE
READ
WRITE
READ
4846 drw 12
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
3. CE0 and ADS = VIL; CE1 and CNTRST = VIH. "NOP" is "No Operation".
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only.
5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
10
6.42
IDT709099L
High-Speed 128K x 8 Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Flow-Through Read-to-Write-to-Read (OE = VIL)(3)
t
CYC1
tCH1
tCL1
CLK
CE0
tSC
tHC
CE1
tSW tHW
R/W
tSW tHW
ADDRESS(4)
An + 4
An
An + 3
An +1
An + 2
An + 2
tSA
tHA
tSD
tHD
DATAIN
Dn + 2
tCD1
tCD1
tCD1
tCD1
(2)
Qn + 3
Qn
READ
Qn + 1
DATAOUT
(1)
CKLZ
(1)
CKHZ
tDC
tDC
t
t
NOP(5)
READ
WRITE
.
4846 drw 13
TimingWaveformof Flow-ThroughRead-to-Write-to-Read(OE Controlled)(3)
tCYC1
tCH1
tCL1
CLK
CE0
tSC
tHC
CE1
tSW tHW
R/W
tSW tHW
(4)
An + 5
An
tHA
An +1
An + 2
An + 3
Dn + 3
An + 4
ADDRESS
tSA
t
SD tHD
DATAIN
Dn + 2
tOE
tDC
tCD1
tCD1
tCD1
(2)
Qn + 4
Qn
DATAOUT
(1)
CKLZ
(1)
t
tOHZ
tDC
OE
READ
WRITE
READ
4846 drw 14
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. Output state (High, Low, or High-impedance is determined by the previous cycle control signals.
3. CE0 and ADS = VIL; CE1 and CNTRST = VIH. "NOP" is "No Operation".
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only.
5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
61.412
IDT709099L
High-Speed 128K x 8 Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Pipelined Read with Address Counter Advance(1)
t
CYC2
tCH2
tCL2
CLK
tSA
tHA
An
ADDRESS
tSAD tHAD
ADS
t
SAD tHAD
CNTEN
tSCN tHCN
tCD2
Qn + 2(2)
Qx - 1(2)
Qx
Qn + 3
Qn + 1
Qn
DATAOUT
tDC
READ
READ
WITH
COUNTER
HOLD
READ WITH COUNTER
EXTERNAL
ADDRESS
COUNTER
4846 drw 15
TimingWaveformof Flow-ThroughReadwithAddressCounterAdvance(1)
t
CYC1
tCH1
tCL1
CLK
tSA
tHA
An
ADDRESS
tSAD tHAD
ADS
tSAD
tHAD
tSCN
tHCN
CNTEN
tCD1
Qn + 3(2)
Qx(2)
Qn
Qn + 4
Qn + 1
Qn + 2
DATAOUT
tDC
READ
READ
EXTERNAL
ADDRESS
READ WITH COUNTER
COUNTER
HOLD
WITH
COUNTER
4846 drw 16
NOTES:
1. CE0 and OE = VIL; CE1, R/W, and CNTRST = VIH.
2. If there is no address change via ADS = VIL (loading a new address) or CNTEN = VIL (advancing the address), i.e. ADS = VIH and CNTEN = VIH, then the data output
remains constant for subsequent clocks.
12
6.42
IDT709099L
High-Speed 128K x 8 Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Address Counter Advance
(Flow-Through or Pipelined Outputs)(1)
t
CYC2
tCH2
tCL2
CLK
tSA
tHA
An
ADDRESS
INTERNAL(3)
ADDRESS
An(7)
An + 2
An + 4
An + 1
An + 3
tSAD tHAD
ADS
CNTEN
t
SD tHD
Dn + 4
Dn + 1
Dn + 3
Dn
Dn + 1
Dn + 2
DATAIN
WRITE
EXTERNAL
ADDRESS
WRITE
WITH COUNTER
WRITE
COUNTER HOLD
WRITE WITH COUNTER
4846 drw 17
Timing Waveform of Counter Reset (Pipelined Outputs)(2)
t
CYC2
tCH2
tCL2
CLK
t
SA tHA
ADDRESS(4)
An + 2
An
An + 1
INTERNAL(3)
ADDRESS
Ax(6)
0
An + 1
1
An
t
SW tHW
R/W
ADS
CNTEN
t
SRST
tHRST
CNTRST
t
SD
tHD
D0
DATAIN
(5)
Qn
Q1
Q0
DATAOUT
.
COUNTER(6)
RESET
WRITE
ADDRESS 0
READ
ADDRESS 0
READ
ADDRESS n
READ
ADDRESS n+1
READ
ADDRESS 1
4846 drw 18
NOTES:
1. CE0 and R/W = VIL; CE1 and CNTRST = VIH.
CE0 = VIL; CE1 = VIH.
2.
3. The "Internal Address" is equal to the "External Address" when ADS = VIL and equals the counter output when ADS = VIH.
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only.
5. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
6. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset cycle.
7. CNTEN = VIL advances Internal Address from ‘An’ to ‘An +1’. The transition shown indicates the time required for the counter to advance. The ‘An +1’ Address is written
to during this cycle.
61.432
IDT709099L
High-Speed 128K x 8 Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Depth and Width Expansion
A Functional Description
The IDT709099 features dual chip enables (refer to Truth Table I)
in order to facilitate rapid and simple depth expansion with no require-
ments for external logic. Figure 4 illustrates how to control the various
chip enables in order to expand two devices in depth.
The IDT709099 provides a true synchronous Dual-Port Static
RAM interface. Registered inputs provide minimal set-up and hold
times on address, data, and all critical control inputs. All internal
registers are clocked on the rising edge of the clock signal, however,
the self-timed internal write pulse is independent of the LOW to HIGH
transition of the clock signal.
The 709099 can also be used in applications requiring expanded
width, as indicated in Figure 4. Since the banks are allocated at the
discretion of the user, the external controller can be set up to drive the
input signals for the various devices as required to allow for 16-bit
or wider applications.
An asynchronous output enable is provided to ease asynchronous
bus interfacing. Counter enable inputs are also provided to stall the
operation of the address counters for fast interleaved memory appli-
cations.
CE0 = VIL or CE1 = VIL for one clock cycle will power down the
internal circuitry to reduce static power consumption. Multiple chip
enables allow easier banking of multiple IDT709099's for depth
expansion configurations. When the Pipelined output mode is en-
abled, two cycles are required with CE0 = VIL and CE1 = VIH to re-
activate the outputs.
A17
IDT709099
IDT709099
CE0
CE0
CE1
CE1
VCC
VCC
Control Inputs
Control Inputs
IDT709099
IDT709099
CE1
CE1
CE0
CE0
CNTRST
CLK
ADS
Control Inputs
Control Inputs
CNTEN
R/W
OE
4846 drw 19
Figure 4. Depth and Width Expansion with IDT709099
14
6.42
IDT709099L
High-Speed 128K x 8 Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Ordering Information
A
XXXXX
99
A
A
A
A
Device
Type
Power Speed
Package
Process/
Temperature
Range
Tube or Tray
Tape and Reel
Blank
8
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
Blank
)
I(1
)
G(2
Green
PF
100-pin TQFP (PN100)
9
12
Commercial & Industrial
Speed in nanoseconds
Commercial Only
L
Low Power
709099 1024K (128K x 8-Bit) Synchronous Dual-Port RAM
4846 drw 20
NOTE:
1. Industrial temperature range is available. For specific other, packages and powers contact your sales office.
2. Green parts available. For specific speeds, packages and powers contact your sales office.
DatasheetDocumentHistory
9/30/99:
11/10/99:
12/22/99:
1/5/01:
InitialPublicRelease
Replaced IDT logo
Page 1
Page 3
Page 4
Addedmissingdiamond
Changedinformation in Truth Table II
Increasedstoragetemperatureparameter
ClarifiedTA parameter
Page 5
DCElectricalparameters–changedwordingfrom"open"to"disabled"
Added overbar to CE in notes
Changed±200mVto0mVinnotes
RemovedPreliminarystatus
11/09/01:
Page 2
Addeddaterevisionforpinconfiguration
AddedIndustrialtemptocolumnheadingandvaluesfor9nsspeedtoDC&ACElectricalCharacteristics
AddedIndustrialtempofferingto9nsorderinginformation
RemovedIndustrialtempfootnotefromalltables
Page 5 & 7
Page 15
Page 4, 5 & 7
61.452
IDT709099L
High-Speed 128K x 8 Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
DatasheetDocumentHistory(continued)
01/29/09:
Page 15
Page 1
Page 15
Page 7
Removed "IDT" from orderable part number
Addedgreenpartsavailabilitytofeatures
Addedgreenindicatortoorderinginformation
08/20/10:
InordertocorrecttheheadernotesoftheACElectCharsTableandalignthemwiththeIndustrialtemprange
values located in the table, the commercial TA header note has been removed
Pages 8-11
Inordertocorrectthefootnotesoftimingdiagrams,CNTEN hasbeenremovedtoreconcilethefootnotes
with the CNTEN logic definition found in Truth Table II - Address Counter Control
Removedthe7.5nsspeedgradefromthecommercialoffering
Page 1
Page 5
Page 7
Removedthe7nsspeedgradefromthecommercialofferingintheDCElectricalCharacteristicstable
Removedthe7nsspeedgradefromthecommercialofferingintheACElectricalCharacteristicstable
Page 15
Page 1
Page 2
Removed the 7ns speed grade from the commercial offering in the ordering information
NumbersforPiplinedOutputModeupdated:includesclocktodataout, cycletimeandoperation
RemovedIDTinreferencetofabrication
04/08/15:
Page 2 &16
Page 6
The package code PN100-1 changed to PN100 to match standard package codes
CorrectedtypointheTypicalOutputDerating(LumpedCapitiveLoad)diagram
AddedTapeandReeltoOrderingInformation
Page 16
CORPORATE HEADQUARTERS
for SALES:
for Tech Support:
408-284-2794
6024 Silver Creek Valley Road
San Jose, CA 95138
800-345-7015 or 408-284-8200
fax: 408-284-2775
www.idt.com
DualPortHelp@idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
16
6.42
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