70914S12PFG [IDT]
HIGH SPEED 36K (4K X 9) SYNCHRONOUS DUAL-PORT RAM;
| 型号： | 70914S12PFG |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | HIGH SPEED 36K (4K X 9) SYNCHRONOUS DUAL-PORT RAM 静态存储器 内存集成电路 |
| 文件： | 总12页 (文件大小：133K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT70914S
HIGH SPEED 36K (4K X 9)
SYNCHRONOUS
DUAL-PORT RAM
LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018
– Data input, address, and control registers
– Fast 12ns clock to data out
– Self-timed write allows fast cycle times
– 16nscycletimes, 60MHzoperation
Clock Enable feature
TTL-compatible, single 5V (+ 10%) power supply
Guaranteed data output hold times
Available in 68-pin PLCC, and 80-pin TQFP
Industrial temperature range (-40°C to +85°C) is available for
selectedspeeds
Features
◆
High-speed clock-to-data output times
– Commercial:12/15/20ns(max.)
Low-poweroperation
◆
◆
◆
◆
◆
◆
– IDT70914S
Active: 850 mW (typ.)
Standby: 50 mW (typ.)
Architecture based on Dual-Port RAM cells
– Allowsfullsimultaneousaccessfrombothports
Synchronous operation
◆
◆
◆
Green parts available, see ordering information
– 4ns setup to clock, 1ns hold on all control, data, and address
inputs
Functional Block Diagram
I/O0-8R
I/O0-8L
WRITE
LOGIC
WRITE
LOGIC
MEMORY
ARRAY
SENSE
AMPS
SENSE
AMPS
DECODER DECODER
REG
en
REG
en
OE
CLK
CLKEN
R
OE
CLK
CLKEN
L
L
R
L
R
Self-
Self-
timed
Write
Logic
timed
Write
Logic
R/W
L
REG
R/WR
REG
CEL
CER
A0L-A11L
A0R-A11R
3490 drw 01
FEBUARY 2018
1
DSC-3490/11
©2018 Integrated Device Technology, Inc.
IDT70914S
High-Speed 36K (4K x 9) Synchronous Dual-Port Static RAM
Commercial Temperature Range
Description
user's option. This feature is especially useful in data communication
applications where it is necessary to use a parity bit for transmission/
receptionerrorchecking.
FabricatedusingCMOShigh-performancetechnology,these Dual-
Ports typicallyoperateononly850mWofpoweratmaximumhigh-speed
clock-to-dataoutput times as fast as12ns.An automaticpowerdown
feature, controlled by CE, permits the on-chip circuitry of each port to
enter a very low standby power mode.
The IDT70914 is a high-speed 4K x 9 bit synchronous Dual-Port
RAM. The memory array is based on Dual-Port memory cells to allow
simultaneous access from both ports. Registers on control, data, and
address inputs provide low set-up and hold times. The timing latitude
providedbythisapproachallowsystemstobedesignedwithveryshort
cycletimes.Withaninputdataregister,thisdevicehasbeenoptimizedfor
applicationshavingunidirectionaldatafloworbidirectionaldataflowin
bursts.
The IDT70914 ispackaged ina68-pinPLCC,andan80-pinTQFP.
TheIDT70914utilizesa9-bitwidedatapathtoallowforparityatthe
Pin Configurations(1,2,3)
26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
A
5L
9
8
7
6
5
4
3
2
N/C
I/O5L
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
A4L
A3L
A2L
A1L
A0L
VCC
I/O4L
I/O3L
I/O2L
I/O1L
I/O0L
GND
GND
I/O0R
I/O1R
I/O2R
I/O3R
CLKEN
CLK
CLK
CLKEN
L
L
70914
J68(4)
1
R
68
67
66
65
64
63
62
61
R
A0R
A1R
A2R
A3R
A4R
A5R
A6R
VCC
I/O4R
I/O5R
44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
3490 drw 03
,
NOTES:
1. All VCC pins must be connected to power supply.
2. All ground pins must be connected to ground supply.
3. J68-1 package body is approximately .95 in x .95 in x .17 in.
4. This package code is used to reference the package diagram.
6.42
2
Comme
IDT70914S
High-Speed 36K (4K x 9) Synchronous Dual-Port Static RAM
Commercial Temperature Range
Pin Configuration(1,2,3) (con't.)
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
N/C
A6R
40
N/C
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
N/C
A5R
I/O5R
I/O4R
VCC
A4R
A3R
A2R
I/O3R
I/O2R
I/O1R
I/O0R
GND
GND
I/O0L
I/O1L
I/O2L
I/O3L
I/O4L
VCC
A1R
A0R
CLKENR
CLKR
CLKL
CLKENL
A0L
70914
PN80(4)
A1L
A2L
A3L
A4L
A5L
I/O5L
N/C
N/C
N/C
N/C
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
3490 drw 04
INDEX
NOTES:
1. All VCC pins must be connected to power supply.
2. All ground pins must be connected to ground supply.
3. PN80-1 package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
6.432
IDT70914S
High-Speed 36K (4K x 9) Synchronous Dual-Port Static RAM
Commercial Temperature Range
Absolute Maximum Ratings(1)
Maximum Operating Temperature
and Supply Voltage(1,2)
Symbol
Rating
Unit
Com'l Only
Grade
Ambient
Temperature
GND
VCC
(2)
V
TERM
Terminal Voltage
with Respect
to GND
-0.5 to +7.0
V
Commercial
0OC to +70OC
0V
5.0V + 10%
(2)
3490 tbl 02
V
TERM
Terminal Voltage
-0.5 to VCC
-55 to +125
V
NOTES:
1. ThisistheparameterTA.Thisisthe"instanton"casaetemperature
Temperature
Under Bias
oC
TBIAS
2. Industrialtemperature:forspecific speeds,packagesandpowerscontactyour
Storage
Temperature
-65 to +150
50
oC
T
STG
IOUT
DC Output
Current
mA
3490 tbl 01
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VTERM must not exceed VCC + 10% for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of VTERM > Vcc + 10%.
Recommended DC Operating
Conditions
Symbol
Parameter
Min.
Typ.
Max. Unit
V
CC
Supply Voltage
4.5
5.0
5.5
0
V
V
V
GND
Ground
0
0
V
IH
IL
Input High Voltage
Input Low Voltage
2.2
6.0(2)
0.8
____
-0.5(1)
V
____
Capacitance
(TA = +25°C, f = 1.0MHz) TQFP Only
V
3490 tbl 03
NOTES:
1. VIL > -1.5V for pulse width less than 10ns.
2. VTERM must not exceed VCC + 10%.
Symbol
Parameter
Input Capacitance
Output Capacitance
Conditions
IN = 3dV
OUT = 3dV
Max. Unit
CIN
V
8
9
pF
COUT
V
pF
3490 tbl 04
NOTES:
1. These parameters are determined by device characterization, but are not
production tested.
2. 3dV references the interpolated capacitance when the input and output switch
from 0V to 3V or from 3V to 0V.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VCC = 5.0V ± 10%)
70914S
Symbol
|ILI
|ILO
Parameter
Input Leakage Current(1)
Test Conditions
CC = 5.5V, VIN = 0V to VCC
CE = VIH, VOUT = 0V to VCC
OL = +4mA
OH = -4mA
Min.
Max.
Unit
___
|
V
10
10
µA
µA
V
___
___
|
Output Leakage Current
Output Low Voltage
Output High Voltage
V
OL
OH
I
0.4
___
V
I
2.4
V
3490 tbl 05
NOTE:
1. At VCC < 2.0V, input leakages are undefined
6.42
4
Comme
IDT70914S
High-Speed 36K (4K x 9) Synchronous Dual-Port Static RAM
Commercial Temperature Range
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(4) (VCC = 5V ± 10%)
70914S12
70914S15
Com'l Only
Com'l Only
Typ.(2)
Typ.(2)
Symbol
Parameter
Test Condition
and CE
Version
Max.
Max.
Unit
ICC
Dynamic Operating
Current
(Both Ports Active)
CE
L
R = VIL,
COM'L
190
95
310
180
90
300
mA
Outputs Disabled
(1)
f = fMAX
ISB1
Standby Current
(Both Ports - TTL
Level Inputs)
CEL and CER = VIH
(1)
COM'L
COM'L
150
220
140
210
mA
mA
f = fMAX
ISB2
Standby Current
(One Port - TTL
Level Inputs)
CE"A" = VIL and
(3)
CE"B" = VIH
170
10
160
10
Active Port Outputs
(1)
Disabled, f=fMAX
ISB3
Full Standby
Both Ports CE
R and
Current (Both
Ports - All CMOS
Level Inputs)
CE > VCC - 0.2V
IN > VCC - 0.2V or
IN < 0.2V, f = 0(2)
L
COM'L
COM'L
15
15
mA
V
V
ISB4
Full Standby
Current (One
Port - All CMOS
Level Inputs)
CE"A" < 0.2V and
CE"B" > VCC - 0.2V(3)
mA
165
210
155
200
V
V
IN > VCC - 0.2V or
IN < 0.2V, Active Port
Outputs Disabled
(1)
f = fMAX
3490 tbl 06a
70914S20
Com'l Only
Symbol
Parameter
Test Condition
and CE
Version
Typ.(2)
Max.
Unit
ICC
Dynamic Operating
Current
(Both Ports Active)
CE
L
Outputs Disabled
R = VIL,
COM'L
170
85
290
130
mA
(1)
f = fMAX
ISB1
Standby Current
(Both Ports - TTL
Level Inputs)
CEL and CER = VIH
(1)
COM'L
COM'L
mA
mA
f = fMAX
ISB2
Standby Current
(One Port - TTL
Level Inputs)
CE"A" = VIL and
(3)
CE"B" = VIH
Active Port Outputs
Disabled, f=fMAX
150
10
200
15
(1)
ISB3
Full Standby
Both Ports CE
CE > VCC - 0.2V
IN > VCC - 0.2V or
IN < 0.2V, f = 0(2)
R and
Current (Both
Ports - All CMOS
Level Inputs)
L
COM'L
COM'L
mA
V
V
ISB4
Full Standby
Current (One
Port - All CMOS
Level Inputs)
CE"A" < 0.2V and
CE"B" > VCC - 0.2V(3)
IN > VCC - 0.2V or
IN < 0.2V, Active Port
mA
145
190
V
V
Outputs Disabled
f = fMAX
(1)
3490 tbl 06b
NOTES:
1. At fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS" at input levels
of GND to 3V.
2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. Vcc=5V, TA=25°C forTyp, andarenotproductiontested. ICCDC=150mA(Typ)
5. Industrialtemperature:forspecificspeeds,packagesandpowerscontactyoursalesoffice.
6.452
IDT70914S
High-Speed 36K (4K x 9) Synchronous Dual-Port Static RAM
Commercial Temperature Range
AC Test Conditions
Input Pulse Levels
GND to 3.0V
3ns Max.
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
1.5V
1.5V
Figures 1,2 and 3
3490 tbl 07
5V
5V
893Ω
893Ω
5pF*
DATAOUT
DATAOUT
30pF
347Ω
347Ω
3490 drw 05
3490 drw 06
Figure 1. AC Output Test load.
Figure 2. Output Test Load
(For tCKLZ, tCKHZ, tOLZ, and tOHZ).
*Including scope and jig.
8
7
6
9pF is the I/O capacitance
of this device, and 30pF is the
AC Test Load Capacitance
5
∆tCD
(Typical, ns)
4
3
2
1
0
,
20 40 60 80 100 120 140 160 180 200
Capacitance (pF)
-1
3490 drw 07
Figure 3. Typical Output Derating (Lumped Capacitive Load).
6.42
6
Comme
IDT70914S
High-Speed 36K (4K x 9) Synchronous Dual-Port Static RAM
Commercial Temperature Range
AC Electrical Characteristics Over the Operating Temperature Range
(Read and Write Cycle Timing)(3)
(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C)
70914S12
Com'l Only
70914S15
Com'l Only
Symbol
tCYC
tCH
Parameter
Min.
16
Max.
Min.
20
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
____
____
____
____
____
____
Clock Cycle Time
Clock High Time
6
6
tCL
Clock Low Time
6
6
____
____
tCD
Clock High to Output Valid
Registered Signal Set-up Time
Registered Signal Hold Time
Data Output Hold After Clock High
12
15
____
____
tS
4
1
3
4
1
3
____
____
____
____
____
____
tH
tDC
(1,2)
tCKLZ
tCKHZ
tOE
Clock High to Output Low-Z
2
2
Clock High to Output High-Z(1,2)
Output Enable to Output Valid
Output Enable to Output Low-Z(1,2)
7
7
____
____
____
____
7
8
____
____
tOLZ
tOHZ
tSCK
tHCK
0
0
(1,2)
____
____
Output Disable to Output High-Z
7
7
____
____
Clock Enable, Disable Set-up Time
Clock Enable, Disable Hold Time
4
2
4
2
____
____
Port-to-Port Delay
____
____
____
____
tCWDD
tCSS
Write Port Clock High to Read Data Delay
25
13
30
15
ns
Clock-to-Clock Setup Time
ns
3490 tbl 08a
70914S20
Com'l Only
Symbol
Parameter
Min.
20
8
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
____
____
____
t
CYC
CH
CL
CD
Clock Cycle Time
t
Clock High Time
t
Clock Low Time
8
____
t
Clock High to Output Valid
Registered Signal Set-up Time
Registered Signal Hold Time
Data Output Hold After Clock High
Clock High to Output Low-Z(1,2)
Clock High to Output High-Z(1,2)
Output Enable to Output Valid
Output Enable to Output Low-Z(1,2)
Output Disable to Output High-Z(1,2)
Clock Enable, Disable Set-up Time
Clock Enable, Disable Hold Time
20
____
t
S
H
5
1
3
____
____
____
t
t
DC
CKLZ
CKHZ
OE
t
2
____
t
9
____
t
10
____
tOLZ
0
____
tOHZ
9
____
tSCK
5
2
____
tHCK
Port-to-Port Delay
Write Port Clock High to Read Data Delay
Clock-to-Clock Setup Time
____
____
t
CWDD
35
15
ns
tCSS
ns
3490 tbl 08b
NOTES:
1. Transition is measured 0mV from Low or High impedance voltage with the Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. Industrial temperature: for specific speeds, packages and powers contact your sales office.
6.472
IDT70914S
High-Speed 36K (4K x 9) Synchronous Dual-Port Static RAM
Commercial Temperature Range
Timing Waveform of Read Cycle, Either Side
tCYC
tCH
tCL
CLK
tSCK
tSCK
tHCK
CLKEN
tS
tH
CE
R/W
ADDRESS
DATAOUT
An
An + 1
An + 2
An + 3
(1)
tDC
tCKHZ
tCD
Qn
Qn + 1
Qn + 1
(1)
tCKLZ
(1)
(1)
tOHZ
tOLZ
tOE
OE
3490 drw 08
Timing Waveform of Write with Port-to-Port Read(2,3,4)
CLK "A"
R/W "A"
NO
MATCH
ADDR "A"
DATA IN "A"
CLK "B"
MATCH
VALID
(5)
tCCS
tCD
R/W "B"
NO
MATCH
ADDR "B"
MATCH
tCWDD
tCD
DATA OUT "B"
VALID
VALID
tDC
3490 drw 09
NOTES:
1. Transition is measured 200mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. CEL = CER = VIL, CLKENL = CLKENR = VIL.
3. OE = VIL for the reading port, port 'B'.
4. All timing is the same for left and right ports. Ports "A" may be either the left or right port. Port "B" is opposite from port "A".
5. If tCCS < maximum specified, then data from right port READ is not valid until the maximum specified for tCWDD.
If tCCS > maximum specified, then data from right port READ is not valid until tCCS + tCD. tCWDD does not apply in this case.
6.42
8
Comme
IDT70914S
High-Speed 36K (4K x 9) Synchronous Dual-Port Static RAM
Commercial Temperature Range
Timing Waveform of Read-to-Write Cycle No. 1(1,2) (tCYC = min.)
tCYC
tCYC
tCH
tCL
tCH
tCL
CLK
CLKEN
CE
tS
tH
(1)
R/W
An + 1(1)
Dn + 1(1)
ADDRESS
DATAIN
An
An + 1
An + 2
Dn + 2
(3)
tCD
tCKHZ
DATAOUT
Qn
(3)
tCKLZ
3490 drw 10
Timing Waveform of Read-to-Write Cycle No. 2(4) (tCYC > min.)
(4)
tCYC
tCH
tCL
CLK
CLKEN
CE
tS
tH
R/W
ADDRESS
DATAIN
An
An + 1
Dn + 1
tCD
DATAOUT
Qn
(3)
tCKLZ
tOHZ
OE
3490 drw 11
NOTES:
1. For tCYC = min.; data out coincident with the rising edge of the subsequent write clock can occur. To ensure writing to the correct address location, the write must
be repeated on the second write clock rising edge. If CE = VIL, invalid data will be written into array. The An+1 must be rewritten on the following cycle.
2. OE LOW throughout.
3. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
4. For tCYC > min.; OE may be used to avoid data out coincident with the rising edge of the subsequent write clock. Use of OE will eliminate the need for the write to
be repeated.
6.492
IDT70914S
High-Speed 36K (4K x 9) Synchronous Dual-Port Static RAM
Commercial Temperature Range
Functional Description
transitionsoftheclocksignalallowingtheshortestpossiblerealizedcycle
times.Clockenableinputsareprovidedtostalltheoperationoftheaddress
and data input registers without introducing clock skew for very fast
interleavedmemoryapplications.
A HIGH on the CE input for one clock cycle will power down the
internalcircuitrytoreducestaticpowerconsumption.
The IDT70914 provides a true synchronous Dual-Port Static RAM
interface.Registeredinputsprovideveryshortset-upandholdtimeson
address,data,andallcriticalcontrolinputs.Allinternalregistersareclocked
ontherisingedgeoftheclock signal.Anasynchronousoutputenableis
providedtoeaseasynchronousbusinterfacing.
The internal write pulse width is dependent on the LOW to HIGH
Truth Table I: Read/Write Control(1)
Inputs
Outputs
Synchronous(3)
Asynchronous
Mode
CLK
R/W
I/O0-8
High-Z
CE
H
L
OE
X
↑
↑
↑
↑
X
L
Deselected, Power-Down
X
DATAIN
DATAOUT
High-Z
Selected and Write Enabled
Read Selected and Data Output Enable Read
Outputs Disabled
L
H
X
L
X
H
3490 tbl 09
Truth Table II: Clock Enable Function Table(1)
Inputs
Register Inputs
Register Outputs(4)
ADDR DATAOUT
Mode
CLK(3)
ADDR
DATAIN
CLKEN(2)
Load "1"
Load "0"
↑
↑
↑
X
L
L
H
L
H
L
H
L
H
L
H
H
X
X
X
X
NC
NC
NC
NC
Hold (do nothing)
3490 tbl 10
NOTES:
1. 'H' = HIGH voltage level steady state, 'h' = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition, 'L' = LOW voltage level steady state 'l' = LOW
voltage level one set-up time prior to the LOW-to-HIGH clock transition, 'X' = Don't care, 'NC' = No change
2. CLKEN = VIL must be clocked in during Power-Up.
3. ControlsignalsareinitiatedandterminatedontherisingedgeoftheCLK,dependingontheirinputlevel.WhenR/WandCEareLOW,awritecycleisinitiatedontheLOW-to-HIGHtransition
oftheCLK.TerminationofawritecycleisdoneonthenextLOW-to-HIGHtransitionoftheCLK.
4. The register outputs are internal signals from the register inputs being clocked in or disabled by CLKEN.
6.42
10
Comme
IDT70914S
High-Speed 36K (4K x 9) Synchronous Dual-Port Static RAM
Commercial Temperature Range
Ordering Information
A
XXXXX
99
A
A
A
A
Device
Type
Power Speed
Package
Process/
Temperature
Range
Tube or Tray
Tape and Reel
Blank
8
Blank
Commercial (0°C to +70°C)
)
G(2
Green
J
PF
68-pin PLCC (J68)
80-pin TQFP (PN80)
12
15
20
Commercial Only
Commercial Only
Commercial Only
Speed in nanoseconds
S
Standard Power
70914
36K (4K x 9-Bit) Synchronous Dual-Port RAM
3490 drw 12
NOTES:
1. IndustrialtemperaturerangeisavailableonselectedTQFPpackagesinstandardpower.Forspecificspeeds,packagesandpowerscontactyoursalesoffice.
2. Greenpartsavailable.Forspecificspeeds,packagesandpowerscontactyoursalesoffice.
LEADFINISH(SnPb)partsareinEOLprocess.ProductDiscontinuationNotice-PDN#SP-17-02
Datasheet Document History
3/10/99:
Initiateddatasheetdocumenthistory
Convertedtonewformat
Cosmeticandtypographicalcorrections
Page2and3Addedadditionalnotestopinconfigurations
Changeddrawingformat
6/7/99:
11/10/99:
5/24/00:
Replaced IDT logo
Page 4 Increasedstoragetemperatureparameter
ClarifiedTA parameter
Page 5 DCElectricalparameters–changedwordingfrom"open"to"disabled"
Changed 200mVto0mVinnotes
1/12/01:
RemovedPGApinout(obsoletepackage)
Changed cycle time of 12ns part from 17ns (58MHz) to 16ns (60MHz)
Page 11 Removed "IDT" from orderable part number
Page 1 Addedgreenpartsavailabilitytofeatures
Page 11 Addedgreenindicatortoorderinginformation
10/21/08:
05/24/10:
6.1412
IDT70914S
High-Speed 36K (4K x 9) Synchronous Dual-Port Static RAM
Commercial Temperature Range
Datasheet Document History (con't.)
06/05/15:
Pages1-12 RemovedMilitaryandIndustrialTemperatureRangesfromdatasheetheader
Page 1 RemovedMilitaryspeedofferingsfromtheFeatures
Page 2 Removed MIL-PRF 38535 QML support information
Pages 2 ,3 &11 The package codes J68-1 and PN80-1 changed to J68 and PN80 respectively to match the standard
packagecodes
Page 4 RemovedthemilitaryandindustrialofferingsintheAbsoluteMaxRatings&theMaxOperatingTemptables
Page 5 Removed the military and industrial offerings in the DC Elec Chars tables
Page 6 CorrectedtypointheTypicalOutputDeratingdrawing
Page 7 Removed military offering for the 20 & 25 speed grades in the AC Elec Chars table
Removed the military temp range information from the AC Elec Chars table title
Page 11 Added Tape and Reel to and removed military offering & 25ns speed grade from the Ordering Information
Page 2 Changed diagram for the J68 pin configuration by rotating package pin labels and pin numbers 90 degrees
clockwise to reflect pin1 orientation and added pin 1 dot at pin 1
04/28/16:
Removed all four chamfers from J68 and aligned the top and bottom pin labels in the standard direction
Page 3 Changed diagram for the PN80 pin configuration by rotating package pin labels and pin numbers 90 degrees
counter clockwise to reflect pin 1 orientation and added pin 1 dot at pin 1
Added the IDT logo, changed the text to be in alignment with new diagram marking specs
forallpinconfigurationsandupdatedfootnotereferencesfortheJ68&thePN80pinconfigurations
Page 11 RemovedIndustrialtemprangeinformationfromtheOrderingInformation
ProductDiscontinuationNotice-PDN#SP-17-02
02/02/18:
Last time buy expires June 15, 2018
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
for Tech Support:
408-284-2794
DualPortHelp@idt.com
800-345-7015 or 408-284-8200
fax: 408-284-2775
www.idt.com
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
6.42
12
相关型号：
70914S15JG
Dual-Port SRAM, 4KX9, 15ns, CMOS, PQCC68, 0.950 X 0.950 X 0.170 INCH, GREEN, PLASTIC, LCC-68
IDT
70914S20JG
Dual-Port SRAM, 4KX9, 20ns, CMOS, PQCC68, 0.950 X 0.950 X 0.170 INCH, GREEN, PLASTIC, LCC-68
IDT
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