709269S12PFGI8 [IDT]
Dual-Port SRAM;
| 型号： | 709269S12PFGI8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Dual-Port SRAM 静态存储器 内存集成电路 |
| 文件： | 总17页 (文件大小：691K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HIGH-SPEED 32/16K x 16
SYNCHRONOUS
IDT709279/69S/L
DUAL-PORT STATIC RAM
Features
◆
◆
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed clock to data access
– Commercial:9/12/15ns(max.)
– Industrial: 12ns (max.)
Counter enable and reset features
◆
Full synchronous operation on both ports
– 4ns setup to clock and 1ns hold on all control, data, and
addressinputs
◆
–
Data input, address, and control registers
◆
Low-power operation
– Fast 9ns clock to data out in the Pipelined output mode
– Self-timedwriteallowsfastcycletime
– IDT709279/69S
Active:950mW(typ.)
– 15ns cycle time, 67MHz operation in Pipelined output mode
Separate upper-byte and lower-byte controls for
multiplexed bus and bus matching compatibility
TTL- compatible, single 5V (±10%) power supply
Industrial temperature range (–40°C to +85°C) is
available for selected speeds
◆
Standby: 5mW (typ.)
– IDT709279/69L
◆
◆
Active:950mW(typ.)
Standby: 1mW (typ.)
◆
◆
Flow-Through or Pipelined output mode on either port via
the FT/PIPE pin
◆
◆
Available in a 100-pin Thin Quad Flatpack (TQFP) package
Green parts available. See ordering information
Dual chip enables allow for depth expansion without
additionallogic
FunctionalBlockDiagram
R/W
UB
R
R/W
L
R
UB
L
CE0L
CE1L
CE0R
CE1R
1
0
1
0
0/1
0/1
LBR
LBL
OE
R
OE
L
1a 0a
1b 0b
0a 1a
0b 1b
0/1
FT/PIPE
L
b
a
0/1
a
b
FT/PIPER
,
,
I/O8L
I/O15L
-
I/O8R-I/O15R
I/O
Control
I/O
Control
I/O0L-I/O7L
I/O0R-I/O7R
(1)
(1)
A
14R
0R
A
14L
Counter/
Address
Reg.
Counter/
Address
Reg.
A
MEMORY
ARRAY
A
0L
CLK
ADS
CNTEN
R
CLK
L
L
L
R
ADS
R
CNTEN
CNTRST
L
CNTRST
R
3243 drw 01
NOTE:
1. A14X is a NC for IDT709269.
JUNE 2015
1
DSC-3243/15
©2015 Integrated Device Technology, Inc.
IDT709279/69S/L
Preliminary
High-Speed 32/16K x 16 Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Description
Withaninputdataregister,theIDT709279/69hasbeenoptimizedfor
applicationshavingunidirectionalorbidirectionaldataflowinbursts.An
automaticpowerdownfeature, controlledbyCE0 andCE1, permitsthe
on-chip circuitry of each port to enter a very low standby power mode.
Fabricated using CMOS high-performance technology, these devices
typicallyoperateononly950mWofpower.
The IDT709279/69 is a high-speed 32/16K x 16 bit synchronous
Dual-Port RAM. The memory array utilizes Dual-Port memory cells to
allowsimultaneousaccessofanyaddressfrombothports.Registerson
control,data,andaddressinputsprovideminimalsetupandholdtimes.
The timing latitude provided by this approach allows systems to be
designedwithveryshortcycletimes.
PinConfigurations(2,3,4)
Index
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
A
A
A
A
A
A
NC
NC
NC
LB
UB
CE0R
CE1R
CNTRST
GND
R/W
OE
FT/PIPE
GND
9R
A
9L
1
75
74
10R
11R
12R
13R
14R
A10L
2
A
A
11L
12L
3
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
4
A13L
5
(1)
(1)
A
14L
6
7
NC
NC
NC
LB
UB
8
9
R
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
L
IDT709279/69PF
R
L
(5)
PN100
CE0L
CE1L
CNTRST
100-Pin TQFP
R
(6)
L
Top View
VCC
R
R/W
OE
FT/PIPE
L
R
L
L
R
GND
I/O15L
I/O14L
I/O13L
I/O12L
I/O11L
I/O10L
I/O15R
I/O14R
I/O13R
I/O12R
I/O11R
I/O10R
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
3243 drw 02
NOTES:
1. A14X is a NC for IDT709269.
2. All VCC pins must be connected to power supply.
3. All GND pins must be connected to ground supply.
4. Package body is approximately 14mm x 14mm x 1.4mm
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
2
6.42
IDT709279/69S/L
Preliminary
High-Speed 32/16K x 16 Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
PinNames
Left Port
Right Port
CE0R, CE1R
R/W
OE
Names
Chip Enables(3)
CE0L, CE1L
R/W
OE
L
R
Read/Write Enable
Output Enable
Address
L
R
(1)
(1)
A
0L - A14L
A
0R - A14R
I/O0R - I/O15R
CLK
UB
LB
ADS
CNTEN
CNTRST
FT/PIPE
I/O0L - I/O15L
CLK
UB
LB
ADS
CNTEN
CNTRST
FT/PIPE
Data Input/Output
Clock
L
R
Upper Byte Select(2)
Lower Byte Select(2)
Address Strobe
Counter Enable
Counter Reset
Flow-Through/Pipeline
Power
L
R
L
R
L
R
NOTES:
1. A14x is a NC for IDT709269.
L
R
2. LB and UB are single buffered regardless of state of FT/PIPE.
3. CEo and CE1 are single buffered when FT/PIPE = VIL,
CEo and CE1 are double buffered when FT/PIPE = VIH,
i.e. the signals take two cycles to deselect.
L
R
L
R
V
SS
GND
Ground
3243 tbl 01
Truth Table I—Read/Write and Enable Control(1,2,3)
Upper Byte
I/O8-15
Lower Byte
I/O0-7
CLK
↑
CE
X
1
R/W
X
Mode
Deselected—Power Down
OE
X
X
X
X
X
X
L
CE
0
UB
X
X
H
L
LB
X
X
H
H
L
H
X
L
L
L
L
L
L
L
L
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
L
X
Deselected—Power Down
Both Bytes Deselected
Write to Upper Byte Only
Write to Lower Byte Only
Write to Both Bytes
↑
H
H
H
H
H
H
H
H
X
↑
L
DIN
↑
H
L
L
High-Z
DIN
↑
L
L
DIN
DIN
↑
L
H
L
H
H
H
X
DOUT
High-Z
Read Upper Byte Only
Read Lower Byte Only
Read Both Bytes
↑
L
H
L
High-Z
DOUT
↑
L
L
DOUT
DOUT
↑
H
X
L
L
High-Z
High-Z
Outputs Disabled
3243 tbl 02
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. ADS, CNTEN, CNTRST = X.
3. OE is an asynchronous input signal.
6.432
IDT709279/69S/L
Preliminary
High-Speed 32/16K x 16 Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Truth Table II—Address Counter Control(1,2)
Previous Internal
External
Internal
Address
MODE
Address
Address
Used
CLK
↑
I/O(3)
ADS CNTEN CNTRST
An
X
X
An
An
L(4)
H
X
L(5)
H
H
DI/O (n)
External Address Used
↑
An + 1
An + 1
D
I/O(n+1) Counter Enabled—Internal Address generation
↑
X
An + 1
X
H
H
H
DI/O(n+1) External Address Blocked—Counter disabled (An + 1 reused)
X
A
0
X
X
L(4)
DI/O(0)
Counter Reset to Address 0
↑
3243 tbl 03
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. CE0, LB, UB, and OE = VIL; CE1 and R/W = VIH.
3. Outputs configured in Flow-Through Output mode: if outputs are in Pipelined mode the data out will be delayed by one cycle.
4. ADS is independent of all other signals including CE0, CE1, UB and LB.
5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other signals including CE0, CE1, UB and LB.
RecommendedOperating
RecommendedDCOperating
Conditions
Temperature and Supply Voltage(1)
Symbol
Parameter
Min.
4.5
Typ.
Max. Unit
Grade
Ambient
GND
V
CC
Temperature
V
CC
Supply Voltage
5.0
5.5
V
V
V
Commercial
0OC to +70OC
-40OC to +85OC
0V
0V
5.0V
5.0V
+
+
10%
GND
Ground
0
0
0
Industrial
10%
V
IH
Input High Voltage
Input Low Voltage
2.2
-0.5(2)
6.0(1)
0.8
____
3243 tbl 04
____
NOTES:
V
IL
V
1. This is the parameter TA. This is the "instant on" case temperature.
3243 tbl 05
NOTES:
1. VTERM must not exceed VCC + 10%.
2. VIL > -1.5V for pulse width less than 10ns.
AbsoluteMaximumRatings(1)
Capacitance(1)
Symbol
Rating
Commercial
& Industrial
Unit
(TA = +25°C, f = 1.0MHz)
Symbol
Parameter
Input Capacitance
Output Capacitance
Conditions(2)
IN = 0V
OUT = 0V
Max. Unit
(2)
V
TERM
Te rminal Vo ltag e
with Respect
to GND
-0.5 to +7.0
V
CIN
V
9
pF
(2)
COUT
V
10
pF
T
BIAS
STG
JN
OUT
TemperatureUnder Bias
Storage Temperature
Junction Temperature
DC Output Current
-55 to +125
-65 to +150
+150
oC
oC
oC
3243 tbl 07
NOTES:
T
1. These parameters are determined by device characterization, but are not
production tested.
T
2. COUT also references CI/O.
I
50
mA
3243 tbl 06
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect
reliability.
2. VTERM must not exceed VCC + 10% for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of VTERM > VCC + 10%.
3. Ambient Temperature Under Bias. No AC Conditions. Chip Deselect.
4
6.42
IDT709279/69S/L
Preliminary
High-Speed 32/16K x 16 Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature Supply Voltage Range (VCC = 5.0V ± 10%)
709279/69S/L
Min. Max.
Symbol
|ILI
|ILO
Parameter
Input Leakage Current(1)
Test Conditions
CC = 5.5V, VIN = 0V to VCC
CE = VIH or CE = VIL, VOUT = 0V to VCC
OL = +4mA
OH = -4mA
Unit
µA
µA
V
___
___
___
|
V
10
10
|
Output Leakage Current
Output Low Voltage
Output High Voltage
0
1
V
OL
I
0.4
___
V
OH
I
2.4
V
3243 tbl 08
NOTE:
1. At VCC < 2.0V input leakages are undefined.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(6) (VCC = 5V ± 10%)
709279/69X9
Com'l Only
709279/69X12
709279/69X15
Com'l Only
Com'l
& Ind
Typ.(4)
Typ.(4)
Symbol
Parameter
Test Condition
and CE = VIL
Version
COM'L
Max.
Max.
Typ.(4)
Max.
Unit
ICC
Dynamic Operating
Current
S
L
210
390
200
200
345
305
190
325
mA
CE
L
R
(1)
210
350
190
285
Outputs Disabled f = fMAX
(Both Ports Active)
____
____
____
____
____
____
IND
S
L
200
200
380
340
____
____
I
SB1
Standby Current
(Both Ports - TTL
Level Inputs)
COM'L
IND
S
L
50
50
135
115
50
50
110
90
50
50
110
90
mA
mA
CE
L
= CE
R
= VIH
(1)
f = fMAX
____
____
____
____
S
L
50
50
125
105
____
____
____
____
ISB2
Standby Current
(One Port - TTL
Level Inputs)
COM'L
IND
S
L
140
140
270
240
130
130
230
200
120
120
220
190
CE"A" = VIL and
(3)
CE"B" = VIH
Active Port Outp(u1t)s
Disabled, f=fMAX
____
____
____
____
S
L
130
130
245
215
____
____
____
____
ISB3
Full Standby Current
(Both Ports -
Both Ports CE
R
and
COM'L
IND
S
L
1.0
0.2
15
5
1.0
0.2
15
5
1.0
0.2
15
5
mA
CE
L
> VCC - 0.2V
CMOS Level Inputs)
V
V
IN > VCC - 0.2V or
IN < 0.2V, f = 0(2)
____
____
____
____
S
L
1.0
0.2
15
5
____
____
____
____
ISB4
Full Standby Current
(One Port -
mA
COM'L
S
L
130
130
245
225
120
120
205
185
110
110
195
175
CE"A" < 0.2V and
CE"B" > VCC - 0.2V(5)
CMOS Level Inputs)
V
V
IN > VCC - 0.2V or
____
____
____
____
____
____
____
____
IND
S
L
120
120
220
200
IN < 0.2V, Active(1P) ort Outputs
Disabled, f = fMAX
3243 tbl 09
NOTES:
1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS" at input
levels of GND to 3V.
2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. VCC = 5V, TA = 25°C for Typ, and are not production tested. ICC DC(f=0) = 150mA (Typ).
5. CEX = VIL means CE0X = VIL and CE1X = VIH
CEX = VIH means CE0X = VIH or CE1X = VIL
CEX < 0.2V means CE0X < 0.2V and CE1X > VCC - 0.2V
CEX > VCC - 0.2V means CE0X > VCC - 0.2V or CE1X < 0.2V
"X" represents "L" for left port or "R" for right port.
6. 'X' in part numbers indicate power rating (S or L).
6.452
IDT709279/69S/L
Preliminary
High-Speed 32/16K x 16 Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Test Conditions
Input Pulse Levels
GND to 3.0V
3ns Max.
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
1.5V
1.5V
Figures 1,2 and 3
3243 tbl 10
5V
5V
893Ω
893Ω
DATAOUT
DATAOUT
30pF
347Ω
5pF*
347Ω
3243 drw 04
3243 drw 05
Figure 1. AC Output Test load.
Figure 2. Output Test Load
(For tCKLZ, tCKHZ, tOLZ, and tOHZ).
*Including scope and jig.
8
7
6
5
10pF is the I/O capacitance
of this device, and 30pF is the
AC Test Load Capacitance
tCD
tCD
(Typical, ns)
1
,
4
3
2
1
2
0
,
20 40 60 80 100 120 140 160 180 200
Capacitance (pF)
-1
3243 drw 06
Figure 3. Typical Output Derating (Lumped Capacitive Load).
6
6.42
IDT709279/69S/L
Preliminary
High-Speed 32/16K x 16 Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating Temperature Range
(Read and Write Cycle Timing)(3,4) (VCC = 5V ± 10%, TA = 0°C to +70°C)
709279/69X9
Com'l Only
709279/69X12
Com'l
709279/69X15
Com'l Only
& Ind
Symbol
Parameter
Min.
25
15
12
12
6
Max.
Min.
30
20
12
12
8
Max.
____
Min.
35
Max.
____
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
CYC1
Clock Cycle Time (Flow-Through)(2)
Clock Cycle Time (Pipelined)(2)
Clock High Time (Flow-Through)(2)
Clock Low Time (Flow-Through)(2)
Clock High Time (Pipelined)(2)
Clock Low Time (Pipelined)(2)
Clock Rise Time
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
CYC2
CH1
CL1
CH2
CL2
R
25
12
12
10
6
____
8
____
10
____
3
3
3
____
____
____
F
Clock Fall Time
3
____
3
____
3
____
SA
Address Setup Time
4
1
4
1
4
1
4
1
4
1
4
1
4
1
4
4
1
4
1
4
1
4
1
4
1
4
1
4
1
4
4
1
4
1
4
1
4
1
4
1
4
1
4
1
4
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
HA
Address Hold Time
SC
Chip Enable Setup Time
Chip Enable Hold Time
Byte Enable Setup Time
Byte Enable Hold Time
R/W Setup Time
HC
SB
HB
SW
HW
SD
R/W Hold Time
Input Data Setup Time
Input Data Hold Time
HD
SAD
ADS Setup Time
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
HAD
SCN
HCN
ADS Hold Time
CNTEN Setup Time
CNTEN Hold Time
SRST
HRST
OE
CNTRST Setup Time
1
____
1
____
1
____
CNTRST Hold Time
Output Enable to Data Valid
Output Enable to Output Low-Z(1)
Output Enable to Output High-Z(1)
9
____
12
____
15
____
OLZ
2
2
2
OHZ
CD1
CD2
DC
1
____
7
1
____
7
1
____
7
Clock to Data Valid (Flow-Through)(2)
Clock to Data Valid (Pipelined)(2)
Data Output Hold After Clock High
Clock High to Output High-Z(1)
Clock High to Output Low-Z(1)
20
25
30
____
____
____
9
____
12
____
15
____
2
2
2
2
2
2
2
2
2
CKHZ
CKLZ
9
____
9
____
9
____
Port-to-Port Delay
____
____
____
____
____
____
t
t
CWDD
Write Port Clock High to Read Data Delay
Clock-to-Clock Setup Time
35
15
40
15
50
20
ns
CCS
ns
3243 tbl 11
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). This parameter is guaranteed by device characteriza-
tion, but is not production tested.
2. The Pipelined output parameters (tCYC2, tCD2) apply to either or both left and right ports when FT/PIPE = VIH. Flow-through parameters (tCYC1, tCD1) apply when
FT/PIPE = VIL for that port.
3. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE) and FT/PIPE. FT/PIPE should be treated as a DC
signal, i.e. steady state during operation.
4. 'X' in part number indicates power rating (S or L).
6.472
IDT709279/69S/L
Preliminary
High-Speed 32/16K x 16 Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Read Cycle for Flow-Through Output
(FT/PIPE"X" = VIL)(3,7)
tCYC1
tCH1
tCL1
CLK
CE0
tSC
tHC
tSC
tHC
(4)
CE1
tSB
tHB
UB, LB
R/W
tHB
tSB
tHW
tSW
tSA
t
HA
ADDRESS(5)
DATAOUT
An
An + 1
An + 2
An + 3
(1)
tDC
tCD1
tCKHZ
Qn
Qn + 1
Qn + 2
(1)
(1)
tCKLZ
tDC
(1)
tOHZ
tOLZ
OE (2)
tOE
3243 drw 07
Timing Waveform of Read Cycle for Pipelined Output (FT/PIPE"X" = VIH)(3,7)
tCYC2
tCH2
tCL2
CLK
CE
0
tSC
tHC
tSC
tHC
(4)
CE1
t
SB
tHB
tSB
tHB
(6)
UB, LB
R/W
tHW
tSW
tSA
tHA
ADDRESS(5)
DATAOUT
An
An + 1
An + 2
Qn
An + 3
(1 Latency)
t
DC
tCD2
Qn + 1
Qn + 2 (6)
(1)
tCKLZ
(1)
(1)
t
OHZ
tOLZ
OE(2)
tOE
3243 drw 08
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.
3. ADS = VIL, CNTEN and CNTRST = VIH.
4. The output is disabled (High-Impedance state) by CE0 = VIH, CE1 = VIL, UB = VIH, or LB = VIH following the next rising edge of the clock. Refer to Truth Table 1.
5. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers
are for reference use only.
6. If UB or LB was HIGH, then the Upper Byte and/or Lower Byte of DATAOUT for Qn + 2 would be disabled (High-Impedance state).
7. "x" denotes Left or Right port. The diagram is with respect to that port.
8
6.42
IDT709279/69S/L
Preliminary
High-Speed 32/16K x 16 Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of a Bank Select Pipelined Read(1,2)
t
CYC2
tCH2
tCL2
CLK
ADDRESS(B1)
CE0(B1)
t
SA
tHA
A6
A5
A4
A3
A
2
A
0
A1
tSC
tHC
t
SC
tHC
(3)
CKHZ
tCD2
tCD2
t
tCD2
Q
0
Q3
Q
1
DATAOUT(B1)
ADDRESS(B2)
(3)
(3)
tDC
tCKLZ
t
DC
tCKHZ
tSA
tHA
A6
A5
A4
A3
A2
A
0
A1
tSC
tHC
CE0(B2)
tSC
tHC
(3)
tCD2
tCKHZ
tCD2
DATAOUT(B2)
Q4
Q2
(3)
(3)
tCKLZ
tCKLZ
3243 drw 09
Timing Waveform of a Bank Select Flow-Through Read(6)
t
CYC1
tCH1
tCL1
CLK
tSA
tHA
A6
A5
A4
A3
A2
A0
A1
ADDRESS(B1)
tSC
tHC
CE0(B1)
t
SC
tHC
(1)
tCD1
tCD1
tCKHZ
tCD1
tCD1
D
0
D
3
D5
D
1
DATAOUT(B1)
ADDRESS(B2)
(1)
(1)
(1)
tDC
tCKLZ
tCKLZ
tDC
t
CKHZ
tSA
tHA
A6
A
5
A4
A3
A2
A
0
A1
t
SC
tHC
CE0(B2)
tSC
tHC
(1)
(1)
tCD1
tCKHZ
tCD1
tCKHZ
D4
DATAOUT(B2)
D2
(1)
(1)
tCKLZ
tCKLZ
3243 drw 09a
NOTES:
1. B1 Represents Bank #1; B2 Represents Bank #2. Each Bank consists of one IDT709279/69 for this waveform, and are setup for depth expansion in this
example. ADDRESS(B1) = ADDRESS(B2) in this situation.
2. UB, LB, OE, and ADS = VIL; CE1(B1), CE1(B2), R/W, CNTEN, and CNTRST = VIH.
3. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
4. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH.
5. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to.
6. If tCCS < maximum specified, then data from right port READ is not valid until the maximum specified for tCWDD.
If tCCS > maximum specified, then data from right port READ is not valid until tCCS + tCD1. tCWDD does not apply in this case.
6.492
IDT709279/69S/L
Preliminary
High-Speed 32/16K x 16 Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform with Port-to-Port Flow-Through Read(1,2,3,5)
CLK "A"
tSW
tHW
R/W "A"
ADDRESS "A"
DATAIN "A"
CLK "B"
t
SA
MATCH
SD HD
VALID
tHA
NO
MATCH
t
t
(4)
tCCS
tCD1
R/W "B"
tHW
t
SW
tHA
tSA
NO
MATCH
ADDRESS "B"
DATAOUT "B"
MATCH
(4)
tCD1
tCWDD
VALID
VALID
tDC
t
DC
3243 drw 10
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH.
3. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to.
4. If tCCS < maximum specified, then data from right port READ is not valid until the maximum specified for tCWDD.
If tCCS > maximum specified, then data from right port READ is not valid until tCCS + tCD1. tCWDD does not apply in this case.
5. All timing is the same for both left and right ports. Port "A" may be either left or right port. Port "B" is the opposite of Port "A".
10
6.42
IDT709279/69S/L
Preliminary
High-Speed 32/16K x 16 Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Pipelined Read-to-Write-to-Read (OE = VIL)(3)
tCYC2
tCH2
tCL2
CLK
CE0
tSC
tHC
CE1
tSB
tHB
UB, LB
R/W
tSW tHW
tSW tHW
(4)
An + 3
An + 4
An
An +1
An + 2
An + 2
ADDRESS
tSA
tHA
tSD
t
HD
DATAIN
Dn + 2
(1)
(1)
tCKLZ
tCD2
tCD2
(2)
tCKHZ
Qn + 3
Qn
DATAOUT
READ
NOP(5)
WRITE
READ
3243 drw 11
Timing Waveforn of Pipelined Read-to-Write-to-Read (OE Controlled)(3)
t
CYC2
tCH2
tCL2
CLK
CE0
tSC
tHC
CE1
tSB
tHB
UB, LB
R/W
tSW tHW
tSW tHW
(4)
An + 4
An
An +1
An + 2
An + 3
Dn + 3
An + 5
ADDRESS
t
SA
tHA
t
SD
tHD
DATAIN
Dn + 2
(1)
CKLZ
tCD2
tCD2
t
(2)
Qn
Qn + 4
DATAOUT
(1)
t
OHZ
OE
READ
WRITE
READ
3243 drw 12
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
3. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH.
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use
only.
5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
6.1412
IDT709279/69S/L
Preliminary
High-Speed 32/16K x 16 Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Flow-Through Read-to-Write-to-Read (OE = VIL)(3)
t
CYC1
tCH1
tCL1
CLK
CE0
tSC
tHC
CE1
tSB
tHB
UB, LB
R/W
tSW tHW
tSW tHW
(4)
An + 4
An
An + 3
An +1
An + 2
Qn + 1
An + 2
ADDRESS
tSA
tHA
t
SD tHD
DATAIN
Dn + 2
t
CD1
t
CD1
tCD1
tCD1
(2)
Qn + 3
Qn
READ
DATAOUT
(1)
(1)
tDC
tDC
tCKLZ
t
CKHZ
NOP(5)
READ
WRITE
3243 drw 13
TimingWaveformof Flow-ThroughRead-to-Write-to-Read(OE Controlled)(3)
tCYC1
tCH1
tCL1
CLK
CE0
tSC
tHC
CE1
tSB
tHB
UB, LB
R/W
tSW tHW
tSW tHW
(4)
An + 5
An
tHA
An +1
An + 2
An + 3
Dn + 3
An + 4
ADDRESS
tSA
t
SD tHD
DATAIN
Dn + 2
tOE
tDC
tCD1
tCD1
tCD1
(2)
Qn + 4
Qn
DATAOUT
(1)
CKLZ
(1)
t
tOHZ
tDC
OE
READ
WRITE
READ
3243 drw 14
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. Output state (High, Low, or High-impedance is determined by the previous cycle control signals.
3. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH.
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use
only.
5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
12
6.42
IDT709279/69S/L
Preliminary
High-Speed 32/16K x 16 Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Pipelined Read with Address Counter Advance(1)
t
CYC2
tCH2
tCL2
CLK
tSA
tHA
An
ADDRESS
tSAD tHAD
ADS
t
SAD tHAD
CNTEN
tSCN tHCN
tCD2
Qn + 2(2)
Qx - 1(2)
Qx
Qn + 3
Qn + 1
Qn
DATAOUT
tDC
READ
EXTERNAL
ADDRESS
READ
WITH
COUNTER
COUNTER
HOLD
READ WITH COUNTER
3243 drw 15
TimingWaveformof Flow-ThroughReadwithAddressCounterAdvance(1)
t
CYC1
tCH1
tCL1
CLK
tSA
tHA
An
ADDRESS
tSAD tHAD
ADS
tSAD
tHAD
tSCN
tHCN
CNTEN
tCD1
Qn + 3(2)
Qx(2)
Qn
Qn + 4
Qn + 1
Qn + 2
DATAOUT
tDC
READ
READ
EXTERNAL
ADDRESS
READ WITH COUNTER
COUNTER
HOLD
WITH
COUNTER
3243 drw 16
NOTES:
1. CE0, OE, UB, and LB = VIL; CE1, R/W, and CNTRST = VIH.
2. If there is no address change via ADS = VIL (loading a new address) or CNTEN = VIL (advancing the address), i.e. ADS = VIH and CNTEN = VIH, then the data
output remains constant for subsequent clocks.
6.1432
IDT709279/69S/L
Preliminary
High-Speed 32/16K x 16 Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Address Counter Advance
(Flow-Through or Pipelined Outputs)(1)
t
CYC2
tCH2
tCL2
CLK
tSA
tHA
An
ADDRESS
INTERNAL(3)
ADDRESS
An(1)
An + 2
An + 4
An + 1
An + 3
tSAD tHAD
ADS
CNTEN
t
SD tHD
Dn + 4
Dn + 1
Dn + 3
Dn
Dn + 1
Dn + 2
DATAIN
WRITE
EXTERNAL
ADDRESS
WRITE
WITH COUNTER
WRITE
COUNTER HOLD
WRITE WITH COUNTER
3243 drw 17
Timing Waveform of Counter Reset (Pipelined Outputs)(2)
t
CYC2
tCH2
tCL2
CLK
tSA tHA
(4)
An + 2
An
An + 1
ADDRESS
INTERNAL(3)
ADDRESS
Ax(6)
0
An + 1
1
An
t
SW tHW
R/W
ADS
CNTEN
tSRST
tHRST
CNTRST
t
SD
tHD
D0
DATAIN
(5)
Qn
Q1
Q0
DATAOUT
COUNTER
RESET
WRITE
READ
ADDRESS 0
READ
READ
READ
ADDRESS 1
ADDRESS 0
ADDRESS n ADDRESS n+1
3243 drw 18
NOTES:
1. CE0, UB, LB, and R/W = VIL; CE1 and CNTRST = VIH.
CE0, UB, LB = VIL; CE1 = VIH.
2.
3. The "Internal Address" is equal to the "External Address" when ADS = VIL and equals the counter output when ADS = VIH.
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use
only.
5. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
6. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset cycle. ADDR0 will be accessed. Extra cycles
are shown here simply for clarification.
7. CNTEN = VIL advances Internal Address from ‘An’ to ‘An +1’. The transition shown indicates the time required for the counter to advance. The ‘An +1’Address is
written to during this cycle.
14
6.42
IDT709279/69S/L
Preliminary
High-Speed 32/16K x 16 Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Depth and Width Expansion
AFunctionalDescription
The IDT709279/69 features dual chip enables (refer to Truth Table
I)inordertofacilitaterapidandsimpledepthexpansionwithnorequire-
mentsforexternallogic.Figure4illustrateshowtocontrolthevariouschip
enables in order to expand two devices in depth.
The IDT709279/69 provides a true synchronous Dual-Port Static
RAM interface.Registeredinputsprovideminimalset-upandholdtimes
onaddress, data, andallcriticalcontrolinputs. Allinternalregistersare
clocked on the rising edge of the clock signal, however, the self-timed
internalwritepulseisindependentoftheLOWtoHIGHtransitionoftheclock
signal.
The IDT709279/69 can also be used in applications requiring ex-
pandedwidth,asindicatedinFigure4.Sincethebanksareallocatedat
thediscretionoftheuser,theexternalcontrollercanbesetuptodrivethe
input signals for the various devices as required to allow for 32-bit
orwiderapplications.
An asynchronous output enable is provided to ease asynchronous
bus interfacing. Counter enable inputs are also provided to stall the
operationoftheaddresscountersforfastinterleavedmemoryapplications.
AHIGHonCE0oraLOWonCE1 foroneclockcyclewillpowerdown
the internal circuitry to reduce static power consumption. Multiple chip
enables allow easier banking of multiple IDT709279/69's for depth
expansionconfigurations.WhenthePipelinedoutputmodeisenabled,two
cycles are required with CE0 LOW and CE1 HIGH to re-activate the
outputs.
(1)
A15/A14
IDT709279/69
IDT709279/69
CE0
CE0
VCC
VCC
CE1
CE1
Control Inputs
Control Inputs
IDT709279/69
IDT709279/69
CE1
CE1
CE0
CE0
,
CNTRST
CLK
Control Inputs
Control Inputs
ADS
CNTEN
R/W
3243 drw 19
OE
Figure 4. Depth and Width Expansion with IDT709279/69
NOTE:
1. A14 is for IDT709269.
6.1452
IDT709279/69S/L
Preliminary
High-Speed 32/16K x 16 Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
OrderingInformation
A
A
XXXXX
99
A
A
A
Device
Type
Power
Speed Package
Process/
Temperature
Range
Tube or Tray
Tape and Reel
Blank
8
Blank
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
)
I(1
)
G(2
Green
PF
100-pin TQFP (PN100)
Commercial Only
Commercial & Industrial
Commercial Only
9
12
15
Speed in nanoseconds
S
L
Standard Power
Low Power
512K (32K x 16-Bit) Synchronous Dual-Port RAM
256K (16K x 16-Bit) Sunchronous Dual-Port RAM
709279
709269
3243 drw 20
NOTES:
1. Industrialtemperaturerangeisavailable.Forspecificspeeds,packagesandpowerscontactyoursalesoffice.
2.Greenpartsavailable.Forspecificspeeds,packagesandpowerscontactyourlocalsalesoffice.
Ordering Information for Flow-through Devices
Old Flow-through Part
70927S/L20
New Combined Part
709279S/L9
70927S/L25
709279S/L12
70927S/L30
709279S/L15
3243 tbl 12
IDT Clock Solution for IDT709279/69 Dual-Port
Dual-Port I/O Specitications
Clock Specifications
IDT
Non-PLL
Clock Device
IDT Dual-Port
Part Number
Input Duty
Cycle
Requirement
Input
Capacitance
Maximum Jitter
Frequency Tolerance
Voltage
5
I/O
709279/69
TTL
9pF
40%
100
150ps
49FCT805T
3243 tbl 13
16
6.42
IDT709279/69S/L
Preliminary
High-Speed 32/16K x 16 Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
DatasheetDocumentHistory
12/9/98:
Initiateddatasheetdocumenthistory
Convertedtonewformat
Cosmeticandtypographicalcorrections
Addedadditionalnotestopinconfigurations
Pages13&14Updatedtimingwaveforms
Page15AddedDepthandWidthExpansionsection
Changeddrawingformat
06/03/99:
Page 3 Deleted note 6 for Table II
Replaced IDT logo
11/10/99:
03/31/00:
CombinedPipelined709279familyandFlow-through70927familyofferingsintoonedatasheet
Changed±200mVinwaveformnotesto0mV
Addedcorrespondingpartchartwithorderinginformation
05/24/00:
Page 1 Inserted diamond in copy
Page4ChangedinformationinTruthTableII, Increasedstoragetemperatureparameter, clarifiedTA parameter
Page5ChangedDCElectricalparameters–changedwordingfrom"Open"to"Disabled"
Page 16 Fixed typeface in heading
AddedIndustrialTemperatureRangesandremovedrelatednotes
Pages 1, 16 and Page Header Removed Preliminary status
08/24/01:
06/21/04:
Page 5 & 7 Removed Industrial Temperature Ranges for 15ns speed from DC and AC Electrical Characteristics
Page16RemovedIndustrialTemperaturefrom15nsspeedinorderinginformation
Consolidatedmultipledevicesintoonedatasheet
Page 2 Added date revision to pin configuration
Page 4 AddedJunctionTemperaturetoAbsoluteMaximumRatingsTable
AddedAmbientTemperaturefootnote
Page 5 & 6 Added 6ns & 7ns speed DC power numbers to the DC Electrical Characteristics Table
Page 8 Added6ns& 7nsspeedACtimingnumberstotheACElectricalCharacteristicsTable
Page 17 Added 6ns & 7ns speed grades to ordering information
Added IDT Clock Solution Table
Page 1 & 18 Replaced old logo with new TM logo
01/29/09:
06/24/15:
Page 17 Removed "IDT" from orderable part number
Page 1 AddedgreenavailabilitytoFeatures
Page 2 RemovedIDTinreferencetofabrication
Page 2 Removeddatefromthe100-pinTQFPconfiguration
Page 2 & 17 The package code PN100-1 changed to PN100 to match standard package codes
Page 5 Removed the X6 & X7 speed grade options and combined the X9, X12 & X15 speed grade
options into one DC Elec Chars table
Page 7 Removed the X6 & X7 speed grade options from the AC Elec Chars table
Page 16 AddedGreenandTape&ReelindicatorstotheOrderingInformation
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
for Tech Support:
408-284-2794
800-345-7015 or 408-284-8200
fax: 408-284-2775
www.idt.com
DualPortHelp@idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
6.1472
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