70P264L55BYI [IDT]
Application Specific SRAM, 16KX16, 55ns, CMOS, PBGA81, 0.50 MM PITCH, BGA-81;
| 型号： | 70P264L55BYI |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Application Specific SRAM, 16KX16, 55ns, CMOS, PBGA81, 0.50 MM PITCH, BGA-81 静态存储器 内存集成电路 |
| 文件： | 总14页 (文件大小：111K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT70P264/254/244L
DATASHEET
VERY LOW POWER 1.8V
16K/8K/4K x 16
DUAL-PORT STATIC RAM
Features
◆
Power supply isolation functionality to aid system power
management
Separate upper-byte and lower-byte control for multiplexed
bus compatibility
Left port is selectable 3.0V, 2.5V or 1.8V
Right port is 1.8V I/O
LVTTL-compatible, single 1.8V (±100mV) power supply
Available in 81 Ball 0.5mm-pitch BGA
Industrial temperature range (-40°C to +85°C)
Green parts available, see ordering information
◆
True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
High-speed access
◆
◆
◆
– Industrial:40/55ns (max.)
Low-power operation
◆
◆
◆
◆
◆
◆
IDT70P264/254/244L
Active:27mW(typ.)
Standby:3.6µW(typ.)
On-chip port interrupt logic which supports level shift
output
◆
◆
Fully asynchronous operation from either port
Functional Block Diagram
R/W
R
R/W
L
UB
R
UB
L
LB
CE
OE
R
LB
CE
OE
L
L
L
R
R
,
I/O8L-I/O15L
I/O0L-I/O7L
I/O8R-I/O15R
I/O0R-I/O7R
I/O
Control
I/O
Control
(1)
(1)
A
A
13R
0R
A
13L
Address
Decoder
Address
Decoder
MEMORY
ARRAY
A
0L
14
14
CE
L
CE
OE
R/W
R
INTERRUPT
LOGIC
OE
L
L
R
R/W
R
INT
L
INTR
7148 drw 01
NOTE:
1. A13X is a NC for IDT70P254. A13X and A12X are NC for IDT70P244.
FEBRUARY 2009
1
DSC-7148/2
©2008IntegratedDeviceTechnology,Inc.
IDT70P264/254/244L
Datasheet
Low Power 1.8V 16K/8K/4K x 16 Dual-Port Static RAM
Industrial Temperature Range
Description
featurecontrolledbyCE permitstheon-chipcircuitryofeachporttoenter
a very low standby power mode.
Fabricated using IDT’s CMOS high-performance technology,
thesedevices typicallyoperateononly27mWofpower.
TheIDT70P264/254/244ispackagedina81ball0.5mm-pitchBall
Grid Array. The package is a 1mm thick and designed to fit in wireless
The IDT70P264/254/244 is a very low power 16K/8K/4K x 16
Dual-PortStaticRAM.TheIDT70P264/254/244isdesignedtobeused
asastand-alone256/128/64K-bitDual-PortSRAM.
Thisdeviceprovidestwoindependentportswithseparatecontrol,
address,andI/Opinsthatpermitindependent,asynchronousaccessfor
reads or writes to any location in memory. An automatic power down handsetapplications.
PinConfigurations
70P264/254/244BY
BY-81
81-Ball 0.5mm Pitch BGA
Top View
1
A2R
A1R
A0R
UBR
VSS
UBL
A0L
A6L
A5L
2
3
4
5
6
7
8
9
A5R
A7R
A6R
A3R
LBL
A4L
A1L
A8L
A7L
A11R
A9R
A8R
A4R
INTL
A2L
CER
VSS
I/O14R I/O12R I/O10R I/O8R
A
B
C
D
E
F
A
B
C
D
E
F
(1)
(1)
A12R
A10R
INTR
LBR
A3L
A13R
I/O13R I/O11R
VSS
I/O7R
I/O6R
I/O3R
I/O1R
R/WR I/O15R
VDD
I/O9R
I/O4R
OER
VDD
I/O5R
I/O2R
I/O13L I/O15L I/O0R
I/O3L
OEL
CEL
VSS
I/O5L
I/O4L
I/O0L
I/O1L
I/O12L VDDQL I/O14L
(1)
A11L
A12L
I/O9L
I/O2L
I/O11L I/O10L
G
H
J
G
H
J
(1)
A9L
A13L
VSS
I/O8L
I/O7L
A10L
R/WL
VDDQL
I/O6L
1
2
3
4
5
6
7
8
9
7148 drw 02
NOTE:
1. A13X is a NC for IDT70P254. A13X and A12X are NC for IDT70P244.
6.42
2
IDT70P264/254/244L
Low Power 1.8V 16K/8K/4K x 16 Dual-Port Static RAM
Datasheet
Industrial Temperature Range
PinNames
Left Port
Right Port
Names
Chip Enable (Input)
Read/Write Enable (Input)
Output Enable (Input)
Address (Input)
CE
R/W
OE
L
CE
R
L
R/W
R
L
OE
R
(1)
(1)
A
0L - A13L
I/O0L - I/O15L
UB
LB
INT
A
0R - A13R
I/O0R - I/O15R
UB
LB
INT
Data Input/Output
Upper Byte Select (Input)
Lower Byte Select (Input)
Interrupt Flag (Output)
L
R
L
R
NOTE:
1. A13X is a NC for IDT70P254. A13X and A12X are NC for IDT70P244.
L
R
Power for Core + Right Port I/O
(1.8V) (Input)
VDD
Left Port I/O Supply Voltage
(1.8V, 2.5V or 3.0V) (Input)
VDDQL
VSS
Ground (0V) (Input)
7148 tbl 01
Truth Table I: Non-Contention Read/Write Control
Inputs
OE
X
Outputs
R/W
X
X
L
I/O8-15
High-Z
High-Z
DATAIN
High-Z
DATAIN
I/O0-7
High-Z
High-Z
High-Z
DATAIN
DATAIN
High-Z
DATAOUT
DATAOUT
High-Z
Mode
Deselected: Power Down
CE
H
X
L
UB
X
H
L
LB
X
H
H
L
X
Both Bytes Deselected
Write to Upper Byte Only(1)
Write to Lower Byte Only(1)
Write to Both Bytes(1)
Read Upper Byte Only
Read Lower Byte Only
Read Both Bytes
X
L
L
X
H
L
L
L
X
L
L
H
H
H
X
L
L
H
L
DATAOUT
High-Z
L
L
H
L
L
L
L
DATAOUT
High-Z
X
H
X
X
Outputs Disabled
7148 tbl 02
NOTE:
1. A0L — A13L ≠ A0R — A13R
6.42
3
IDT70P264/254/244L
Datasheet
Low Power 1.8V 16K/8K/4K x 16 Dual-Port Static RAM
Industrial Temperature Range
AbsoluteMaximumRatings(1)
Symbol
Rating
Industrial
Unit
V
V
TERM
Supply Voltage on VDD
with Respect to GND
-0.5 to +2.9
VTERM
Supply Voltage on VDDQL
with Respect to GND
-0.5 to +3.6
V
(2)
TERM
V
Terminal Voltage with
Respect to GND
-0.5 to VDD +0.3(4)
V
(3)
T
BIAS
STG
JN
Temperature Under Bias
Storage Temperature
Junction Temperature
DC Output Current
-55 to +125
-65 to +150
+150
oC
oC
T
oC
T
I
V
OUT (for
DDQL = 3.0V)
20
mA
I
OUT (for
DC Output Current
20
mA
V
DDQL = 2.5V)
7148 tbl 03
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
2. VTERM must not exceed VDD + 0.3V for more than 25% of the cycle time or 10ns maximum, and
is limited to < 20mA for the period over VTERM = VDD + 0.3V.
3. Ambient Temperature under DC Bias. No AC Conditions. Chip Deselected.
4. VDDQL + 0.3V for left port.
Capacitance
MaximumOperatingTemperature
andSupplyVoltage(1)
(TA = +25°C, f = 1.0MHz)
Symbol
Parameter
Input Capacitance
Output Capacitance
Conditions(2)
IN = 3dV
OUT = 3dV
Max. Unit
Grade
Ambient
GND
VDD
Temperature
CIN
V
9
pF
Industrial
-40OC to +85OC
0V
1.8V
+
100mV
COUT
V
10
pF
7148 tbl 04
7148 tbl 07
NOTE:
NOTES:
1. This is the parameter TA. This is the "instant on" case temperature.
1. This parameter is determined by device characterization but is not production
tested.
2. 3dV references the interpolated capacitance when the input and output signals
switch from 0V to 3V or from 3V to 0V.
6.42
4
IDT70P264/254/244L
Low Power 1.8V 16K/8K/4K x 16 Dual-Port Static RAM
Datasheet
Industrial Temperature Range
RecommendedDCOperatingConditions(VDDQL =3.0V±300mV)
Symbol
Parameter
Min.
1.7
2.7
0
Typ.
Max.
Unit
V
V
V
V
V
V
V
DD
Supply Voltage
1.8
1.9
V
DDQL
SS
Left Port Supply Voltage
Ground
3.0
3.3
V
0
0
V
___
IHL
ILL
Input High Voltage (VDDQL = 3.0V)
Input Low Voltage (VDDQL = 3.0V)
Input High Voltage
Input Low Voltage
2.0
-0.2
1.2
-0.2
V
DDQL + 0.2
0.7
V
___
___
___
V
V
IHR
ILR
V
DD + 0.2
0.4
V
7148 tbl 05
RecommendedDCOperatingConditions(VDDQL =2.5V±100mV)
Symbol
Parameter
Min.
1.7
2.4
0
Typ.
Max.
Unit
V
V
V
V
V
V
V
DD
Supply Voltage
1.8
1.9
V
DDQL
SS
Left Port Supply Voltage
Ground
2.5
2.6
V
0
0
V
___
IHL
ILL
Input High Voltage (VDDQL = 2.5V)
Input Low Voltage (VDDQL = 2.5V)
Input High Voltage
Input Low Voltage
1.7
-0.3
1.2
-0.2
V
DDQL + 0.3
0.6
V
___
___
___
V
IHR
ILR
V
DD + 0.2
0.4
V
V
7148 tbl 06
RecommendedDCOperatingConditions(VDDQL =1.8V±100mV)
Symbol
Parameter
Min.
1.7
1.7
0
Typ.
Max.
Unit
V
V
V
V
V
V
V
DD
Supply Voltage
1.8
1.9
V
DDQL
SS
Left Port Supply Voltage
Ground
1.8
1.9
V
0
0
V
___
IHL
ILL
Input High Voltage (VDDQL = 1.8V)
Input Low Voltage (VDDQL = 1.8V)
Input High Voltage
Input Low Voltage
1.2
-0.2
1.2
-0.2
V
DDQL + 0.2
V
___
___
___
0.4
V
IHR
ILR
V
DD + 0.2
0.4
V
V
7148 tbl 06_5
NOTES:
1. VIL > -1.5V for pulse width less than 10ns.
2. VTERM must not exceed VDD + 0.3V.
6.42
5
IDT70P264/254/244L
Datasheet
Low Power 1.8V 16K/8K/4K x 16 Dual-Port Static RAM
Industrial Temperature Range
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 1.8V ± 100mV)
Symbol
Parameter
Min.
Max.
Unit
Test Conditions
DD = 1.8V, VIN = 0V to
CE = VIH, VOUT = 0V to
OLL = +2mA
OHL = -2mA
OLL = +2mA
OHL = -2mA
OLL = +0.1mA
OHL = -0.1mA
OLR = +0.1mA
OHR = -0.1mA
OL = +2mA
I
I
LI
Input Leakage Current
-1
1
1
µA
µA
V
V
VDD
LO
Output Leakage Current
-1
VDD
___
V
OLL
Output Low Voltage (VDDQL = 3.0V)
Output High Voltage (VDDQL = 3.0V)
Output Low Voltage (VDDQL = 2.5V)
Output High Voltage (VDDQL = 2.5V)
Output Low Voltage (VDDQL = 1.8V)
Output High Voltage (VDDQL = 1.8V)
Output Low Voltage
0.4
I
___
V
V
V
V
V
V
V
V
OHL
2.1
V
I
___
OLL
0.4
V
I
___
OHL
OLL
2.0
V
I
___
0.2
V
I
___
OHL
OLR
OHR
OLINT
V
DDQL - 0.2V
V
I
___
0.2
V
I
___
Output High Voltage
V
DD - 0.2V
V
I
___
(1,2)
Output Low Voltage Interrupt
0.4
V
I
7148 tbl 08
NOTES:
1. Interrupt can be level shifted to a higher voltage by tieing a resistor (R3) to an external power supply (VDDINTX). The value of R3 is a trade off between
tINX and power.
2. VDDINTR > VDD, VDDINTL > VDDQL
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 1.8V ±100mV)
70P264/254/244
Ind'l Only
40ns
Typ.(1)
55ns
Typ.(1)
Symbol
Parameter
Test Condition
L = VIL, Outputs Open
Version
IND'L
Max.
Max.
Unit
IDD
Dynamic Operating Current
(Both Ports Active)
mA
L
L
L
25
40
15
25
CE
R
and CE
(2)
f = fMAX
ISB1
Standby Current (Both Ports
Inactive)
2
2
µA
mA
µA
CE
R
= VDD - 0.2V and CEL =
VDDQL - 0.2V
,
IND'L
IND'L
6
6
(2)
f = fMAX
ISB2
Standby Current (One Port
Inactive, One Port Active)
8.5
18
8.5
14
CE"
f = fMAX
A
" = VIL and CE"
B
" = VIH(3), Active Port Outputs Open
(2)
ISB3
Full Standby Current (Both
Ports Inactive - CMOS Level
Inputs)
CE
f = 0
L
> VDDQL - 0.2V and CE
R
> VDD - 0.2V,
2
IND'L
IND'L
L
L
6
2
6
(3)
ISB4
Standby Current (One Port
Inactive, One Port Active -
CMOS Level Inputs)
8.5
18
8.5
14
mA
CE"A" < 0.2V and CE"B" > VDDQ - 0.2V
,
Active Port Outputs Open
(2)
f = fMAX
7148 tbl 09
NOTES:
1. VDD = 1.8V, TA = +25°C, and are not production tested. IDD = 15mA (typ.)
2. At f = fMAX, address and control lines are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions”.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
6.42
6
IDT70P264/254/244L
Low Power 1.8V 16K/8K/4K x 16 Dual-Port Static RAM
Datasheet
Industrial Temperature Range
AC Test Conditions
Input Pulse Levels
GND to 3.0V/GND to 2.5V/GND to 1.8V
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
3ns Max.
1.5V/1.25V/0.9V
1.5V/1.25V/0.9V
Figure 1A
7148 tbl 10
3.3V
3.0V/2.5V1.8V
R3 = 1kΩ
3.0V/2.5V
1.8V
R1
R1
R2
1022Ω
729Ω
13500Ω
10800Ω
30pF
7148 tbl 10_5
R2
30pF
7148 drw 03a
7148 drw 03
Figure 1B. AC Output Test Load for Interrupt
Figure 1A. AC Output Test Load
(5pF for tLZ, tHZ, tWZ, tOW)
Timing of Power-Up Power-Down
CE
tPU
tPD
I
CC
50
%
50%
I
SB
,
7148 drw 04
6.42
7
IDT70P264/254/244L
Datasheet
Low Power 1.8V 16K/8K/4K x 16 Dual-Port Static RAM
Industrial Temperature Range
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltageRange(2)
70P264/254/244
Ind'l Only
40ns
55ns
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
READ CYCLE
____
____
t
RC
AA
ACE
ABE
AOE
OH
LZ
HZ
PU
PD
Read Cycle Time
40
55
ns
ns
ns
ns
ns
ns
ns
ns
ns
____
____
t
Address Access Time
40
40
40
55
55
55
____
____
____
____
____
____
t
Chip Enable Access Time
Byte Enable Access Time
Output Enable Access Time
Output Hold from Address Change
Output Low-Z Time(1,3)
t
t
25
30
____
____
t
5
5
____
____
t
5
5
Output High-Z Time(1,3)
10
25
____
____
t
t
Chip Enable to Power Up Time(1)
Chip Disable to Power Down Time(1)
0
0
____
____
____
____
t
40
55
ns
7148 tbl 11
NOTES:
1. This parameter is guaranteed by device characterization, but is not production tested.
2. The specification for tDH must be met by the device supplying write data to the SRAM under all operating conditions. Although tDH and tOW values will vary over
voltage and temperature, the actual tDH will always be smaller than the actual tOW.
3. At any given temperature and voltage condition, tHZ is less than tLZ for any given device.
6.42
8
IDT70P264/254/244L
Low Power 1.8V 16K/8K/4K x 16 Dual-Port Static RAM
Datasheet
Industrial Temperature Range
Waveform of Read Cycles
t
RC
ADDRESS
tAA
CE
OE
t
ACE
t
AOE
t
ABE
UB, LB
R/W
tOH
(1)
t
LZ
DATAOUT
VALID DATA
(2)
tHZ
7148 drw 05
,
NOTES:
1. Timing depends on which signal is asserted last, OE, CE, LB, or UB.
2. Timing depends on which signal is de-asserted first CE, OE, LB, or UB.
6.42
9
IDT70P264/254/244L
Datasheet
Low Power 1.8V 16K/8K/4K x 16 Dual-Port Static RAM
Industrial Temperature Range
AC Electrical Characteristics Over the
Operating TemperatureandSupplyVoltage(3)
70P264/254/244
Ind'l Only
40ns
55ns
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
WC
EW
AW
AS
WP
WR
DW
DH
WZ
OW
Write Cycle Time
40
30
30
0
55
45
45
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
Chip Enable to End-of-Write(2)
Address Valid to End-of-Write
Address Set-up Time(2)
Write Pulse Width
t
t
t
25
0
40
0
t
Write Recovery Time
Data Valid to End-of-Write
Data Hold Time(3)
t
20
30
t
0
0
(1)
____
____
t
Write Enable to Output in High-Z
Output Active from End-of-Write(1,3)
15
25
____
____
t
0
0
ns
7148 tbl 12
NOTES:
1. This parameter is guaranteed by device characterization, but is not production tested.
2. To access SRAM, CE = VIL, UB or LB = VIL.
3. The specification for tDH must be met by the device supplying write data to the SRAM under all operating conditions. Although tDH and tOW values will vary over
voltage and temperature, the actual tDH will always be smaller than the actual tOW.
6.42
10
IDT70P264/254/244L
Low Power 1.8V 16K/8K/4K x 16 Dual-Port Static RAM
Datasheet
Industrial Temperature Range
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8)
tWC
ADDRESS
(7)
tHZ
OE
tAW
CE(9)
CE(9)
(3)
(6)
(2)
tWR
tAS
tWP
R/W
(7)
tWZ
tOW
(4)
(4)
DATAOUT
DATAIN
t
DW
tDH
,
7148 drw 06
Timing Waveform of Write Cycle No. 2, CE, UB, LB Controlled Timing(1,5)
tWC
ADDRESS
CE(9)
tAW
(3)
WR
(2)
(6)
AS
t
tEW
t
UB or LB(9)
R/W
tDW
tDH
DATAIN
,,
7148 drw 07
NOTES:
1. R/W or CE or UB & LB must be high during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of a low UB or LB and a LOW CE and a LOW R/W for memory array writing cycle.
3. tWR is measured from the earlier of CE or R/W going HIGH to the end of write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state.
6. Timing depends on which enable signal is asserted last, CE, R/W or byte control.
7. This parameter is guaranteed by device characterization, but is not production tested.
8. If OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be placed
on the bus for the required tDW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified
tWP.
9. To access SRAM, CE = VIL, UB or LB = VIL.
6.42
11
IDT70P264/254/244L
Datasheet
Low Power 1.8V 16K/8K/4K x 16 Dual-Port Static RAM
Industrial Temperature Range
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltageRange
70P264/254/244
Ind'l Only
40ns
55ns
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
INTERRUPT TIMING
____
____
____
____
t
AS
WR
INS
INR
Address Set-up Time
Write Recovery Time
Interrupt Set Time
0
0
ns
ns
ns
t
0
0
____
____
t
35
45
45
45
____
____
t
Interrupt Reset Time
ns
7148 tbl 13
Waveform of Interrupt Timing(1)
tWC
INTERRUPT SET ADDRESS(2)
ADDR"A"
(3)
(4)
t
AS
tWR
CE"A"
R/W"A"
INT"B"
(3)
t
INS
,
7148 drw 08
t
RC
INTERRUPT CLEAR ADDRESS(2)
ADDR"B"
(3)
t
AS
CE"B"
OE"B"
(3)
INR
t
,
INT"B"
7148 drw 09
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.
2. See Interrupt Truth Table II.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
6.42
12
IDT70P264/254/244L
Low Power 1.8V 16K/8K/4K x 16 Dual-Port Static RAM
Datasheet
Industrial Temperature Range
Truth Table II — Interrupt Flag(1)
Left Port
Right Port
(1)
(1)
R/W
L
L
A
13L-A0L
R/W
R
A
13R-A0R
Function
Set Right INT Flag
Reset Right INT Flag
Set Left INT Flag
Reset Left INT Flag
CE
L
OE
L
INT
X
L
CE
R
OE
R
INTR
L
X
X
L
X
X
X
L
3FFF
X
X
X
L
L
X
X
L
X
3FFF
3FFE
X
L
R
X
X
X
H
X
X
R
X
X
L
L
X
X
L
X
3FFE
H
X
L
7148 tbl 14
NOTES:
1. A13X is a NC for IDT70P254. A13X and A12X are NC for IDT70P244. Interrupt Addresses are 1FFF and 1FFE for IDT70P254 and FFF and FFE for IDT70P244.
Interrupts
FunctionalDescription
Iftheuserchoosestheinterruptfunction,amemorylocation(mailbox
ormessagecenter)is assignedtoeachport. Theleftportinterruptflag
(INTL) is asserted when the right port writes to memory location 3FFE
(HEX) (1FFE for IDT70P254, FFE for IDT70P244), where a write is
defined as the CE=R/W=VIL per Truth Table II. The left port clears the
interruptbyaccessingaddresslocation3FFE (1FFEforIDT70P254,FFE
forIDT70P244)whenCER=OER=VIL,R/Wisa"don'tcare".Likewise,
therightportinterruptflag(INTR)isassertedwhentheleftportwritesto
memorylocation3FFF(HEX)(1FFFforIDT70P254,FFFforIDT70P244)
andtocleartheinterruptflag(INTR),therightportmustreadthememory
location3FFF.Themessage(16bits)at3FFEor3FFFisuser-defined,
sinceitisanaddressableSRAMlocation.Iftheinterruptfunctionisnotused,
addresslocations3FFEand3FFFarenotusedasmailboxes,butaspart
of the random access memory. Refer to Truth Table II for the interrupt
operation.
The IDT70P264/254/244provides twoports withseparate control,
address andI/Opins thatpermitindependentaccess toanylocationin
memory.TheIDT70P264/254/244hasanautomaticpowerdownfeature
controlled by CE. The CE controls on-chip power down circuitry that
permitstherespectiveporttogointoastandbymodewhennotselected
(CE HIGH).Whenaportis enabled,access totheentirememoryarray
ispermitted.
PowerSupply
Each port can operate on independent I/O voltages. This is deter-
minedbywhatis connectedtotheVDDIOL andVDDpins. Thesupported
I/O standards are 1.8V/2.5V LVCMOS and 3.0V LVTTL.
TheIDT70P264/254/244includespowersupplyisolationfunctional-
ity which aids system power management. VDD and VDDIOL can be
independentlypoweredup/downwhichallowstheleft portortherightport
andcoretobepowereddownwhennotinuse. IfVDDIOL ispowereddown,
butVDD remainspoweredupallinputstothecorefromtheleftportwillbe
forcedtodeassertedstatesatfullswingDCvaluestominimizeleakage
currentandactivepowerconsumption. IfVDDispowereddownbutVDDIOL
remainpoweredup,alloutputsfortheleftport willremaininthestatethey
were in prior to power down.
TheinterruptoutputsoftheIDT70P264/254/244shouldbeconnected
to an interrupt power supply (VDDINTX) through an external pull-up
resistor. AslongasVDDINTR >VDDandVDDINTL>VDDQL,therewill
be no current flowing between VDDINTx and VDD/VDDQL.
6.42
13
IDT70P264/254/244L
Datasheet
Low Power 1.8V 16K/8K/4K x 16 Dual-Port Static RAM
Industrial Temperature Range
Ordering Information
A
XXXXX
A
999
A
A
Device
Type
Power Speed Package
Process/
Temperature
Range
Industrial (-40°C to +85°C)
I
Green
G
81 Ball 0.5mm-pitch BGA(BY81)
BY
40
55
Industrial Only
Low Power
Speed in nanoseconds
L
70P264
70P254
70P244
256K (16K x 16) 1.8V Dual-Port SRAM
128K (8K x 16) 1.8V Dual-Port SRAM
64K (4K x 16) 1.8V Dual-Port SRAM
7148 drw 10
DatasheetDocumentHistory
09/26/08:
02/20/09:
InitialDatasheet
RemovedPreliminarystatusfromentiredatasheet
Page 14 Removed "IDT" from orderable part number
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6.42
14
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