70P265L90BYI [IDT]
Application Specific SRAM, 16KX16, 90ns, CMOS, PBGA100, 0.50 MM PITCH, BGA-100;
| 型号： | 70P265L90BYI |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Application Specific SRAM, 16KX16, 90ns, CMOS, PBGA100, 0.50 MM PITCH, BGA-100 静态存储器 内存集成电路 |
| 文件： | 总22页 (文件大小：146K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT70P265/255/245L
VERY LOW POWER 1.8V
16K/8K/4K X 16 DUAL-PORT
STATIC RAM
Features
◆
◆
True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
One port with dedicated time-muliplexed address/data
(ADM) interface
Power supply isolation functionality to aid system power
management
Separate upper-byte and lower-byte control
Supports 3.0V, 2.5V and 1.8V I/O's
Input Read Register
Output Drive Register
BUSY and Interrupt Flag
On-chip port arbitration logic
Fully asynchronous operation from either port
Available in 100 Ball 0.5mm-pitch BGA
Industrial temperature range (-40°C to +85°C)
Green parts available, see ordering information
◆
◆
◆
◆
◆
◆
◆
◆
◆
◆
◆
◆
◆
One port configurable to standard SRAM or time-multi-
plexed address/data interface
High-speed access
– Industrial: 65ns (max.), ADM mode
– Industrial: 40ns (max.), Standard SRAM mode
Low-power operation
◆
IDT70P265/255/245L
Active:27mW(typ.)
Standby:3.6µW(typ.)
Functional Block Diagram
IRR1 – IRR0 (2)
ODR4 – ODR0
SFEN
IRR/ODR
I/O15L – I/O8L
Data <15..0>
I/O7L – I/O0L
I/O15R – I/O8R
Data <15..0>
I/O7R – I/O0R
Mux’ed
Mux’ed
Address /
Memory Array
Address /
Data
I/O Control
16K/8K/4K x 16
Data
I/O Control
ADVL
ADVR
UBR
LBR
AddrL <13..0>
AddrR <13..0>
UBL
LBL
A13R – A0R
Address
Decode
Address
Decode
MSEL
CSL
OEL
CSR
Control Logic
OER
WEL
WER
BUSYR
INTR
BUSYL
INTL
7145 drw 01
NOTES:
1. A13 - A0 for IDT70P265; A12 - A0 for IDT70P255; A11 - A0 for IDT70P245.
2. IRR0 and IRR1 are not available for IDT70P265.
OCTOBER 2008
1
DSC-7145/1
©2008IntegratedDeviceTechnology,Inc.
IDT70P265/255/245L
Low Power 16K/8K/4K x 16 Dual-Port Static RAM
Industrial Temperature Range
Description
Fabricated using IDT’s CMOS high-performance technology,
thesedevices typicallyoperateononly27mWofpower.
TheIDT70P265/255/245ispackagedina100ball0.5mm-pitch
BallGridArray.Thepackageisa1mmthickanddesignedtofitinwireless
handsetapplications.
The IDT70P265/255/245 is a very low power 16K/8K/4K x 16
Dual-PortStaticRAM.TheIDT70P265/255/245isdesignedtobeused
asastand-alone256/128/64K-bitDual-PortSRAM.
Thisdeviceprovidestwoindependentportswithseparatecontrol,
address,andI/Opinsthatpermitindependent,asynchronousaccessfor
reads or writes to any location in memory. An automatic power down
featurecontrolledbyCSpermitstheon-chipcircuitryofeachporttoenter
a very low standby power mode.
PinConfigurations(2,3)
70P265/255/245BY
BY-100
100-Ball 0.5mm Pitch BGA
Top View
1
2
3
4
5
6
7
8
9
10
VSS
A5R
A3R
A0R
A8R
A4R
A1R
A11R
A7R
A2R
UBR
A9R
A6R
VSS
CSR
ADVR I/O15R I/O12R I/O10R
A
B
C
D
E
F
A
B
C
D
E
F
WER
OER VDDIOR I/O9R
I/O6R
VSS
(1)
(3)
LBR IRR1
I/O14R I/O11R I/O7R
ODR4 ODR2 BUSYR INTR
DNU(4) ODR3
A10R A12R
I/O13R I/O8R
I/O5R
I/O2R
VSS
VSS
INTL
VSS
VSS
I/O4R VDDIOR I/O1R
SFEN ODR1 BUSYL DNU(4) VDD
ODR0 DNU(4) DNU(4) DNU(4) OEL
VSS
I/O3R
I/O0R I/O15L VDDIOL
I/O3L
I/O11L I/O12L I/O14L I/O13L
G
H
J
G
H
J
DNU(4) DNU(4) DNU(4)
DNU(4) DNU(4) DNU(4) IRR0
DNU(4) DNU(4) DNU(4) UBL
LBL
CSL
VDD
I/O1L VDDIOL MSEL DNU(4) I/O10L
(2)
VSS
I/O4L
I/O0L
I/O6L
I/O2L
I/O8L
I/O5L
I/O9L
I/O7L
ADVL
WEL
K
K
1
2
3
4
5
6
7
8
9
10
7145 drw 02
NOTES:-
1. This pin is A13R for IDT70P265.
2. This pin is DNU for IDT70P265.
3. This pin is DNU for IDT70P245.
4. DNU pins are "do not use". No trace or power component can be connected to these pins.
6.42
2
OCTOBER16,2008
IDT70P265/255/245L
Low Power 16K/8K/4K x 16 Dual-Port Static RAM
Industrial Temperature Range
PinNames
Left Port
Right Port
Description
Chip Select (Input)
CS
WE
OE
L
CS
WE
OE
R
Read/Write Enable (Input)
Output Enable (Input)
L
R
L
R
(1)
A0R - A13R
Address (Input)
(2)
MSEL
Mode Select (Input)
Address/Data (Input/Output)
Address Latch Enable (Input)
Upper Byte Enable (Input)
Lower Byte Enable (Input)
Interrupt Flag (Output)
I/O0L - I/O15L
ADV
UB
LB
INT
BUSY
I/O0R - I/O15R
(3)
L
ADV
UB
LB
INT
BUSY
SFEN
IRR
- IRR (4)
ODR - ODR
R
L
R
NOTES:
L
R
1. A13 - A0 for IDT70P265; A12 - A0 for IDT70P255; A11 - A0 for IDT70P245.
2. MSEL = 0 for Standard SRAM operation, MSEL = 1 for Address/Data Mux
(ADM) operation.
L
R
Busy Flag (Output)
L
R
3. ADVR is only used when the right port is in ADM mode.
Special Function Enable (Input)
Input Read Register (Inputs)
Output Drive Register (Outputs)
Core Power Supply (Input)
Ground (Input)
4. IRR0 is DNU and IRR1 is A13R for 70P265.
0
1
0
4
VDD
VSS
VDDIO
L
Left Port Power Supply (Input)
Right Port Power Supply (Input)
Do Not Use
VDDIO
R
DNU
7145 tbl 01
Truth Table I: ADM Interface Read/Write Control
Inputs
Outputs
I/O0 - I/O15
High-Z
Mode
Deselected/Power Down
ADV
X
CS
H
X
X
L
WE
X
OE
X
H
X
L
UB
X
X
H
L
LB
X
X
H
L
X
X
High-Z
Output Disable
X
X
High-Z
Upper and Lower Bytes Deselected
Pulse
H
DATAOUT (I/O
0
- I/O15) Read Upper and Lower Bytes
- I/O
DATAOUT (I/O0
High-Z (I/O - I/O15
7)
Pulse
L
H
L
H
L
8
)
Read Lower Byte Only
High-Z (I/O0 - I/O7)
DATAOUT (I/O8 - I/O15) Read Upper Byte Only
Pulse
Pulse
Pulse
L
L
L
H
L
L
L
X
X
L
L
H
H
L
L
DATAIN (I/O
0
- I/O15
)
Write Upper and Lower Bytes
DATAIN (I/O
0
8
- I/O
7
)
High-Z (I/O
- I/O15
)
Write Lower Byte Only
High-Z (I/O
0
8
- I/O
7
)
Pulse
L
L
X
L
H
DATAIN (I/O
- I/O15
)
Write Upper Byte Only
7145 tbl 02a
OCTOBER16,2008
6.42
3
IDT70P265/255/245L
Low Power 16K/8K/4K x 16 Dual-Port Static RAM
Industrial Temperature Range
Truth Table II: Standard SRAM Interface Read/Write Control
Inputs
OE
X
Outputs
I/O0 - I/O15
High-Z
Mode
Deselected/Power Down
CS
H
X
X
L
WE
X
UB
X
X
H
L
LB
X
X
H
L
X
H
High-Z
Output Disable
X
X
High-Z
Upper and Lower Bytes Deselected
H
L
DATAOUT (I/O
0
- I/O15) Read Upper and Lower Bytes
- I/O
DATAOUT (I/O0
High-Z (I/O - I/O15
7)
)
L
H
L
H
L
8
Read Lower Byte Only
High-Z (I/O0 - I/O7)
DATAOUT (I/O8 - I/O15) Read Upper Byte Only
L
L
L
H
L
L
L
X
X
L
L
H
H
L
L
DATAIN (I/O
0
- I/O15
)
Write Upper and Lower Bytes
DATAIN (I/O
0
8
- I/O
7
)
High-Z (I/O
- I/O15
)
Write Lower Byte Only
High-Z (I/O
DATAIN (I/O
0
8
- I/O
- I/O15
7
)
)
L
L
X
L
H
Write Upper Byte Only
7145 tbl 02b
AbsoluteMaximumRatings(1)
Commercial
& Industrial
Symbol
Rating
Unit
(2)
V
TERM
Terminal Voltage with
Respect to GND
-0.5 to VDDIOX +0.5
V
(3)
BIAS
T
Temperature Under Bias
-55 to +125
-65 to +150
+150
oC
oC
T
STG
JN
OUT
NOTES:
Storage Temperature
Junction Temperature
oC
T
I
DC Output Current
20
mA
7145 tbl 03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage
to the device. This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VTERM must not exceed VDDIOX + 0.5V for more than 25% of the cycle time or 10ns maximum, and is limited
to < 20mA for the period over VTERM = VDDIOX + 0.5V.
3. Ambient Temperature under DC Bias. No AC Conditions. Chip Deselected.
6.42
4
OCTOBER16,2008
IDT70P265/255/245L
Low Power 16K/8K/4K x 16 Dual-Port Static RAM
Industrial Temperature Range
Capacitance
MaximumOperatingTemperature
andSupplyVoltage(1)
(TA = +25°C, f = 1.0MHz)
Symbol
Parameter
Input Capacitance
Output Capacitance
Conditions(2)
IN = 3dV
OUT = 3dV
Max. Unit
Grade
Ambient
Temperature
GND
VDD
CIN
V
9
pF
1.8V
2.5V
3.0V
+
+
+
100mV
100mV
300mV
COUT
V
10
pF
Industrial
-40OC to +85OC
0V
7145 tbl 05
NOTES:
1. This parameter is determined by device characterization but is not production NOTE :
7145 tbl 04
tested.
1. This is the parameter TA. This is the "instant on" case temperature.
2. 3dV references the interpolated capacitance when the input and output signals
switch from 0V to 3V or from 3V to 0V.
DC Electrical Characteristics Over the Operating and
TemperatureandSupply VoltageRange(VDD =1.8V)
70P265/255/245
Ind'l Only
P1 I/O
Voltage Voltage
P2 I/O
Min.
DDIO - 0.2
2.0
Typ.
Max.
Unit
V
Symbol
Parameter
___
___
Output High Voltage (I
0
0
0
H
H
H
= -100 µA)
= -2 mA)
= -2 mA)
1.8V (any port)
V
___
___
___
___
___
___
___
___
___
___
___
___
___
___
___
___
___
Output High Voltage (I
Output High Voltage (I
2.5V (any port)
3.0V (any port)
1.8V (any port)
2.5V (any port)
3.0V (any port)
1.8V (any port)
2.5V (any port)
3.0V (any port)
1.8V (any port)
2.5V (any port)
3.0V (any port)
1.8V (any port)
2.5V (any port)
3.0V (any port)
V
2.1
V
V
V
V
V
V
OH
___
Output Low Voltage (I
Output Low Voltage (I
Output Low Voltage (I
0
L
= 100 µA)
= 2 mA)
= 2 mA)
0.2
V
___
___
___
___
___
0
L
L
0.4
V
0
0.4
V
OL
0.2
V
0.2
V
0.2
V
OL ODR
ODR Output Low Voltage (I
Input High Voltage
0L = 8 mA)
1.2
1.7
2.0
-0.2
-0.3
-0.2
-1
V
V
V
DDIO + 0.2
V
DDIO+ 0.3
V
DDIO + 0.2
V
IH
0.4
0.6
0.7
1
V
V
V
IL
Input Low Voltage
1.8V
2.5V
1.8V
2.5V
___
___
___
___
___
-1
1
3.0V
1.8V
3.0V
1.8V
-1
-1
1
1
µA
µA
I
I
OZ
Output Leakage Current
2.5V
3.0V
2.5V
3.0V
-1
-1
1
1
ODR Output Leakage Current
VOUT = VDDIO
CEX ODR
___
___
___
1.8V
2.5V
3.0V
1.8V
2.5V
3.0V
-1
-1
-1
1
1
1
µA
I
IX
Input Leakage Current
7145 tbl 06
OCTOBER16,2008
6.42
5
IDT70P265/255/245L
Low Power 16K/8K/4K x 16 Dual-Port Static RAM
Industrial Temperature Range
DC Electrical Characteristics Over the Operating and
TemperatureandSupplyVoltageRange(VDD =2.5V)
70P265/255/245
Ind'l Only
P1 I/O
Voltage Voltage
P2 I/O
Min.
Typ.
Max.
Unit
V
Symbol
Parameter
___
___
Output High Voltage (I
0
H
H
= -2 mA)
= -2 mA)
2.5V (any port)
2.0
___
___
___
___
___
___
___
___
___
___
V
V
V
V
V
OH
Output High Voltage (I
0
3.0V (any port)
2.5V (any port)
3.0V (any port)
2.5V (any port)
3.0V (any port)
2.5V (any port)
3.0V (any port)
2.5V (any port)
3.0V (any port)
2.1
V
___
Output Low Voltage (I
0
L
= 2 mA)
= 2 mA)
0.4
0.4
0.2
0.2
V
___
___
___
OL
Output Low Voltage (I
0
L
V
V
OL ODR
ODR Output Low Voltage (I
Input High Voltage
0L
= 8 mA)
V
1.7
2.0
V
DDIO+ 0.3
DDIO + 0.2
0.6
V
V
V
V
IH
IL
V
-0.3
-0.2
Input Low Voltage
0.7
___
___
2.5V
3.0V
2.5V
3.0V
-1
-1
1
1
µA
µA
I
OZ
Output Leakage Current
___
___
2.5V
3.0V
2.5V
3.0V
-1
-1
1
1
ODR Output Leakage Current
VOUT = VDDIO
ICEX ODR
___
___
2.5V
3.0V
2.5V
3.0V
-1
-1
1
1
IIX
Input Leakage Current
µA
7145 tbl 07
DC Electrical Characteristics Over the Operating and
TemperatureandSupplyVoltageRange(VDD =3.0V)
70P265/255/245
Ind'l Only
P1 I/O
Voltage Voltage
P2 I/O
Min.
Typ.
Max.
Unit
V
Symbol
Parameter
___
___
V
V
V
V
V
OH
Output High Voltage (I
0
H
= -2 mA)
= 2 mA)
= 8 mA)
3.0V (any port)
2.1
___
___
___
___
OL
Output Low Voltage (I
0
L
3.0V (any port)
3.0V (any port)
3.0V (any port)
3.0V (any port)
0.4
0.2
V
___
OL ODR
ODR Output Low Voltage (I
Input High Voltage
0L
V
IH
IL
2.0
V
DDIO + 0.2
V
___
___
Input Low Voltage
-0.2
-1
0.7
1
V
IOZ
Output Leakage Current
3.0V
3.0V
µA
ODR Output Leakage Current
___
___
V
OUT = VDDIO
µA
I
CEX ODR
3.0V
3.0V
3.0V
3.0V
-1
-1
1
1
IIX
Input Leakage Current
µA
7145 tbl 08
6.42
6
OCTOBER16,2008
IDT70P265/255/245L
Low Power 16K/8K/4K x 16 Dual-Port Static RAM
Industrial Temperature Range
DC Electrical Characteristics Over the Operating and
TemperatureandSupplyVoltageRange
70P265/255/245
Ind'l Only
65 ns
90 ns
Typ.
Symbol
Parameter
Test Condition (1)
VDD
1.8V
2.5V
3.0V
1.8V
2.5V
3.0V
1.8V
2.5V
3.0V
1.8V
2.5V
3.0V
1.8V
2.5V
3.0V
Typ.
25
39
49
2
Max.
Max.
25
40
60
6
Unit
mA
µA
mA
µA
40
55
70
6
15
28
42
2
IDD
Dynamic Operating Current
VDD = MAX, IOUT = 0mA
CS
0.2V, MSEL < 0.2V or >
R
and CSL > VDDIO -
6
8
6
8
Standby Current (Both Ports
Inactive)
V
DDIO - 0.2V,
f = fMAX
ISB1
7
10
18
30
40
6
7
10
14
25
35
6
8.5
21
28
2
8.5
18
25
2
Standby Current (One Port
Active, One Port Inactive)
CS
R
or CSL > VDDIO - 0.2V,
f = fMAX
ISB2
CS
0.2V, MSEL < 0.2V or >
R
and CSL > VDDIO -
Full Standby Current (Both
Ports Inactive - CMOS Level
Inputs)
4
6
4
6
V
DDIO - 0.2V,
f = 0
ISB3
6
8
6
8
8.5
21
28
18
30
40
8.5
18
25
14
25
35
Standby Current (One Port
Active, One Port Inactive -
CMOS Level Inputs)
CS
L
or CS
f = fMAX
R > VDDIO - 0.2V,
ISB4
mA
7145 tbl 09
NOTE :
1. fMAX = 1/tRC = All inputs cycling at f = 1/tRC (except output enable). f=0 means no address or control lines change. This applied only to inputs at CMOS
level standby ISB3.
OCTOBER16,2008
6.42
7
IDT70P265/255/245L
Low Power 16K/8K/4K x 16 Dual-Port Static RAM
Industrial Temperature Range
AC Test Conditions
Input Pulse Levels
GND to 3.0V/GND to 2.5V/GND to 1.8V
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
3ns Max.
1.5V/1.25V/0.9V
1.5V/1.25V/0.9V
Figure 1
7145 tbl 10
3.0V/2.5V/1.8V
R1
3.0V/2.5V
1022Ω
1.8V
R1
R2
13500Ω
729Ω
10800Ω
R2
7145 tbl 11
(1)
30pF
7145 drw 03
Figure 1. AC Output Test Load
(5pF for tLZ, tHZ, tWZ, tOW)
Timing of Power-Up Power-Down
CS
t
PU
t
PD
I
DD
50%
50%
I
SB
,
7145 drw 04
6.42
8
OCTOBER16,2008
IDT70P265/255/245L
Low Power 16K/8K/4K x 16 Dual-Port Static RAM
Industrial Temperature Range
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltageRange(1)
70P265/255/245
65 ns
90 ns
Symbol
Parameter
Min.
Max.
Min.
Max..
Unit
(2)
ADM Port Read Cycle
____
____
t
RC
ACC1
ACC2
ACC3
AVDA
AVD
AVDS
AVDH
CSS
OE
Read Cycle Time
65
90
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
____
____
t
Random Access ADV Low to Data Valid
Random Access Address to Data Valid
Random Access CS to Data Valid
Random Access ADV High to Data Valid
ADV Low Pulse
65
65
65
90
90
90
____
____
____
____
____
____
t
t
t
35
50
____
____
t
15
15
3
20
20
5
____
____
____
____
____
____
t
Address Set-up to ADV Rising Edge
Address Hold from ADV Rising Edge
CS Set-up to ADV Rising Edge
OE Low to Data Valid
t
t
7
10
____
____
t
35
50
(3)
____
____
tLZOE
3
5
OE Low to I/O Low-Z
(3)
____
____
tHZOE
15
15
25
25
OE High to I/O High-Z
(3)
____
____
____
____
tHZCS
CS High to I/O High-Z
tDBE
35
50
UB/LB Low to I/O Valid
(3)
(3)
____
____
tLZBE
3
5
UB/LB Low to I/O Low-Z
____
____
t
HZBE
AVOE
PU
PD
15
25
UB/LB High to I/O High-Z
____
____
t
0
0
ADV High to OE Low
____
____
t
Chip Enable to Power Up Time
0
0
____
____
t
Chip Disable to Power Down Time
65
90
(4)
Standard Port Read Cycle
____
____
t
RC
AA
OHA
ACS
DOE
Read Cycle Time
40
60
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
____
____
t
Address to Data Valid
Output Hold from Address Change
CS to Data Valid
40
60
____
____
t
5
5
____
____
t
40
60
____
____
t
25
35
OE Low to Data Valid
OE Low to Data Low-Z
OE High to Data High-Z
CS Low to Data Low-Z
CS Low to Data High-Z
UB/LB Low to Data Low-Z
UB/LB High to Data High-Z
UB/LB Access Time
(3)
(3)
____
____
tLZOE
5
5
____
____
tHZOE
10
30
(3)
(3)
(3)
(3)
____
____
tLZCS
5
5
____
____
tHZCS
30
10
____
____
tLZBE
5
5
____
____
tHZBE
30
60
10
40
____
____
tABE
ns
7145 tbl 12
NOTES:
1. VDD = 1.8V
2. ADM port timing applies to left ADM port and right port configured to ADM mode.
3. This parameter is guaranteed by design and is not tested.
4. Standard SRAM port timing applies to right port configured to standard SRAM mode.
OCTOBER16,2008
6.42
9
IDT70P265/255/245L
Low Power 16K/8K/4K x 16 Dual-Port Static RAM
Industrial Temperature Range
ADM Port Read Cycle (Either Port Access, WE High)
tACC2
tAVDS
tAVDH
I/O [15:0]
Valid Address
Valid Data
tACC1
tAVD
tAVDA
ADV
tACC3
tCSS
tHZCS
CS
tAVOE
tOE
tHZOE
OE
WE
tLZBE
tDBE
tHZBE
UB, LB
7145 drw 05
Standard Port Read Cycle (Right Port Access, WE High)
tRC
tAA
tOHA
Address
Valid Address
tACS
tLZCS
tHZCS
CS
tDOE
tLZOE
tHZOE
OE
WE
tABE
tLZBE
tHZBE
UB, LB
Data Out
Valid Data
6.42
10
OCTOBER16,2008
IDT70P265/255/245L
Low Power 16K/8K/4K x 16 Dual-Port Static RAM
Industrial Temperature Range
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltageRange(1)
70P265/255/245
65 ns
90 ns
Symbol
Parameter
Min.
Max.
Min.
Max..
Unit
(2)
ADM Port Write Cycle
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
WC
SCS
AVD
AVDS
AVDH
CSS
WRL
BW
SD
HD
Write Cycle Time
65
65
15
15
3
90
90
20
20
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
CS Low to Write End
t
ADV Low Pulse
t
Address Set-up to ADV Rising Edge
Address Hold from ADV Rising Edge
CS Set-up to ADV Rising Edge
WE Pulse Width
t
t
7
10
45
45
30
0
t
28
28
20
0
t
UB/LB Low to Write End
Data Set-up to Write End
Data Hold from Write End
WE High to I/O Low-Z
t
t
(3)
LZWE
t
0
0
tAVWE
0
0
ADV High to WE Low
____
____
tWODR
Write End to ODR Valid
40
60
(4)
Standard Port Write Cycle
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
WC
SCS
AW
HA
SA
WRL
SD
HD
HZWE
Write Cycle Time
40
30
30
0
60
50
50
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
CS Low to Write End
t
Address Valid to Write End
Address Hold to Write End
Address Set-up to Write Start
Write Pulse Width
t
t
0
0
t
25
20
45
30
t
Data Set-up to Write End
Data Hold from Write End
WE Low to Data High-Z
WE High to Data Low-Z
Write End to ODR Valid
t
0
0
(3)
____
____
t
15
25
(3)
LZWE
____
____
t
0
0
____
____
tWODR
40
60
ns
7145 tbl 13
NOTES:
1. VDD = 1.8V
2. ADM port timing applies to left ADM port and right port configured to ADM mode.
3. This parameter is guaranteed by design and is not tested.
4. Standard SRAM port timing applies to right port configured to standard SRAM mode.
OCTOBER16,2008
6.42
11
IDT70P265/255/245L
Low Power 16K/8K/4K x 16 Dual-Port Static RAM
Industrial Temperature Range
ADM Port Write Cycle (Either Port Access, WE Controlled, OE High)
tAVDS
tAVDH
tSD
tHD
I/O [15:0]
Addr1<15..0>
WData1<15..0>
tAVD
ADV
tSCS
tCSS
CS
OE
tAVWE
tWRL
WE
tBW
UB, LB
ADM Port Write Cycle (Either Port Access, CS Controlled, OE High)
tAVDS
tAVDH
tSD
tHD
I/O [15:0]
Addr1<15..0>
WData1<15..0>
tAVD
ADV
tSCS
tCSS
CS
OE
tAVWE
tWRL
WE
tBW
UB, LB
6.42
12
OCTOBER16,2008
IDT70P265/255/245L
Low Power 16K/8K/4K x 16 Dual-Port Static RAM
Industrial Temperature Range
Standard Port Write Cycle (Right Port Access, WE Controlled)
tWC
tAW
Address
Valid Address
tSA
tHA
CS
OE
tWRL
tHZWE
tLZWE
WE
tBW
UB, LB
tSD
tHD
Data
Valid Data
Standard Port Write Cycle (Right Port Access, CS Controlled)
tWC
tAW
Address
Valid Address
tHA
tSA
tSCS
tLZCS
CS
OE
tWRL
tHZWE
WE
tBW
UB, LB
tSD
tHD
Data
Valid Data
OCTOBER16,2008
6.42
13
IDT70P265/255/245L
Low Power 16K/8K/4K x 16 Dual-Port Static RAM
Industrial Temperature Range
AC Electrical Characteristics Over the
Operating TemperatureandSupplyVoltageRange(1)
70P265/255/245
65 ns
90 ns
Symbol
Parameter
Min.
Max.
Min.
Max..
Unit
Arbitration Timing
____
____
____
____
____
____
____
____
t
BLA
BHA
BLC
30
30
30
50
50
50
ns
ns
ns
ns
ns
ns
ns
BUSY Low from Address Match
BUSY High from Address Match
BUSY Low from CS Low
t
t
tBHC
30
50
BUSY High from CS High
Port Set-up Priority
(2)
____
____
tPS
5
5
____
____
30
55
45
50
85
70
t
BDD
WDD
DDD
BUSY High to Data Valid
____
____
____
____
t
Write Pulse to Data Delay
Write Data Valid to Read Data Valid
t
ns
7145 tbl 14
NOTES:
1. VDD = 1.8V.
2. Add 2 ns to this parameter if VDD and VDDIOR are <1.8V, and VDDIOL is >2.5V at temperature <0OC.
Arbitration Timing
Address
Address Match
CSR
tPS
CSL
tBLC
tBHC
BUSYL
6.42
14
OCTOBER16,2008
IDT70P265/255/245L
Low Power 16K/8K/4K x 16 Dual-Port Static RAM
Industrial Temperature Range
Arbitration Timing
(Address Controlled with Left ADM and Right STD Configuration)
Left Address Valid First
A0
I/OL [15:0]
ADVL
tAVDH
AddressL
(Internal)
A0
tPS
AddressR
A0
A1
tBLA
tBHA
BUSYR
Right Address Valid First
I/OL [15:0]
A
0
Data
A
1
ADVL
tAVDH
tAVDH
AddressL
(Internal)
A0
A1
tPS
AddressR
A0
tBHA
tBLA
BUSYL
OCTOBER16,2008
6.42
15
IDT70P265/255/245L
Low Power 16K/8K/4K x 16 Dual-Port Static RAM
Industrial Temperature Range
Arbitration Timing
(Address Controlled with Left ADM and Right ADM Configuration)
ADVL
tAVDH
tAVDH
Address L
(Internal)
Mismatch
tPS
ADVR
tAVDH
Address R
(Internal)
Address Match
tBLA
tBHA
BUSYR
Read with BUSY Timing
I/OL [15:0]
Valid Address
Data
Valid Address
ADVL
WEL
AddressR
Address Match
BUSYR
tBDD
tDDD
Valid
Data
Data OutR
tWDD
6.42
16
OCTOBER16,2008
IDT70P265/255/245L
Low Power 16K/8K/4K x 16 Dual-Port Static RAM
Industrial Temperature Range
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltageRange(1)
70P265/255/245
65 ns
90 ns
Symbol
Parameter
Min.
Max.
Min.
Max..
Unit
Interrupt Timing
____
____
____
____
t
INS
35
35
55
55
ns
INT Set Time
tINR
ns
INT Reset Time
7145 tbl 15
NOTE:
1. VDD = 1.8V
Interrupt Timing
Left Port Writes to Right Mailbox Setting INTR
I/OL [15:0]
Right Mailbox Address
Write Data
tHD
OEL
CSL
WEL
tINS
INTR
Right Port Reads Right Mailbox Clearing INT R
AddressR
Right Mailbox Address
CSR
OER
WER
tINR
INTR
OCTOBER16,2008
6.42
17
IDT70P265/255/245L
Low Power 16K/8K/4K x 16 Dual-Port Static RAM
Industrial Temperature Range
Truth Table III — Interrupt Flag(1)
Left Port
Right Port
OE
A
13L-A0L
A
13R-A0R
Function
Set Right INT Flag
Reset Right INT Flag
Set Left INT Flag
Reset Left INT Flag
WE
L
CS
L
OE
L
INT
X
L
WE
X
CS
X
L
R
INTR
X
X
X
L
3FFF(2)
X
X
L
X
L
R
X
X
X
L
X
X
3FFF(2)
3FFE(3)
X
H
X
X
R
X
X
L
L
L
X
X
L
X
3FFE(3)
H
X
X
L
7145 tbl 16
NOTES:
1. Assumes BUSYL = BUSYR = VIH.
2. 3FFF for 70P265, 1FFF for 70P255, FFF for 70P245.
3. 3FFE for 70P265, 1FFE for 70P255, FFE for 70P245.
Truth Table IV —
Address BUSY Arbitration
Inputs
Outputs
Address Match
Function
Normal
Normal
Normal
CS
L
CS
R
BUSY
H
L
BUSYR
Left/Right Port
NO MATCH
MATCH
X
H
X
L
X
X
H
L
H
H
H
MATCH
H
H
MATCH
(1)
(1)
Write Inhibit(2)
7145 tbl 17
NOTES:
1. L if the inputs to the opposite port were stable prior to the address and enable inputs of this port. H if the inputs to the opposite port became stable after the address
and enable inputs of this port. If tPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs cannot be LOW simultaneously.
2. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored
when BUSYR outputs are driving LOW regardless of actual logic level on the pin.
6.42
18
OCTOBER16,2008
IDT70P265/255/245L
Low Power 16K/8K/4K x 16 Dual-Port Static RAM
Industrial Temperature Range
Truth Table V — Input Read Register Operation(3)
ADDR
I/O0-I/O1
I/O2-I/O15
Mode
SFEN
H
CS
L
WE
H
OE
L
UB
LB
(1)
(1)
(1)
(1)
L
L
x0000 - Max VALID
VALID
Standard Memory Access
(2)
(4)
L
L
H
L
X
L
x0000
VALID
VALID
IRR Read(3)
7145 tbl 18
NOTES:
1. UB or LB = VIL. If LB = VIL, then I/O0 - I/O7 are VALID. If UB = VIL, then I/O8 - I/O15 are VALID.
2. LB must be active (LB = VIL) for these bits to be valid.
3. SFEN = VIL to activate IRR reads.
4. Valid data bits from memory.
Truth Table VI — Output Drive Register Operation(5)
R/W
H
ADDR
I/O0-I/O4
I/O5-I/O15
Mode
SFEN
H
CE
L
OE
UB
LB
(1)
(2)
(2)
(2)
(2)
X
L
L
x0000 - Max VALID
VALID
Standard Memory Access
ODR Write(4,5)
(3)
(4)
L
L
L
X
L
X
X
L
L
x0001
x0001
VALID
VALID
(3)
(6)
L
L
H
VALID
VALID
ODR Read(5)
7145 tbl 19
NOTES:
1. Output enable must be low (OE = Vil) during reads for valid data to be output.
2. UB or LB = VIL. If LB = VIL, then I/O0 - I/O7 are VALID. If UB = VIL, then I/O8 - I/O15 are VALID.
3. LB must be active (LB = VIL) for these bits to be valid.
4. During ODR writes data will also be written to the memory.
5. SFEN = VIL to activate ODR reads and writes.
6. Valid data bits from memory.
OCTOBER16,2008
6.42
19
IDT70P265/255/245L
Low Power 16K/8K/4K x 16 Dual-Port Static RAM
Industrial Temperature Range
Standard SRAM Interface Read/
Write Operation
FunctionalDescription
The IDT70P265/255/245 are low-power CMOS 16K/8K/4K x 16
dual-portstaticRAMs. Thetwoportsare:onededicatedtime-multiplexed
The description of this section is applicable to the right access port
addressanddata(ADM)interfaceandoneconfigurablestandardSRAM configuredtooperateinStandardSRAMmode. Read/writeoperationwith
orADMinterface. Thetwoportsprovideseparatecontrol,address(right standardSRAMinterfaceconfigurationisthesameastheADMportexcept
portonly),andI/Opinsthatpermitindependent,asynchronousreadand addressesarepresentedontheaddressbus. Operationiscontrolledby
writeaccess toanymemorylocation. TheIDT70P265/255/245has an CS,OEandWE. AreadoperationisissuedwhenWEisassertedHIGH.
automaticpower-downfeaturecontrolledbyCS. TheCScontrolson-chip AwriteoperationisissuedwhenWEisassertedLOW. TheI/Obusisthe
powerdowncircuitrythatpermitstherespectiveporttogointoastandby destinationforreaddataandthesourcedataforwritedatawhentheread
mode whennotselected(CS HIGH).
operationisissued. However,writedataneedstobedriventotheI/Owhen
thewriteoperationisissued.
PowerSupply
Thecorevoltage(VDD)canbe1.8V,2.5Vor3.0V,aslongasitislower
thanorequaltotheI/Ovoltage. Eachportcanoperateonindependent
I/Ovoltages. ThisisdeterminedbywhatisconnectedtotheVDDIOL and
VDDIOR pins. ThesupportedI/Ostandardsare1.8V/2.5VLVCMOSand
3.0V LVTTL.
Interrupts
Iftheuserchoosestheinterruptfunction,amemorylocation(mailbox
ormessagecenter)is assignedtoeachport. Theleftportinterruptflag
(INTL) is asserted when the right port writes to memory location 3FFE
(HEX) (1FFE for IDT70P255 and FFE for IDT70P245), where a write
isdefinedasthe CS=WE=VILperTruthTableIII.Theleftportclearsthe
interruptbyaccessingaddresslocation3FFEwhenCSR=OER=VIL,WE
isa"don'tcare".Likewise,therightportinterruptflag(INTR)isasserted
when the left port writes to memory location 3FFF (HEX) (1FFF for
IDT70P255 and FFF for IDT70P245) and to clear the interrupt flag
(INTR),therightportmustreadthememorylocation3FFF.Themessage
(16bits)at3FFEor3FFFisuser-defined,sinceitisanaddressableSRAM
location.Iftheinterruptfunctionisnotused,addresslocations3FFEand
3FFF are not used as mail boxes, but as part of the random access
memory. RefertoTruthTable IIIforthe interrupt operation.
TheIDT70P265/255/245includespowersupplyisolationfunctional-
itywhichaidssystempowermanagement. VDD,VDDIOR andVDDIOL canall
beindependentlypoweredup/downwhichallowseitherportand/orthe
core to be powered down when not in use. If VDDIOX is powered down,
but VDD remains powered up all inputs to the core will be forced to
deassertedstatesatfullswingDCvaluestominimizeleakagecurrentand
active power consumption. If VDD is powered down but VDDIOX remain
poweredup,alloutputsfortheport(s)inquestionwillremaininthestate
they were in prior to power down.
ADM Interface Read/Write Operation
ThedescriptionofthissectionisapplicabletoboththeleftADMportand
rightportconfiguredinADMmode.
Threecontrolsignals,ADV,WE,andCSareusedtoperformtheread/
writeoperation. AddresssignalsarefirstappliedtotheI/Obusalongwith
CSLOW. TheaddressesareloadedfromtheI/Obusinresponsetothe
risingedge ofthe Address LatchEnable (ADV)signal. Itis necessary
to meet the set-up (tAVDS) and hold (tAVDH) times given in the AC
specificationswithvalidaddressinformationinordertoproperlylatchthe
addresses.
Oncetheaddresssignalsarelatchedin,areadoperationisissued
whenWE staysHIGH. TheI/ObusbecomesHIGH-Zoncetheaddress
signalsmeetingtAVDH. ThereaddataisdrivenontheI/ObustOE afterthe
OEisassertedLOW,andhelduntiltHZOE ortHZCS aftertherisingedgeof
OEorCS,whichevercomes first.
BusyLogic
BusyLogicprovidesahardwareindicationthatbothportsoftheSRAM
haveaccessedthesamelocationatthesametime.Italsoallowsoneofthe
twoaccessestoproceedandsignalstheothersidethattheSRAMis“busy”.
TheBUSYpincanthenbeusedtostalltheaccessuntiltheoperationon
theothersideiscompleted.Ifawriteoperationhasbeenattemptedfrom
thesidethatreceivesaBUSYindication,thewritesignalisgatedinternally
topreventthewritefromproceeding.
TheuseofBUSYlogicisnotrequiredordesirableforallapplications.
InsomecasesitmaybeusefultologicallyORtheBUSYoutputstogether
anduse any BUSYindicationas aninterruptsource toflagthe eventof
anillegalorillogicaloperation.
A write operation is issued when WE is asserted LOW. The write
dataisappliedtotheI/Obusrightafteraddressmeetstheholdtime
(tAVDH). Andwrite data is writtenwiththe risingedge ofeitherWE or
CS,whichevercomes first,andmeets dataset-up(tSD)andhold(tHD)
times.
AwriteoperationisissuedwhenWEisassertedLOW. Thewritedata
isappliedtotheI/Obusrightafteraddressmeetstheholdtime(tAVDH). And
write data is written with the rising edge of either WE or CS, whichever
comesfirst,andmeetsdataset-up(tSD)andhold(tHD)times.
6.42
20
OCTOBER16,2008
IDT70P265/255/245L
Low Power 16K/8K/4K x 16 Dual-Port Static RAM
Industrial Temperature Range
Input Read Register
TheInputReadRegister(IRR)oftheIDT70P265/255/245captures
thestatusoftwoexternalbinaryinputdevicesconnectedtotheInputRead
pins(e.g.DIPswitches).ThecontentsoftheIRRarereadasastandard
memoryaccesstoaddressx0000fromeitherportandthedataisoutput
viathestandardI/Os (TruthTableV). DuringInputRegisterreads I/O0
-I/O1 arevalidbitsandI/O2 -I/O15arereadfromthememory.Writes to
addressx0000arenormalmemoryoperation.WhenSFEN=VIH,theIRR
isinactiveandaddressx0000canbeusedaspartofthemainmemory.
The IRR inputs willbe 1.8V/2.5VLVCMOSor3.0VLVTTL, depending
onthecorevoltagesupply.RefertoTruthTableVforInputReadRegister
operation.
Output Drive Register
TheOutputDriveRegister(ODR)oftheIDT70P265/255/245deter-
minesthestateofuptofiveexternalbinary-statedevicesbyprovidinga
pathtoVSSfortheexternalcircuit.Thefiveexternaldevicessupportedby
theODRcanoperateatdifferentvoltages(1.5V<VSUPPLY <3.5V),butthe
combinedcurrentofthedevicesmustnotexceed40mA(8mAIMAX foreach
externaldevice). The status ofthe ODRbits is setusingstandardwrite
accessesfromeitherporttoaddressx0001witha“1”correspondingto“on“
anda “0”correspondingto“off”. The status ofthe ODRbits canalsobe
read(withoutchangingthestatusofthebits)viaastandardreadtoaddress
x0001. When SFEN = VIL, the ODR is active and address x0001 is not
availableforstandardmemoryoperations.WhenSFEN=VIH,theODR
isinactiveandaddressx0001canbeusedaspartofthemainmemory.
During reads and writes to the ODR I/O0 - I/O4 are valid bits and I/O5 -
I/O15willnotaffecttheODRfunctionbuttheywillreadfromorwritetothe
memory. RefertoTruthTable VIforOutputDrive Registeroperation.
OCTOBER16,2008
6.42
21
IDT70P265/255/245L
Low Power 16K/8K/4K x 16 Dual-Port Static RAM
Industrial Temperature Range
Ordering Information
A
IDT XXXXX
A
999
A
A
Device
Type
Power Speed Package
Process/
Temperature
Range
Industrial (-40°C to +85°C)
I
Green
G
100 Ball 0.5mm-pitch BGA(BY100)
BY
65
90
Industrial Only
Low Power
Speed in nanoseconds
L
70P265
70P255
70P245
256K (16K x 16) Dual-Port SRAM
128K (8K x 16) Dual-Port SRAM
64K (4K x 16) Dual-Port SRAM
7145 drw 16
DatasheetDocumentHistory
10/16/08:
InitialDatasheet
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
800-345-7015 or 408-284-8200
fax: 408-284-2775
for Tech Support:
408-284-2794
DualPortHelp@idt.com
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
6.42
22
OCTOBER16,2008
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SI9122E
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